Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/elinkxl.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /* $NetBSD: elinkxl.c,v 1.79.2.2 2005/10/28 19:46:55 jmc Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: elinkxl.c,v 1.79.2.2 2005/10/28 19:46:55 jmc Exp $"); 41 42 #include "bpfilter.h" 43 #include "rnd.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/callout.h> 48 #include <sys/kernel.h> 49 #include <sys/mbuf.h> 50 #include <sys/socket.h> 51 #include <sys/ioctl.h> 52 #include <sys/errno.h> 53 #include <sys/syslog.h> 54 #include <sys/select.h> 55 #include <sys/device.h> 56 #if NRND > 0 57 #include <sys/rnd.h> 58 #endif 59 60 #include <uvm/uvm_extern.h> 61 62 #include <net/if.h> 63 #include <net/if_dl.h> 64 #include <net/if_ether.h> 65 #include <net/if_media.h> 66 67 #if NBPFILTER > 0 68 #include <net/bpf.h> 69 #include <net/bpfdesc.h> 70 #endif 71 72 #include <machine/cpu.h> 73 #include <machine/bus.h> 74 #include <machine/intr.h> 75 #include <machine/endian.h> 76 77 #include <dev/mii/miivar.h> 78 #include <dev/mii/mii.h> 79 #include <dev/mii/mii_bitbang.h> 80 81 #include <dev/ic/elink3reg.h> 82 /* #include <dev/ic/elink3var.h> */ 83 #include <dev/ic/elinkxlreg.h> 84 #include <dev/ic/elinkxlvar.h> 85 86 #ifdef DEBUG 87 int exdebug = 0; 88 #endif 89 90 /* ifmedia callbacks */ 91 int ex_media_chg(struct ifnet *ifp); 92 void ex_media_stat(struct ifnet *ifp, struct ifmediareq *req); 93 94 void ex_probe_media(struct ex_softc *); 95 void ex_set_filter(struct ex_softc *); 96 void ex_set_media(struct ex_softc *); 97 void ex_set_xcvr(struct ex_softc *, u_int16_t); 98 struct mbuf *ex_get(struct ex_softc *, int); 99 u_int16_t ex_read_eeprom(struct ex_softc *, int); 100 int ex_init(struct ifnet *); 101 void ex_read(struct ex_softc *); 102 void ex_reset(struct ex_softc *); 103 void ex_set_mc(struct ex_softc *); 104 void ex_getstats(struct ex_softc *); 105 void ex_printstats(struct ex_softc *); 106 void ex_tick(void *); 107 108 void ex_power(int, void *); 109 110 static int ex_eeprom_busy(struct ex_softc *); 111 static int ex_add_rxbuf(struct ex_softc *, struct ex_rxdesc *); 112 static void ex_init_txdescs(struct ex_softc *); 113 114 static void ex_shutdown(void *); 115 static void ex_start(struct ifnet *); 116 static void ex_txstat(struct ex_softc *); 117 118 int ex_mii_readreg(struct device *, int, int); 119 void ex_mii_writereg(struct device *, int, int, int); 120 void ex_mii_statchg(struct device *); 121 122 void ex_probemedia(struct ex_softc *); 123 124 /* 125 * Structure to map media-present bits in boards to ifmedia codes and 126 * printable media names. Used for table-driven ifmedia initialization. 127 */ 128 struct ex_media { 129 int exm_mpbit; /* media present bit */ 130 const char *exm_name; /* name of medium */ 131 int exm_ifmedia; /* ifmedia word for medium */ 132 int exm_epmedia; /* ELINKMEDIA_* constant */ 133 }; 134 135 /* 136 * Media table for 3c90x chips. Note that chips with MII have no 137 * `native' media. 138 */ 139 struct ex_media ex_native_media[] = { 140 { ELINK_PCI_10BASE_T, "10baseT", IFM_ETHER|IFM_10_T, 141 ELINKMEDIA_10BASE_T }, 142 { ELINK_PCI_10BASE_T, "10baseT-FDX", IFM_ETHER|IFM_10_T|IFM_FDX, 143 ELINKMEDIA_10BASE_T }, 144 { ELINK_PCI_AUI, "10base5", IFM_ETHER|IFM_10_5, 145 ELINKMEDIA_AUI }, 146 { ELINK_PCI_BNC, "10base2", IFM_ETHER|IFM_10_2, 147 ELINKMEDIA_10BASE_2 }, 148 { ELINK_PCI_100BASE_TX, "100baseTX", IFM_ETHER|IFM_100_TX, 149 ELINKMEDIA_100BASE_TX }, 150 { ELINK_PCI_100BASE_TX, "100baseTX-FDX",IFM_ETHER|IFM_100_TX|IFM_FDX, 151 ELINKMEDIA_100BASE_TX }, 152 { ELINK_PCI_100BASE_FX, "100baseFX", IFM_ETHER|IFM_100_FX, 153 ELINKMEDIA_100BASE_FX }, 154 { ELINK_PCI_100BASE_MII,"manual", IFM_ETHER|IFM_MANUAL, 155 ELINKMEDIA_MII }, 156 { ELINK_PCI_100BASE_T4, "100baseT4", IFM_ETHER|IFM_100_T4, 157 ELINKMEDIA_100BASE_T4 }, 158 { 0, NULL, 0, 159 0 }, 160 }; 161 162 /* 163 * MII bit-bang glue. 164 */ 165 u_int32_t ex_mii_bitbang_read(struct device *); 166 void ex_mii_bitbang_write(struct device *, u_int32_t); 167 168 const struct mii_bitbang_ops ex_mii_bitbang_ops = { 169 ex_mii_bitbang_read, 170 ex_mii_bitbang_write, 171 { 172 ELINK_PHY_DATA, /* MII_BIT_MDO */ 173 ELINK_PHY_DATA, /* MII_BIT_MDI */ 174 ELINK_PHY_CLK, /* MII_BIT_MDC */ 175 ELINK_PHY_DIR, /* MII_BIT_DIR_HOST_PHY */ 176 0, /* MII_BIT_DIR_PHY_HOST */ 177 } 178 }; 179 180 /* 181 * Back-end attach and configure. 182 */ 183 void 184 ex_config(sc) 185 struct ex_softc *sc; 186 { 187 struct ifnet *ifp; 188 u_int16_t val; 189 u_int8_t macaddr[ETHER_ADDR_LEN] = {0}; 190 bus_space_tag_t iot = sc->sc_iot; 191 bus_space_handle_t ioh = sc->sc_ioh; 192 int i, error, attach_stage; 193 194 callout_init(&sc->ex_mii_callout); 195 196 ex_reset(sc); 197 198 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR0); 199 macaddr[0] = val >> 8; 200 macaddr[1] = val & 0xff; 201 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR1); 202 macaddr[2] = val >> 8; 203 macaddr[3] = val & 0xff; 204 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR2); 205 macaddr[4] = val >> 8; 206 macaddr[5] = val & 0xff; 207 208 aprint_normal("%s: MAC address %s\n", sc->sc_dev.dv_xname, 209 ether_sprintf(macaddr)); 210 211 if (sc->ex_conf & (EX_CONF_INV_LED_POLARITY|EX_CONF_PHY_POWER)) { 212 GO_WINDOW(2); 213 val = bus_space_read_2(iot, ioh, ELINK_W2_RESET_OPTIONS); 214 if (sc->ex_conf & EX_CONF_INV_LED_POLARITY) 215 val |= ELINK_RESET_OPT_LEDPOLAR; 216 if (sc->ex_conf & EX_CONF_PHY_POWER) 217 val |= ELINK_RESET_OPT_PHYPOWER; 218 bus_space_write_2(iot, ioh, ELINK_W2_RESET_OPTIONS, val); 219 } 220 if (sc->ex_conf & EX_CONF_NO_XCVR_PWR) { 221 GO_WINDOW(0); 222 bus_space_write_2(iot, ioh, ELINK_W0_MFG_ID, 223 EX_XCVR_PWR_MAGICBITS); 224 } 225 226 attach_stage = 0; 227 228 /* 229 * Allocate the upload descriptors, and create and load the DMA 230 * map for them. 231 */ 232 if ((error = bus_dmamem_alloc(sc->sc_dmat, 233 EX_NUPD * sizeof (struct ex_upd), PAGE_SIZE, 0, &sc->sc_useg, 1, 234 &sc->sc_urseg, BUS_DMA_NOWAIT)) != 0) { 235 aprint_error( 236 "%s: can't allocate upload descriptors, error = %d\n", 237 sc->sc_dev.dv_xname, error); 238 goto fail; 239 } 240 241 attach_stage = 1; 242 243 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_useg, sc->sc_urseg, 244 EX_NUPD * sizeof (struct ex_upd), (caddr_t *)&sc->sc_upd, 245 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 246 aprint_error("%s: can't map upload descriptors, error = %d\n", 247 sc->sc_dev.dv_xname, error); 248 goto fail; 249 } 250 251 attach_stage = 2; 252 253 if ((error = bus_dmamap_create(sc->sc_dmat, 254 EX_NUPD * sizeof (struct ex_upd), 1, 255 EX_NUPD * sizeof (struct ex_upd), 0, BUS_DMA_NOWAIT, 256 &sc->sc_upd_dmamap)) != 0) { 257 aprint_error( 258 "%s: can't create upload desc. DMA map, error = %d\n", 259 sc->sc_dev.dv_xname, error); 260 goto fail; 261 } 262 263 attach_stage = 3; 264 265 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_upd_dmamap, 266 sc->sc_upd, EX_NUPD * sizeof (struct ex_upd), NULL, 267 BUS_DMA_NOWAIT)) != 0) { 268 aprint_error( 269 "%s: can't load upload desc. DMA map, error = %d\n", 270 sc->sc_dev.dv_xname, error); 271 goto fail; 272 } 273 274 attach_stage = 4; 275 276 /* 277 * Allocate the download descriptors, and create and load the DMA 278 * map for them. 279 */ 280 if ((error = bus_dmamem_alloc(sc->sc_dmat, 281 EX_NDPD * sizeof (struct ex_dpd), PAGE_SIZE, 0, &sc->sc_dseg, 1, 282 &sc->sc_drseg, BUS_DMA_NOWAIT)) != 0) { 283 aprint_error( 284 "%s: can't allocate download descriptors, error = %d\n", 285 sc->sc_dev.dv_xname, error); 286 goto fail; 287 } 288 289 attach_stage = 5; 290 291 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_drseg, 292 EX_NDPD * sizeof (struct ex_dpd), (caddr_t *)&sc->sc_dpd, 293 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 294 aprint_error("%s: can't map download descriptors, error = %d\n", 295 sc->sc_dev.dv_xname, error); 296 goto fail; 297 } 298 memset(sc->sc_dpd, 0, EX_NDPD * sizeof (struct ex_dpd)); 299 300 attach_stage = 6; 301 302 if ((error = bus_dmamap_create(sc->sc_dmat, 303 EX_NDPD * sizeof (struct ex_dpd), 1, 304 EX_NDPD * sizeof (struct ex_dpd), 0, BUS_DMA_NOWAIT, 305 &sc->sc_dpd_dmamap)) != 0) { 306 aprint_error( 307 "%s: can't create download desc. DMA map, error = %d\n", 308 sc->sc_dev.dv_xname, error); 309 goto fail; 310 } 311 312 attach_stage = 7; 313 314 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dpd_dmamap, 315 sc->sc_dpd, EX_NDPD * sizeof (struct ex_dpd), NULL, 316 BUS_DMA_NOWAIT)) != 0) { 317 aprint_error( 318 "%s: can't load download desc. DMA map, error = %d\n", 319 sc->sc_dev.dv_xname, error); 320 goto fail; 321 } 322 323 attach_stage = 8; 324 325 326 /* 327 * Create the transmit buffer DMA maps. 328 */ 329 for (i = 0; i < EX_NDPD; i++) { 330 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 331 EX_NTFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 332 &sc->sc_tx_dmamaps[i])) != 0) { 333 aprint_error( 334 "%s: can't create tx DMA map %d, error = %d\n", 335 sc->sc_dev.dv_xname, i, error); 336 goto fail; 337 } 338 } 339 340 attach_stage = 9; 341 342 /* 343 * Create the receive buffer DMA maps. 344 */ 345 for (i = 0; i < EX_NUPD; i++) { 346 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 347 EX_NRFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 348 &sc->sc_rx_dmamaps[i])) != 0) { 349 aprint_error( 350 "%s: can't create rx DMA map %d, error = %d\n", 351 sc->sc_dev.dv_xname, i, error); 352 goto fail; 353 } 354 } 355 356 attach_stage = 10; 357 358 /* 359 * Create ring of upload descriptors, only once. The DMA engine 360 * will loop over this when receiving packets, stalling if it 361 * hits an UPD with a finished receive. 362 */ 363 for (i = 0; i < EX_NUPD; i++) { 364 sc->sc_rxdescs[i].rx_dmamap = sc->sc_rx_dmamaps[i]; 365 sc->sc_rxdescs[i].rx_upd = &sc->sc_upd[i]; 366 sc->sc_upd[i].upd_frags[0].fr_len = 367 htole32((MCLBYTES - 2) | EX_FR_LAST); 368 if (ex_add_rxbuf(sc, &sc->sc_rxdescs[i]) != 0) { 369 aprint_error("%s: can't allocate or map rx buffers\n", 370 sc->sc_dev.dv_xname); 371 goto fail; 372 } 373 } 374 375 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 0, 376 EX_NUPD * sizeof (struct ex_upd), 377 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 378 379 ex_init_txdescs(sc); 380 381 attach_stage = 11; 382 383 384 GO_WINDOW(3); 385 val = bus_space_read_2(iot, ioh, ELINK_W3_RESET_OPTIONS); 386 if (val & ELINK_MEDIACAP_MII) 387 sc->ex_conf |= EX_CONF_MII; 388 389 ifp = &sc->sc_ethercom.ec_if; 390 391 /* 392 * Initialize our media structures and MII info. We'll 393 * probe the MII if we discover that we have one. 394 */ 395 sc->ex_mii.mii_ifp = ifp; 396 sc->ex_mii.mii_readreg = ex_mii_readreg; 397 sc->ex_mii.mii_writereg = ex_mii_writereg; 398 sc->ex_mii.mii_statchg = ex_mii_statchg; 399 ifmedia_init(&sc->ex_mii.mii_media, IFM_IMASK, ex_media_chg, 400 ex_media_stat); 401 402 if (sc->ex_conf & EX_CONF_MII) { 403 /* 404 * Find PHY, extract media information from it. 405 * First, select the right transceiver. 406 */ 407 ex_set_xcvr(sc, val); 408 409 mii_attach(&sc->sc_dev, &sc->ex_mii, 0xffffffff, 410 MII_PHY_ANY, MII_OFFSET_ANY, 0); 411 if (LIST_FIRST(&sc->ex_mii.mii_phys) == NULL) { 412 ifmedia_add(&sc->ex_mii.mii_media, IFM_ETHER|IFM_NONE, 413 0, NULL); 414 ifmedia_set(&sc->ex_mii.mii_media, IFM_ETHER|IFM_NONE); 415 } else { 416 ifmedia_set(&sc->ex_mii.mii_media, IFM_ETHER|IFM_AUTO); 417 } 418 } else 419 ex_probemedia(sc); 420 421 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 422 ifp->if_softc = sc; 423 ifp->if_start = ex_start; 424 ifp->if_ioctl = ex_ioctl; 425 ifp->if_watchdog = ex_watchdog; 426 ifp->if_init = ex_init; 427 ifp->if_stop = ex_stop; 428 ifp->if_flags = 429 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 430 sc->sc_if_flags = ifp->if_flags; 431 IFQ_SET_READY(&ifp->if_snd); 432 433 /* 434 * We can support 802.1Q VLAN-sized frames. 435 */ 436 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 437 438 /* 439 * The 3c90xB has hardware IPv4/TCPv4/UDPv4 checksum support. 440 */ 441 if (sc->ex_conf & EX_CONF_90XB) 442 sc->sc_ethercom.ec_if.if_capabilities |= IFCAP_CSUM_IPv4 | 443 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 444 445 if_attach(ifp); 446 ether_ifattach(ifp, macaddr); 447 448 GO_WINDOW(1); 449 450 sc->tx_start_thresh = 20; 451 sc->tx_succ_ok = 0; 452 453 /* TODO: set queues to 0 */ 454 455 #if NRND > 0 456 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 457 RND_TYPE_NET, 0); 458 #endif 459 460 /* Establish callback to reset card when we reboot. */ 461 sc->sc_sdhook = shutdownhook_establish(ex_shutdown, sc); 462 if (sc->sc_sdhook == NULL) 463 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 464 sc->sc_dev.dv_xname); 465 466 /* Add a suspend hook to make sure we come back up after a resume. */ 467 sc->sc_powerhook = powerhook_establish(ex_power, sc); 468 if (sc->sc_powerhook == NULL) 469 aprint_error("%s: WARNING: unable to establish power hook\n", 470 sc->sc_dev.dv_xname); 471 472 /* The attach is successful. */ 473 sc->ex_flags |= EX_FLAGS_ATTACHED; 474 return; 475 476 fail: 477 /* 478 * Free any resources we've allocated during the failed attach 479 * attempt. Do this in reverse order and fall though. 480 */ 481 switch (attach_stage) { 482 case 11: 483 { 484 struct ex_rxdesc *rxd; 485 486 for (i = 0; i < EX_NUPD; i++) { 487 rxd = &sc->sc_rxdescs[i]; 488 if (rxd->rx_mbhead != NULL) { 489 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 490 m_freem(rxd->rx_mbhead); 491 } 492 } 493 } 494 /* FALLTHROUGH */ 495 496 case 10: 497 for (i = 0; i < EX_NUPD; i++) 498 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_dmamaps[i]); 499 /* FALLTHROUGH */ 500 501 case 9: 502 for (i = 0; i < EX_NDPD; i++) 503 bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_dmamaps[i]); 504 /* FALLTHROUGH */ 505 case 8: 506 bus_dmamap_unload(sc->sc_dmat, sc->sc_dpd_dmamap); 507 /* FALLTHROUGH */ 508 509 case 7: 510 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dpd_dmamap); 511 /* FALLTHROUGH */ 512 513 case 6: 514 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_dpd, 515 EX_NDPD * sizeof (struct ex_dpd)); 516 /* FALLTHROUGH */ 517 518 case 5: 519 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_drseg); 520 break; 521 522 case 4: 523 bus_dmamap_unload(sc->sc_dmat, sc->sc_upd_dmamap); 524 /* FALLTHROUGH */ 525 526 case 3: 527 bus_dmamap_destroy(sc->sc_dmat, sc->sc_upd_dmamap); 528 /* FALLTHROUGH */ 529 530 case 2: 531 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_upd, 532 EX_NUPD * sizeof (struct ex_upd)); 533 /* FALLTHROUGH */ 534 535 case 1: 536 bus_dmamem_free(sc->sc_dmat, &sc->sc_useg, sc->sc_urseg); 537 break; 538 } 539 540 } 541 542 /* 543 * Find the media present on non-MII chips. 544 */ 545 void 546 ex_probemedia(sc) 547 struct ex_softc *sc; 548 { 549 bus_space_tag_t iot = sc->sc_iot; 550 bus_space_handle_t ioh = sc->sc_ioh; 551 struct ifmedia *ifm = &sc->ex_mii.mii_media; 552 struct ex_media *exm; 553 u_int16_t config1, reset_options, default_media; 554 int defmedia = 0; 555 const char *sep = "", *defmedianame = NULL; 556 557 GO_WINDOW(3); 558 config1 = bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2); 559 reset_options = bus_space_read_1(iot, ioh, ELINK_W3_RESET_OPTIONS); 560 GO_WINDOW(0); 561 562 default_media = (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; 563 564 aprint_normal("%s: ", sc->sc_dev.dv_xname); 565 566 /* Sanity check that there are any media! */ 567 if ((reset_options & ELINK_PCI_MEDIAMASK) == 0) { 568 aprint_error("no media present!\n"); 569 ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL); 570 ifmedia_set(ifm, IFM_ETHER|IFM_NONE); 571 return; 572 } 573 574 #define PRINT(str) aprint_normal("%s%s", sep, str); sep = ", " 575 576 for (exm = ex_native_media; exm->exm_name != NULL; exm++) { 577 if (reset_options & exm->exm_mpbit) { 578 /* 579 * Default media is a little complicated. We 580 * support full-duplex which uses the same 581 * reset options bit. 582 * 583 * XXX Check EEPROM for default to FDX? 584 */ 585 if (exm->exm_epmedia == default_media) { 586 if ((exm->exm_ifmedia & IFM_FDX) == 0) { 587 defmedia = exm->exm_ifmedia; 588 defmedianame = exm->exm_name; 589 } 590 } else if (defmedia == 0) { 591 defmedia = exm->exm_ifmedia; 592 defmedianame = exm->exm_name; 593 } 594 ifmedia_add(ifm, exm->exm_ifmedia, exm->exm_epmedia, 595 NULL); 596 PRINT(exm->exm_name); 597 } 598 } 599 600 #undef PRINT 601 602 #ifdef DIAGNOSTIC 603 if (defmedia == 0) 604 panic("ex_probemedia: impossible"); 605 #endif 606 607 aprint_normal(", default %s\n", defmedianame); 608 ifmedia_set(ifm, defmedia); 609 } 610 611 /* 612 * Bring device up. 613 */ 614 int 615 ex_init(ifp) 616 struct ifnet *ifp; 617 { 618 struct ex_softc *sc = ifp->if_softc; 619 bus_space_tag_t iot = sc->sc_iot; 620 bus_space_handle_t ioh = sc->sc_ioh; 621 int i; 622 int error = 0; 623 624 if ((error = ex_enable(sc)) != 0) 625 goto out; 626 627 ex_waitcmd(sc); 628 ex_stop(ifp, 0); 629 630 /* 631 * Set the station address and clear the station mask. The latter 632 * is needed for 90x cards, 0 is the default for 90xB cards. 633 */ 634 GO_WINDOW(2); 635 for (i = 0; i < ETHER_ADDR_LEN; i++) { 636 bus_space_write_1(iot, ioh, ELINK_W2_ADDR_0 + i, 637 LLADDR(ifp->if_sadl)[i]); 638 bus_space_write_1(iot, ioh, ELINK_W2_RECVMASK_0 + i, 0); 639 } 640 641 GO_WINDOW(3); 642 643 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_RESET); 644 ex_waitcmd(sc); 645 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_RESET); 646 ex_waitcmd(sc); 647 648 /* 649 * Disable reclaim threshold for 90xB, set free threshold to 650 * 6 * 256 = 1536 for 90x. 651 */ 652 if (sc->ex_conf & EX_CONF_90XB) 653 bus_space_write_2(iot, ioh, ELINK_COMMAND, 654 ELINK_TXRECLTHRESH | 255); 655 else 656 bus_space_write_1(iot, ioh, ELINK_TXFREETHRESH, 6); 657 658 bus_space_write_2(iot, ioh, ELINK_COMMAND, 659 SET_RX_EARLY_THRESH | ELINK_THRESH_DISABLE); 660 661 bus_space_write_4(iot, ioh, ELINK_DMACTRL, 662 bus_space_read_4(iot, ioh, ELINK_DMACTRL) | ELINK_DMAC_UPRXEAREN); 663 664 bus_space_write_2(iot, ioh, ELINK_COMMAND, 665 SET_RD_0_MASK | XL_WATCHED_INTERRUPTS); 666 bus_space_write_2(iot, ioh, ELINK_COMMAND, 667 SET_INTR_MASK | XL_WATCHED_INTERRUPTS); 668 669 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 0xff); 670 if (sc->intr_ack) 671 (* sc->intr_ack)(sc); 672 ex_set_media(sc); 673 ex_set_mc(sc); 674 675 676 bus_space_write_2(iot, ioh, ELINK_COMMAND, STATS_ENABLE); 677 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 678 bus_space_write_4(iot, ioh, ELINK_UPLISTPTR, sc->sc_upddma); 679 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_ENABLE); 680 bus_space_write_2(iot, ioh, ELINK_COMMAND, ELINK_UPUNSTALL); 681 682 if (sc->ex_conf & (EX_CONF_PHY_POWER | EX_CONF_INV_LED_POLARITY)) { 683 u_int16_t cbcard_config; 684 685 GO_WINDOW(2); 686 cbcard_config = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 0x0c); 687 if (sc->ex_conf & EX_CONF_PHY_POWER) { 688 cbcard_config |= 0x4000; /* turn on PHY power */ 689 } 690 if (sc->ex_conf & EX_CONF_INV_LED_POLARITY) { 691 cbcard_config |= 0x0010; /* invert LED polarity */ 692 } 693 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 0x0c, cbcard_config); 694 695 GO_WINDOW(3); 696 } 697 698 ifp->if_flags |= IFF_RUNNING; 699 ifp->if_flags &= ~IFF_OACTIVE; 700 ex_start(ifp); 701 sc->sc_if_flags = ifp->if_flags; 702 703 GO_WINDOW(1); 704 705 callout_reset(&sc->ex_mii_callout, hz, ex_tick, sc); 706 707 out: 708 if (error) { 709 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 710 ifp->if_timer = 0; 711 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 712 } 713 return (error); 714 } 715 716 #define MCHASHSIZE 256 717 #define ex_mchash(addr) (ether_crc32_be((addr), ETHER_ADDR_LEN) & \ 718 (MCHASHSIZE - 1)) 719 720 /* 721 * Set multicast receive filter. Also take care of promiscuous mode 722 * here (XXX). 723 */ 724 void 725 ex_set_mc(sc) 726 struct ex_softc *sc; 727 { 728 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 729 struct ethercom *ec = &sc->sc_ethercom; 730 struct ether_multi *enm; 731 struct ether_multistep estep; 732 int i; 733 u_int16_t mask = FIL_INDIVIDUAL | FIL_BRDCST; 734 735 if (ifp->if_flags & IFF_PROMISC) { 736 mask |= FIL_PROMISC; 737 goto allmulti; 738 } 739 740 ETHER_FIRST_MULTI(estep, ec, enm); 741 if (enm == NULL) 742 goto nomulti; 743 744 if ((sc->ex_conf & EX_CONF_90XB) == 0) 745 /* No multicast hash filtering. */ 746 goto allmulti; 747 748 for (i = 0; i < MCHASHSIZE; i++) 749 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 750 ELINK_COMMAND, ELINK_CLEARHASHFILBIT | i); 751 752 do { 753 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 754 ETHER_ADDR_LEN) != 0) 755 goto allmulti; 756 757 i = ex_mchash(enm->enm_addrlo); 758 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 759 ELINK_COMMAND, ELINK_SETHASHFILBIT | i); 760 ETHER_NEXT_MULTI(estep, enm); 761 } while (enm != NULL); 762 mask |= FIL_MULTIHASH; 763 764 nomulti: 765 ifp->if_flags &= ~IFF_ALLMULTI; 766 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, 767 SET_RX_FILTER | mask); 768 return; 769 770 allmulti: 771 ifp->if_flags |= IFF_ALLMULTI; 772 mask |= FIL_MULTICAST; 773 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, 774 SET_RX_FILTER | mask); 775 } 776 777 778 static void 779 ex_txstat(sc) 780 struct ex_softc *sc; 781 { 782 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 783 bus_space_tag_t iot = sc->sc_iot; 784 bus_space_handle_t ioh = sc->sc_ioh; 785 int i; 786 787 /* 788 * We need to read+write TX_STATUS until we get a 0 status 789 * in order to turn off the interrupt flag. 790 * ELINK_TXSTATUS is in the upper byte of 2 with ELINK_TIMER 791 * XXX: Big Endian? Can we assume that TXSTATUS will be the 792 * upper byte? 793 */ 794 while ((i = bus_space_read_2(iot, ioh, ELINK_TIMER)) & TXS_COMPLETE) { 795 bus_space_write_2(iot, ioh, ELINK_TIMER, 0x0); 796 797 if (i & TXS_JABBER) { 798 ++sc->sc_ethercom.ec_if.if_oerrors; 799 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 800 printf("%s: jabber (%x)\n", 801 sc->sc_dev.dv_xname, i); 802 ex_init(ifp); 803 /* TODO: be more subtle here */ 804 } else if (i & TXS_UNDERRUN) { 805 ++sc->sc_ethercom.ec_if.if_oerrors; 806 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 807 printf("%s: fifo underrun (%x) @%d\n", 808 sc->sc_dev.dv_xname, i, 809 sc->tx_start_thresh); 810 if (sc->tx_succ_ok < 100) 811 sc->tx_start_thresh = min(ETHER_MAX_LEN, 812 sc->tx_start_thresh + 20); 813 sc->tx_succ_ok = 0; 814 ex_init(ifp); 815 /* TODO: be more subtle here */ 816 } else if (i & TXS_MAX_COLLISION) { 817 ++sc->sc_ethercom.ec_if.if_oerrors; 818 ++sc->sc_ethercom.ec_if.if_collisions; 819 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 820 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 821 } else if (sc->tx_succ_ok < 100) 822 sc->tx_succ_ok++; 823 } 824 } 825 826 int 827 ex_media_chg(ifp) 828 struct ifnet *ifp; 829 { 830 831 if (ifp->if_flags & IFF_UP) 832 ex_init(ifp); 833 return 0; 834 } 835 836 void 837 ex_set_xcvr(sc, media) 838 struct ex_softc *sc; 839 const u_int16_t media; 840 { 841 bus_space_tag_t iot = sc->sc_iot; 842 bus_space_handle_t ioh = sc->sc_ioh; 843 u_int32_t icfg; 844 845 /* 846 * We're already in Window 3 847 */ 848 icfg = bus_space_read_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG); 849 icfg &= ~(CONFIG_XCVR_SEL << 16); 850 if (media & (ELINK_MEDIACAP_MII | ELINK_MEDIACAP_100BASET4)) 851 icfg |= ELINKMEDIA_MII << (CONFIG_XCVR_SEL_SHIFT + 16); 852 if (media & ELINK_MEDIACAP_100BASETX) 853 icfg |= ELINKMEDIA_AUTO << (CONFIG_XCVR_SEL_SHIFT + 16); 854 if (media & ELINK_MEDIACAP_100BASEFX) 855 icfg |= ELINKMEDIA_100BASE_FX 856 << (CONFIG_XCVR_SEL_SHIFT + 16); 857 bus_space_write_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG, icfg); 858 } 859 860 void 861 ex_set_media(sc) 862 struct ex_softc *sc; 863 { 864 bus_space_tag_t iot = sc->sc_iot; 865 bus_space_handle_t ioh = sc->sc_ioh; 866 u_int32_t configreg; 867 868 if (((sc->ex_conf & EX_CONF_MII) && 869 (sc->ex_mii.mii_media_active & IFM_FDX)) 870 || (!(sc->ex_conf & EX_CONF_MII) && 871 (sc->ex_mii.mii_media.ifm_media & IFM_FDX))) { 872 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, 873 MAC_CONTROL_FDX); 874 } else { 875 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, 0); 876 } 877 878 /* 879 * If the device has MII, select it, and then tell the 880 * PHY which media to use. 881 */ 882 if (sc->ex_conf & EX_CONF_MII) { 883 u_int16_t val; 884 885 GO_WINDOW(3); 886 val = bus_space_read_2(iot, ioh, ELINK_W3_RESET_OPTIONS); 887 ex_set_xcvr(sc, val); 888 mii_mediachg(&sc->ex_mii); 889 return; 890 } 891 892 GO_WINDOW(4); 893 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 0); 894 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 895 delay(800); 896 897 /* 898 * Now turn on the selected media/transceiver. 899 */ 900 switch (IFM_SUBTYPE(sc->ex_mii.mii_media.ifm_cur->ifm_media)) { 901 case IFM_10_T: 902 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 903 JABBER_GUARD_ENABLE|LINKBEAT_ENABLE); 904 break; 905 906 case IFM_10_2: 907 bus_space_write_2(iot, ioh, ELINK_COMMAND, START_TRANSCEIVER); 908 DELAY(800); 909 break; 910 911 case IFM_100_TX: 912 case IFM_100_FX: 913 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 914 LINKBEAT_ENABLE); 915 DELAY(800); 916 break; 917 918 case IFM_10_5: 919 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 920 SQE_ENABLE); 921 DELAY(800); 922 break; 923 924 case IFM_MANUAL: 925 break; 926 927 case IFM_NONE: 928 return; 929 930 default: 931 panic("ex_set_media: impossible"); 932 } 933 934 GO_WINDOW(3); 935 configreg = bus_space_read_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG); 936 937 configreg &= ~(CONFIG_MEDIAMASK << 16); 938 configreg |= (sc->ex_mii.mii_media.ifm_cur->ifm_data << 939 (CONFIG_MEDIAMASK_SHIFT + 16)); 940 941 bus_space_write_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG, configreg); 942 } 943 944 /* 945 * Get currently-selected media from card. 946 * (if_media callback, may be called before interface is brought up). 947 */ 948 void 949 ex_media_stat(ifp, req) 950 struct ifnet *ifp; 951 struct ifmediareq *req; 952 { 953 struct ex_softc *sc = ifp->if_softc; 954 u_int16_t help; 955 956 if ((ifp->if_flags & (IFF_UP|IFF_RUNNING)) == (IFF_UP|IFF_RUNNING)) { 957 if (sc->ex_conf & EX_CONF_MII) { 958 mii_pollstat(&sc->ex_mii); 959 req->ifm_status = sc->ex_mii.mii_media_status; 960 req->ifm_active = sc->ex_mii.mii_media_active; 961 } else { 962 GO_WINDOW(4); 963 req->ifm_status = IFM_AVALID; 964 req->ifm_active = 965 sc->ex_mii.mii_media.ifm_cur->ifm_media; 966 help = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 967 ELINK_W4_MEDIA_TYPE); 968 if (help & LINKBEAT_DETECT) 969 req->ifm_status |= IFM_ACTIVE; 970 GO_WINDOW(1); 971 } 972 } 973 } 974 975 976 977 /* 978 * Start outputting on the interface. 979 */ 980 static void 981 ex_start(ifp) 982 struct ifnet *ifp; 983 { 984 struct ex_softc *sc = ifp->if_softc; 985 bus_space_tag_t iot = sc->sc_iot; 986 bus_space_handle_t ioh = sc->sc_ioh; 987 volatile struct ex_fraghdr *fr = NULL; 988 volatile struct ex_dpd *dpd = NULL, *prevdpd = NULL; 989 struct ex_txdesc *txp; 990 struct mbuf *mb_head; 991 bus_dmamap_t dmamap; 992 int offset, totlen, segment, error; 993 u_int32_t csum_flags; 994 995 if (sc->tx_head || sc->tx_free == NULL) 996 return; 997 998 txp = NULL; 999 1000 /* 1001 * We're finished if there is nothing more to add to the list or if 1002 * we're all filled up with buffers to transmit. 1003 */ 1004 while (sc->tx_free != NULL) { 1005 /* 1006 * Grab a packet to transmit. 1007 */ 1008 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1009 if (mb_head == NULL) 1010 break; 1011 1012 /* 1013 * Get pointer to next available tx desc. 1014 */ 1015 txp = sc->tx_free; 1016 dmamap = txp->tx_dmamap; 1017 1018 /* 1019 * Go through each of the mbufs in the chain and initialize 1020 * the transmit buffer descriptors with the physical address 1021 * and size of the mbuf. 1022 */ 1023 reload: 1024 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1025 mb_head, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1026 switch (error) { 1027 case 0: 1028 /* Success. */ 1029 break; 1030 1031 case EFBIG: 1032 { 1033 struct mbuf *mn; 1034 1035 /* 1036 * We ran out of segments. We have to recopy this 1037 * mbuf chain first. Bail out if we can't get the 1038 * new buffers. 1039 */ 1040 printf("%s: too many segments, ", sc->sc_dev.dv_xname); 1041 1042 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1043 if (mn == NULL) { 1044 m_freem(mb_head); 1045 printf("aborting\n"); 1046 goto out; 1047 } 1048 if (mb_head->m_pkthdr.len > MHLEN) { 1049 MCLGET(mn, M_DONTWAIT); 1050 if ((mn->m_flags & M_EXT) == 0) { 1051 m_freem(mn); 1052 m_freem(mb_head); 1053 printf("aborting\n"); 1054 goto out; 1055 } 1056 } 1057 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1058 mtod(mn, caddr_t)); 1059 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1060 m_freem(mb_head); 1061 mb_head = mn; 1062 printf("retrying\n"); 1063 goto reload; 1064 } 1065 1066 default: 1067 /* 1068 * Some other problem; report it. 1069 */ 1070 printf("%s: can't load mbuf chain, error = %d\n", 1071 sc->sc_dev.dv_xname, error); 1072 m_freem(mb_head); 1073 goto out; 1074 } 1075 1076 /* 1077 * remove our tx desc from freelist. 1078 */ 1079 sc->tx_free = txp->tx_next; 1080 txp->tx_next = NULL; 1081 1082 fr = &txp->tx_dpd->dpd_frags[0]; 1083 totlen = 0; 1084 for (segment = 0; segment < dmamap->dm_nsegs; segment++, fr++) { 1085 fr->fr_addr = htole32(dmamap->dm_segs[segment].ds_addr); 1086 fr->fr_len = htole32(dmamap->dm_segs[segment].ds_len); 1087 totlen += dmamap->dm_segs[segment].ds_len; 1088 } 1089 fr--; 1090 fr->fr_len |= htole32(EX_FR_LAST); 1091 txp->tx_mbhead = mb_head; 1092 1093 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1094 BUS_DMASYNC_PREWRITE); 1095 1096 dpd = txp->tx_dpd; 1097 dpd->dpd_nextptr = 0; 1098 dpd->dpd_fsh = htole32(totlen); 1099 1100 /* Byte-swap constants so compiler can optimize. */ 1101 1102 if (sc->ex_conf & EX_CONF_90XB) { 1103 csum_flags = 0; 1104 1105 if (mb_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 1106 csum_flags |= htole32(EX_DPD_IPCKSUM); 1107 1108 if (mb_head->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1109 csum_flags |= htole32(EX_DPD_TCPCKSUM); 1110 else if (mb_head->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1111 csum_flags |= htole32(EX_DPD_UDPCKSUM); 1112 1113 dpd->dpd_fsh |= csum_flags; 1114 } else { 1115 KDASSERT((mb_head->m_pkthdr.csum_flags & 1116 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) == 0); 1117 } 1118 1119 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1120 ((caddr_t)dpd - (caddr_t)sc->sc_dpd), 1121 sizeof (struct ex_dpd), 1122 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1123 1124 /* 1125 * No need to stall the download engine, we know it's 1126 * not busy right now. 1127 * 1128 * Fix up pointers in both the "soft" tx and the physical 1129 * tx list. 1130 */ 1131 if (sc->tx_head != NULL) { 1132 prevdpd = sc->tx_tail->tx_dpd; 1133 offset = ((caddr_t)prevdpd - (caddr_t)sc->sc_dpd); 1134 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1135 offset, sizeof (struct ex_dpd), 1136 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1137 prevdpd->dpd_nextptr = htole32(DPD_DMADDR(sc, txp)); 1138 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1139 offset, sizeof (struct ex_dpd), 1140 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1141 sc->tx_tail->tx_next = txp; 1142 sc->tx_tail = txp; 1143 } else { 1144 sc->tx_tail = sc->tx_head = txp; 1145 } 1146 1147 #if NBPFILTER > 0 1148 /* 1149 * Pass packet to bpf if there is a listener. 1150 */ 1151 if (ifp->if_bpf) 1152 bpf_mtap(ifp->if_bpf, mb_head); 1153 #endif 1154 } 1155 out: 1156 if (sc->tx_head) { 1157 sc->tx_tail->tx_dpd->dpd_fsh |= htole32(EX_DPD_DNIND); 1158 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1159 ((caddr_t)sc->tx_tail->tx_dpd - (caddr_t)sc->sc_dpd), 1160 sizeof (struct ex_dpd), 1161 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1162 ifp->if_flags |= IFF_OACTIVE; 1163 bus_space_write_2(iot, ioh, ELINK_COMMAND, ELINK_DNUNSTALL); 1164 bus_space_write_4(iot, ioh, ELINK_DNLISTPTR, 1165 DPD_DMADDR(sc, sc->tx_head)); 1166 1167 /* trigger watchdog */ 1168 ifp->if_timer = 5; 1169 } 1170 } 1171 1172 1173 int 1174 ex_intr(arg) 1175 void *arg; 1176 { 1177 struct ex_softc *sc = arg; 1178 bus_space_tag_t iot = sc->sc_iot; 1179 bus_space_handle_t ioh = sc->sc_ioh; 1180 u_int16_t stat; 1181 int ret = 0; 1182 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1183 1184 if ((ifp->if_flags & IFF_RUNNING) == 0 || 1185 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1186 return (0); 1187 1188 for (;;) { 1189 stat = bus_space_read_2(iot, ioh, ELINK_STATUS); 1190 1191 if ((stat & XL_WATCHED_INTERRUPTS) == 0) { 1192 if ((stat & INTR_LATCH) == 0) { 1193 #if 0 1194 printf("%s: intr latch cleared\n", 1195 sc->sc_dev.dv_xname); 1196 #endif 1197 break; 1198 } 1199 } 1200 1201 ret = 1; 1202 1203 /* 1204 * Acknowledge interrupts. 1205 */ 1206 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 1207 (stat & (XL_WATCHED_INTERRUPTS | INTR_LATCH))); 1208 if (sc->intr_ack) 1209 (*sc->intr_ack)(sc); 1210 1211 if (stat & HOST_ERROR) { 1212 printf("%s: adapter failure (%x)\n", 1213 sc->sc_dev.dv_xname, stat); 1214 ex_reset(sc); 1215 ex_init(ifp); 1216 return 1; 1217 } 1218 if (stat & TX_COMPLETE) { 1219 ex_txstat(sc); 1220 } 1221 if (stat & UPD_STATS) { 1222 ex_getstats(sc); 1223 } 1224 if (stat & DN_COMPLETE) { 1225 struct ex_txdesc *txp, *ptxp = NULL; 1226 bus_dmamap_t txmap; 1227 1228 /* reset watchdog timer, was set in ex_start() */ 1229 ifp->if_timer = 0; 1230 1231 for (txp = sc->tx_head; txp != NULL; 1232 txp = txp->tx_next) { 1233 bus_dmamap_sync(sc->sc_dmat, 1234 sc->sc_dpd_dmamap, 1235 (caddr_t)txp->tx_dpd - (caddr_t)sc->sc_dpd, 1236 sizeof (struct ex_dpd), 1237 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1238 if (txp->tx_mbhead != NULL) { 1239 txmap = txp->tx_dmamap; 1240 bus_dmamap_sync(sc->sc_dmat, txmap, 1241 0, txmap->dm_mapsize, 1242 BUS_DMASYNC_POSTWRITE); 1243 bus_dmamap_unload(sc->sc_dmat, txmap); 1244 m_freem(txp->tx_mbhead); 1245 txp->tx_mbhead = NULL; 1246 } 1247 ptxp = txp; 1248 } 1249 1250 /* 1251 * Move finished tx buffers back to the tx free list. 1252 */ 1253 if (sc->tx_free) { 1254 sc->tx_ftail->tx_next = sc->tx_head; 1255 sc->tx_ftail = ptxp; 1256 } else 1257 sc->tx_ftail = sc->tx_free = sc->tx_head; 1258 1259 sc->tx_head = sc->tx_tail = NULL; 1260 ifp->if_flags &= ~IFF_OACTIVE; 1261 } 1262 1263 if (stat & UP_COMPLETE) { 1264 struct ex_rxdesc *rxd; 1265 struct mbuf *m; 1266 struct ex_upd *upd; 1267 bus_dmamap_t rxmap; 1268 u_int32_t pktstat; 1269 1270 rcvloop: 1271 rxd = sc->rx_head; 1272 rxmap = rxd->rx_dmamap; 1273 m = rxd->rx_mbhead; 1274 upd = rxd->rx_upd; 1275 1276 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, 1277 rxmap->dm_mapsize, 1278 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1279 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1280 ((caddr_t)upd - (caddr_t)sc->sc_upd), 1281 sizeof (struct ex_upd), 1282 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1283 pktstat = le32toh(upd->upd_pktstatus); 1284 1285 if (pktstat & EX_UPD_COMPLETE) { 1286 /* 1287 * Remove first packet from the chain. 1288 */ 1289 sc->rx_head = rxd->rx_next; 1290 rxd->rx_next = NULL; 1291 1292 /* 1293 * Add a new buffer to the receive chain. 1294 * If this fails, the old buffer is recycled 1295 * instead. 1296 */ 1297 if (ex_add_rxbuf(sc, rxd) == 0) { 1298 u_int16_t total_len; 1299 1300 if (pktstat & 1301 ((sc->sc_ethercom.ec_capenable & 1302 ETHERCAP_VLAN_MTU) ? 1303 EX_UPD_ERR_VLAN : EX_UPD_ERR)) { 1304 ifp->if_ierrors++; 1305 m_freem(m); 1306 goto rcvloop; 1307 } 1308 1309 total_len = pktstat & EX_UPD_PKTLENMASK; 1310 if (total_len < 1311 sizeof(struct ether_header)) { 1312 m_freem(m); 1313 goto rcvloop; 1314 } 1315 m->m_pkthdr.rcvif = ifp; 1316 m->m_pkthdr.len = m->m_len = total_len; 1317 #if NBPFILTER > 0 1318 if (ifp->if_bpf) 1319 bpf_mtap(ifp->if_bpf, m); 1320 #endif 1321 /* 1322 * Set the incoming checksum information for the packet. 1323 */ 1324 if ((sc->ex_conf & EX_CONF_90XB) != 0 && 1325 (pktstat & EX_UPD_IPCHECKED) != 0) { 1326 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1327 if (pktstat & EX_UPD_IPCKSUMERR) 1328 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1329 if (pktstat & EX_UPD_TCPCHECKED) { 1330 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1331 if (pktstat & EX_UPD_TCPCKSUMERR) 1332 m->m_pkthdr.csum_flags |= 1333 M_CSUM_TCP_UDP_BAD; 1334 } else if (pktstat & EX_UPD_UDPCHECKED) { 1335 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1336 if (pktstat & EX_UPD_UDPCKSUMERR) 1337 m->m_pkthdr.csum_flags |= 1338 M_CSUM_TCP_UDP_BAD; 1339 } 1340 } 1341 (*ifp->if_input)(ifp, m); 1342 } 1343 goto rcvloop; 1344 } 1345 /* 1346 * Just in case we filled up all UPDs and the DMA engine 1347 * stalled. We could be more subtle about this. 1348 */ 1349 if (bus_space_read_4(iot, ioh, ELINK_UPLISTPTR) == 0) { 1350 printf("%s: uplistptr was 0\n", 1351 sc->sc_dev.dv_xname); 1352 ex_init(ifp); 1353 } else if (bus_space_read_4(iot, ioh, ELINK_UPPKTSTATUS) 1354 & 0x2000) { 1355 printf("%s: receive stalled\n", 1356 sc->sc_dev.dv_xname); 1357 bus_space_write_2(iot, ioh, ELINK_COMMAND, 1358 ELINK_UPUNSTALL); 1359 } 1360 } 1361 1362 #if NRND > 0 1363 if (stat) 1364 rnd_add_uint32(&sc->rnd_source, stat); 1365 #endif 1366 } 1367 1368 /* no more interrupts */ 1369 if (ret && IFQ_IS_EMPTY(&ifp->if_snd) == 0) 1370 ex_start(ifp); 1371 return ret; 1372 } 1373 1374 int 1375 ex_ioctl(ifp, cmd, data) 1376 struct ifnet *ifp; 1377 u_long cmd; 1378 caddr_t data; 1379 { 1380 struct ex_softc *sc = ifp->if_softc; 1381 struct ifreq *ifr = (struct ifreq *)data; 1382 int s, error; 1383 1384 s = splnet(); 1385 1386 switch (cmd) { 1387 case SIOCSIFMEDIA: 1388 case SIOCGIFMEDIA: 1389 error = ifmedia_ioctl(ifp, ifr, &sc->ex_mii.mii_media, cmd); 1390 break; 1391 case SIOCSIFFLAGS: 1392 /* If the interface is up and running, only modify the receive 1393 * filter when setting promiscuous or debug mode. Otherwise 1394 * fall through to ether_ioctl, which will reset the chip. 1395 */ 1396 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 1397 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 1398 == (IFF_UP|IFF_RUNNING)) 1399 && ((ifp->if_flags & (~RESETIGN)) 1400 == (sc->sc_if_flags & (~RESETIGN)))) { 1401 ex_set_mc(sc); 1402 error = 0; 1403 break; 1404 #undef RESETIGN 1405 } 1406 /* FALLTHROUGH */ 1407 default: 1408 error = ether_ioctl(ifp, cmd, data); 1409 if (error == ENETRESET) { 1410 /* 1411 * Multicast list has changed; set the hardware filter 1412 * accordingly. 1413 */ 1414 if (ifp->if_flags & IFF_RUNNING) 1415 ex_set_mc(sc); 1416 error = 0; 1417 } 1418 break; 1419 } 1420 1421 sc->sc_if_flags = ifp->if_flags; 1422 splx(s); 1423 return (error); 1424 } 1425 1426 void 1427 ex_getstats(sc) 1428 struct ex_softc *sc; 1429 { 1430 bus_space_handle_t ioh = sc->sc_ioh; 1431 bus_space_tag_t iot = sc->sc_iot; 1432 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1433 u_int8_t upperok; 1434 1435 GO_WINDOW(6); 1436 upperok = bus_space_read_1(iot, ioh, UPPER_FRAMES_OK); 1437 ifp->if_ipackets += bus_space_read_1(iot, ioh, RX_FRAMES_OK); 1438 ifp->if_ipackets += (upperok & 0x03) << 8; 1439 ifp->if_opackets += bus_space_read_1(iot, ioh, TX_FRAMES_OK); 1440 ifp->if_opackets += (upperok & 0x30) << 4; 1441 ifp->if_ierrors += bus_space_read_1(iot, ioh, RX_OVERRUNS); 1442 ifp->if_collisions += bus_space_read_1(iot, ioh, TX_COLLISIONS); 1443 /* 1444 * There seems to be no way to get the exact number of collisions, 1445 * this is the number that occurred at the very least. 1446 */ 1447 ifp->if_collisions += 2 * bus_space_read_1(iot, ioh, 1448 TX_AFTER_X_COLLISIONS); 1449 /* 1450 * Interface byte counts are counted by ether_input() and 1451 * ether_output(), so don't accumulate them here. Just 1452 * read the NIC counters so they don't generate overflow interrupts. 1453 * Upper byte counters are latched from reading the totals, so 1454 * they don't need to be read if we don't need their values. 1455 */ 1456 bus_space_read_2(iot, ioh, RX_TOTAL_OK); 1457 bus_space_read_2(iot, ioh, TX_TOTAL_OK); 1458 1459 /* 1460 * Clear the following to avoid stats overflow interrupts 1461 */ 1462 bus_space_read_1(iot, ioh, TX_DEFERRALS); 1463 bus_space_read_1(iot, ioh, TX_AFTER_1_COLLISION); 1464 bus_space_read_1(iot, ioh, TX_NO_SQE); 1465 bus_space_read_1(iot, ioh, TX_CD_LOST); 1466 GO_WINDOW(4); 1467 bus_space_read_1(iot, ioh, ELINK_W4_BADSSD); 1468 GO_WINDOW(1); 1469 } 1470 1471 void 1472 ex_printstats(sc) 1473 struct ex_softc *sc; 1474 { 1475 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1476 1477 ex_getstats(sc); 1478 printf("in %llu out %llu ierror %llu oerror %llu ibytes %llu obytes " 1479 "%llu\n", (unsigned long long)ifp->if_ipackets, 1480 (unsigned long long)ifp->if_opackets, 1481 (unsigned long long)ifp->if_ierrors, 1482 (unsigned long long)ifp->if_oerrors, 1483 (unsigned long long)ifp->if_ibytes, 1484 (unsigned long long)ifp->if_obytes); 1485 } 1486 1487 void 1488 ex_tick(arg) 1489 void *arg; 1490 { 1491 struct ex_softc *sc = arg; 1492 int s; 1493 1494 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1495 return; 1496 1497 s = splnet(); 1498 1499 if (sc->ex_conf & EX_CONF_MII) 1500 mii_tick(&sc->ex_mii); 1501 1502 if (!(bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, ELINK_STATUS) 1503 & COMMAND_IN_PROGRESS)) 1504 ex_getstats(sc); 1505 1506 splx(s); 1507 1508 callout_reset(&sc->ex_mii_callout, hz, ex_tick, sc); 1509 } 1510 1511 void 1512 ex_reset(sc) 1513 struct ex_softc *sc; 1514 { 1515 u_int16_t val = GLOBAL_RESET; 1516 1517 if (sc->ex_conf & EX_CONF_RESETHACK) 1518 val |= 0x10; 1519 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, val); 1520 /* 1521 * XXX apparently the command in progress bit can't be trusted 1522 * during a reset, so we just always wait this long. Fortunately 1523 * we normally only reset the chip during autoconfig. 1524 */ 1525 delay(100000); 1526 ex_waitcmd(sc); 1527 } 1528 1529 void 1530 ex_watchdog(ifp) 1531 struct ifnet *ifp; 1532 { 1533 struct ex_softc *sc = ifp->if_softc; 1534 1535 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1536 ++sc->sc_ethercom.ec_if.if_oerrors; 1537 1538 ex_reset(sc); 1539 ex_init(ifp); 1540 } 1541 1542 void 1543 ex_stop(ifp, disable) 1544 struct ifnet *ifp; 1545 int disable; 1546 { 1547 struct ex_softc *sc = ifp->if_softc; 1548 bus_space_tag_t iot = sc->sc_iot; 1549 bus_space_handle_t ioh = sc->sc_ioh; 1550 struct ex_txdesc *tx; 1551 struct ex_rxdesc *rx; 1552 int i; 1553 1554 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_DISABLE); 1555 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_DISABLE); 1556 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 1557 1558 for (tx = sc->tx_head ; tx != NULL; tx = tx->tx_next) { 1559 if (tx->tx_mbhead == NULL) 1560 continue; 1561 m_freem(tx->tx_mbhead); 1562 tx->tx_mbhead = NULL; 1563 bus_dmamap_unload(sc->sc_dmat, tx->tx_dmamap); 1564 tx->tx_dpd->dpd_fsh = tx->tx_dpd->dpd_nextptr = 0; 1565 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1566 ((caddr_t)tx->tx_dpd - (caddr_t)sc->sc_dpd), 1567 sizeof (struct ex_dpd), 1568 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1569 } 1570 sc->tx_tail = sc->tx_head = NULL; 1571 ex_init_txdescs(sc); 1572 1573 sc->rx_tail = sc->rx_head = 0; 1574 for (i = 0; i < EX_NUPD; i++) { 1575 rx = &sc->sc_rxdescs[i]; 1576 if (rx->rx_mbhead != NULL) { 1577 bus_dmamap_unload(sc->sc_dmat, rx->rx_dmamap); 1578 m_freem(rx->rx_mbhead); 1579 rx->rx_mbhead = NULL; 1580 } 1581 ex_add_rxbuf(sc, rx); 1582 } 1583 1584 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | INTR_LATCH); 1585 1586 callout_stop(&sc->ex_mii_callout); 1587 if (sc->ex_conf & EX_CONF_MII) 1588 mii_down(&sc->ex_mii); 1589 1590 if (disable) 1591 ex_disable(sc); 1592 1593 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1594 sc->sc_if_flags = ifp->if_flags; 1595 ifp->if_timer = 0; 1596 } 1597 1598 static void 1599 ex_init_txdescs(sc) 1600 struct ex_softc *sc; 1601 { 1602 int i; 1603 1604 for (i = 0; i < EX_NDPD; i++) { 1605 sc->sc_txdescs[i].tx_dmamap = sc->sc_tx_dmamaps[i]; 1606 sc->sc_txdescs[i].tx_dpd = &sc->sc_dpd[i]; 1607 if (i < EX_NDPD - 1) 1608 sc->sc_txdescs[i].tx_next = &sc->sc_txdescs[i + 1]; 1609 else 1610 sc->sc_txdescs[i].tx_next = NULL; 1611 } 1612 sc->tx_free = &sc->sc_txdescs[0]; 1613 sc->tx_ftail = &sc->sc_txdescs[EX_NDPD-1]; 1614 } 1615 1616 1617 int 1618 ex_activate(self, act) 1619 struct device *self; 1620 enum devact act; 1621 { 1622 struct ex_softc *sc = (void *) self; 1623 int s, error = 0; 1624 1625 s = splnet(); 1626 switch (act) { 1627 case DVACT_ACTIVATE: 1628 error = EOPNOTSUPP; 1629 break; 1630 1631 case DVACT_DEACTIVATE: 1632 if (sc->ex_conf & EX_CONF_MII) 1633 mii_activate(&sc->ex_mii, act, MII_PHY_ANY, 1634 MII_OFFSET_ANY); 1635 if_deactivate(&sc->sc_ethercom.ec_if); 1636 break; 1637 } 1638 splx(s); 1639 1640 return (error); 1641 } 1642 1643 int 1644 ex_detach(sc) 1645 struct ex_softc *sc; 1646 { 1647 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1648 struct ex_rxdesc *rxd; 1649 int i; 1650 1651 /* Succeed now if there's no work to do. */ 1652 if ((sc->ex_flags & EX_FLAGS_ATTACHED) == 0) 1653 return (0); 1654 1655 /* Unhook our tick handler. */ 1656 callout_stop(&sc->ex_mii_callout); 1657 1658 if (sc->ex_conf & EX_CONF_MII) { 1659 /* Detach all PHYs */ 1660 mii_detach(&sc->ex_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1661 } 1662 1663 /* Delete all remaining media. */ 1664 ifmedia_delete_instance(&sc->ex_mii.mii_media, IFM_INST_ANY); 1665 1666 #if NRND > 0 1667 rnd_detach_source(&sc->rnd_source); 1668 #endif 1669 ether_ifdetach(ifp); 1670 if_detach(ifp); 1671 1672 for (i = 0; i < EX_NUPD; i++) { 1673 rxd = &sc->sc_rxdescs[i]; 1674 if (rxd->rx_mbhead != NULL) { 1675 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1676 m_freem(rxd->rx_mbhead); 1677 rxd->rx_mbhead = NULL; 1678 } 1679 } 1680 for (i = 0; i < EX_NUPD; i++) 1681 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_dmamaps[i]); 1682 for (i = 0; i < EX_NDPD; i++) 1683 bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_dmamaps[i]); 1684 bus_dmamap_unload(sc->sc_dmat, sc->sc_dpd_dmamap); 1685 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dpd_dmamap); 1686 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_dpd, 1687 EX_NDPD * sizeof (struct ex_dpd)); 1688 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_drseg); 1689 bus_dmamap_unload(sc->sc_dmat, sc->sc_upd_dmamap); 1690 bus_dmamap_destroy(sc->sc_dmat, sc->sc_upd_dmamap); 1691 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_upd, 1692 EX_NUPD * sizeof (struct ex_upd)); 1693 bus_dmamem_free(sc->sc_dmat, &sc->sc_useg, sc->sc_urseg); 1694 1695 shutdownhook_disestablish(sc->sc_sdhook); 1696 powerhook_disestablish(sc->sc_powerhook); 1697 1698 return (0); 1699 } 1700 1701 /* 1702 * Before reboots, reset card completely. 1703 */ 1704 static void 1705 ex_shutdown(arg) 1706 void *arg; 1707 { 1708 struct ex_softc *sc = arg; 1709 1710 ex_stop(&sc->sc_ethercom.ec_if, 1); 1711 /* 1712 * Make sure the interface is powered up when we reboot, 1713 * otherwise firmware on some systems gets really confused. 1714 */ 1715 (void) ex_enable(sc); 1716 } 1717 1718 /* 1719 * Read EEPROM data. 1720 * XXX what to do if EEPROM doesn't unbusy? 1721 */ 1722 u_int16_t 1723 ex_read_eeprom(sc, offset) 1724 struct ex_softc *sc; 1725 int offset; 1726 { 1727 bus_space_tag_t iot = sc->sc_iot; 1728 bus_space_handle_t ioh = sc->sc_ioh; 1729 u_int16_t data = 0, cmd = READ_EEPROM; 1730 int off; 1731 1732 off = sc->ex_conf & EX_CONF_EEPROM_OFF ? 0x30 : 0; 1733 cmd = sc->ex_conf & EX_CONF_EEPROM_8BIT ? READ_EEPROM8 : READ_EEPROM; 1734 1735 GO_WINDOW(0); 1736 if (ex_eeprom_busy(sc)) 1737 goto out; 1738 bus_space_write_2(iot, ioh, ELINK_W0_EEPROM_COMMAND, 1739 cmd | (off + (offset & 0x3f))); 1740 if (ex_eeprom_busy(sc)) 1741 goto out; 1742 data = bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_DATA); 1743 out: 1744 return data; 1745 } 1746 1747 static int 1748 ex_eeprom_busy(sc) 1749 struct ex_softc *sc; 1750 { 1751 bus_space_tag_t iot = sc->sc_iot; 1752 bus_space_handle_t ioh = sc->sc_ioh; 1753 int i = 100; 1754 1755 while (i--) { 1756 if (!(bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_COMMAND) & 1757 EEPROM_BUSY)) 1758 return 0; 1759 delay(100); 1760 } 1761 printf("\n%s: eeprom stays busy.\n", sc->sc_dev.dv_xname); 1762 return (1); 1763 } 1764 1765 /* 1766 * Create a new rx buffer and add it to the 'soft' rx list. 1767 */ 1768 static int 1769 ex_add_rxbuf(sc, rxd) 1770 struct ex_softc *sc; 1771 struct ex_rxdesc *rxd; 1772 { 1773 struct mbuf *m, *oldm; 1774 bus_dmamap_t rxmap; 1775 int error, rval = 0; 1776 1777 oldm = rxd->rx_mbhead; 1778 rxmap = rxd->rx_dmamap; 1779 1780 MGETHDR(m, M_DONTWAIT, MT_DATA); 1781 if (m != NULL) { 1782 MCLGET(m, M_DONTWAIT); 1783 if ((m->m_flags & M_EXT) == 0) { 1784 m_freem(m); 1785 if (oldm == NULL) 1786 return 1; 1787 m = oldm; 1788 MRESETDATA(m); 1789 rval = 1; 1790 } 1791 } else { 1792 if (oldm == NULL) 1793 return 1; 1794 m = oldm; 1795 MRESETDATA(m); 1796 rval = 1; 1797 } 1798 1799 /* 1800 * Setup the DMA map for this receive buffer. 1801 */ 1802 if (m != oldm) { 1803 if (oldm != NULL) 1804 bus_dmamap_unload(sc->sc_dmat, rxmap); 1805 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1806 m->m_ext.ext_buf, MCLBYTES, NULL, 1807 BUS_DMA_READ|BUS_DMA_NOWAIT); 1808 if (error) { 1809 printf("%s: can't load rx buffer, error = %d\n", 1810 sc->sc_dev.dv_xname, error); 1811 panic("ex_add_rxbuf"); /* XXX */ 1812 } 1813 } 1814 1815 /* 1816 * Align for data after 14 byte header. 1817 */ 1818 m->m_data += 2; 1819 1820 rxd->rx_mbhead = m; 1821 rxd->rx_upd->upd_pktstatus = htole32(MCLBYTES - 2); 1822 rxd->rx_upd->upd_frags[0].fr_addr = 1823 htole32(rxmap->dm_segs[0].ds_addr + 2); 1824 rxd->rx_upd->upd_nextptr = 0; 1825 1826 /* 1827 * Attach it to the end of the list. 1828 */ 1829 if (sc->rx_head != NULL) { 1830 sc->rx_tail->rx_next = rxd; 1831 sc->rx_tail->rx_upd->upd_nextptr = htole32(sc->sc_upddma + 1832 ((caddr_t)rxd->rx_upd - (caddr_t)sc->sc_upd)); 1833 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1834 (caddr_t)sc->rx_tail->rx_upd - (caddr_t)sc->sc_upd, 1835 sizeof (struct ex_upd), 1836 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1837 } else { 1838 sc->rx_head = rxd; 1839 } 1840 sc->rx_tail = rxd; 1841 1842 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, rxmap->dm_mapsize, 1843 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1844 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1845 ((caddr_t)rxd->rx_upd - (caddr_t)sc->sc_upd), 1846 sizeof (struct ex_upd), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1847 return (rval); 1848 } 1849 1850 u_int32_t 1851 ex_mii_bitbang_read(self) 1852 struct device *self; 1853 { 1854 struct ex_softc *sc = (void *) self; 1855 1856 /* We're already in Window 4. */ 1857 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT)); 1858 } 1859 1860 void 1861 ex_mii_bitbang_write(self, val) 1862 struct device *self; 1863 u_int32_t val; 1864 { 1865 struct ex_softc *sc = (void *) self; 1866 1867 /* We're already in Window 4. */ 1868 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT, val); 1869 } 1870 1871 int 1872 ex_mii_readreg(v, phy, reg) 1873 struct device *v; 1874 int phy, reg; 1875 { 1876 struct ex_softc *sc = (struct ex_softc *)v; 1877 int val; 1878 1879 if ((sc->ex_conf & EX_CONF_INTPHY) && phy != ELINK_INTPHY_ID) 1880 return 0; 1881 1882 GO_WINDOW(4); 1883 1884 val = mii_bitbang_readreg(v, &ex_mii_bitbang_ops, phy, reg); 1885 1886 GO_WINDOW(1); 1887 1888 return (val); 1889 } 1890 1891 void 1892 ex_mii_writereg(v, phy, reg, data) 1893 struct device *v; 1894 int phy; 1895 int reg; 1896 int data; 1897 { 1898 struct ex_softc *sc = (struct ex_softc *)v; 1899 1900 GO_WINDOW(4); 1901 1902 mii_bitbang_writereg(v, &ex_mii_bitbang_ops, phy, reg, data); 1903 1904 GO_WINDOW(1); 1905 } 1906 1907 void 1908 ex_mii_statchg(v) 1909 struct device *v; 1910 { 1911 struct ex_softc *sc = (struct ex_softc *)v; 1912 bus_space_tag_t iot = sc->sc_iot; 1913 bus_space_handle_t ioh = sc->sc_ioh; 1914 int mctl; 1915 1916 GO_WINDOW(3); 1917 mctl = bus_space_read_2(iot, ioh, ELINK_W3_MAC_CONTROL); 1918 if (sc->ex_mii.mii_media_active & IFM_FDX) 1919 mctl |= MAC_CONTROL_FDX; 1920 else 1921 mctl &= ~MAC_CONTROL_FDX; 1922 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, mctl); 1923 GO_WINDOW(1); /* back to operating window */ 1924 } 1925 1926 int 1927 ex_enable(sc) 1928 struct ex_softc *sc; 1929 { 1930 if (sc->enabled == 0 && sc->enable != NULL) { 1931 if ((*sc->enable)(sc) != 0) { 1932 printf("%s: de/vice enable failed\n", 1933 sc->sc_dev.dv_xname); 1934 return (EIO); 1935 } 1936 sc->enabled = 1; 1937 } 1938 return (0); 1939 } 1940 1941 void 1942 ex_disable(sc) 1943 struct ex_softc *sc; 1944 { 1945 if (sc->enabled == 1 && sc->disable != NULL) { 1946 (*sc->disable)(sc); 1947 sc->enabled = 0; 1948 } 1949 } 1950 1951 void 1952 ex_power(why, arg) 1953 int why; 1954 void *arg; 1955 { 1956 struct ex_softc *sc = (void *)arg; 1957 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1958 int s; 1959 1960 s = splnet(); 1961 switch (why) { 1962 case PWR_SUSPEND: 1963 case PWR_STANDBY: 1964 ex_stop(ifp, 0); 1965 if (sc->power != NULL) 1966 (*sc->power)(sc, why); 1967 break; 1968 case PWR_RESUME: 1969 if (ifp->if_flags & IFF_UP) { 1970 if (sc->power != NULL) 1971 (*sc->power)(sc, why); 1972 ex_init(ifp); 1973 } 1974 break; 1975 case PWR_SOFTSUSPEND: 1976 case PWR_SOFTSTANDBY: 1977 case PWR_SOFTRESUME: 1978 break; 1979 } 1980 splx(s); 1981 }
Cache object: b18ecf05afe82f232a69371eec113c71
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]