Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/gem.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /* $NetBSD: gem.c,v 1.78.4.1 2009/05/01 01:56:16 snj Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * Copyright (c) 2001-2003 Thomas Moestl 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 35 * See `GEM Gigabit Ethernet ASIC Specification' 36 * http://www.sun.com/processors/manuals/ge.pdf 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.78.4.1 2009/05/01 01:56:16 snj Exp $"); 41 42 #include "opt_inet.h" 43 #include "bpfilter.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/callout.h> 48 #include <sys/mbuf.h> 49 #include <sys/syslog.h> 50 #include <sys/malloc.h> 51 #include <sys/kernel.h> 52 #include <sys/socket.h> 53 #include <sys/ioctl.h> 54 #include <sys/errno.h> 55 #include <sys/device.h> 56 57 #include <machine/endian.h> 58 59 #include <uvm/uvm_extern.h> 60 61 #include <net/if.h> 62 #include <net/if_dl.h> 63 #include <net/if_media.h> 64 #include <net/if_ether.h> 65 66 #ifdef INET 67 #include <netinet/in.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/in_var.h> 70 #include <netinet/ip.h> 71 #include <netinet/tcp.h> 72 #include <netinet/udp.h> 73 #endif 74 75 #if NBPFILTER > 0 76 #include <net/bpf.h> 77 #endif 78 79 #include <sys/bus.h> 80 #include <sys/intr.h> 81 82 #include <dev/mii/mii.h> 83 #include <dev/mii/miivar.h> 84 #include <dev/mii/mii_bitbang.h> 85 86 #include <dev/ic/gemreg.h> 87 #include <dev/ic/gemvar.h> 88 89 #define TRIES 10000 90 91 static void gem_start(struct ifnet *); 92 static void gem_stop(struct ifnet *, int); 93 int gem_ioctl(struct ifnet *, u_long, void *); 94 void gem_tick(void *); 95 void gem_watchdog(struct ifnet *); 96 void gem_shutdown(void *); 97 void gem_pcs_start(struct gem_softc *sc); 98 void gem_pcs_stop(struct gem_softc *sc, int); 99 int gem_init(struct ifnet *); 100 void gem_init_regs(struct gem_softc *sc); 101 static int gem_ringsize(int sz); 102 static int gem_meminit(struct gem_softc *); 103 void gem_mifinit(struct gem_softc *); 104 static int gem_bitwait(struct gem_softc *sc, bus_space_handle_t, int, 105 u_int32_t, u_int32_t); 106 void gem_reset(struct gem_softc *); 107 int gem_reset_rx(struct gem_softc *sc); 108 static void gem_reset_rxdma(struct gem_softc *sc); 109 static void gem_rx_common(struct gem_softc *sc); 110 int gem_reset_tx(struct gem_softc *sc); 111 int gem_disable_rx(struct gem_softc *sc); 112 int gem_disable_tx(struct gem_softc *sc); 113 static void gem_rxdrain(struct gem_softc *sc); 114 int gem_add_rxbuf(struct gem_softc *sc, int idx); 115 void gem_setladrf(struct gem_softc *); 116 117 /* MII methods & callbacks */ 118 static int gem_mii_readreg(struct device *, int, int); 119 static void gem_mii_writereg(struct device *, int, int, int); 120 static void gem_mii_statchg(struct device *); 121 122 void gem_statuschange(struct gem_softc *); 123 124 int gem_ser_mediachange(struct ifnet *); 125 void gem_ser_mediastatus(struct ifnet *, struct ifmediareq *); 126 127 struct mbuf *gem_get(struct gem_softc *, int, int); 128 int gem_put(struct gem_softc *, int, struct mbuf *); 129 void gem_read(struct gem_softc *, int, int); 130 int gem_pint(struct gem_softc *); 131 int gem_eint(struct gem_softc *, u_int); 132 int gem_rint(struct gem_softc *); 133 int gem_tint(struct gem_softc *); 134 void gem_power(int, void *); 135 136 #ifdef GEM_DEBUG 137 static void gem_txsoft_print(const struct gem_softc *, int, int); 138 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 139 printf x 140 #else 141 #define DPRINTF(sc, x) /* nothing */ 142 #endif 143 144 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 145 146 147 /* 148 * gem_attach: 149 * 150 * Attach a Gem interface to the system. 151 */ 152 void 153 gem_attach(sc, enaddr) 154 struct gem_softc *sc; 155 const uint8_t *enaddr; 156 { 157 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 158 struct mii_data *mii = &sc->sc_mii; 159 bus_space_tag_t t = sc->sc_bustag; 160 bus_space_handle_t h = sc->sc_h1; 161 struct ifmedia_entry *ifm; 162 int i, error; 163 u_int32_t v; 164 char *nullbuf; 165 166 /* Make sure the chip is stopped. */ 167 ifp->if_softc = sc; 168 gem_reset(sc); 169 170 /* 171 * Allocate the control data structures, and create and load the 172 * DMA map for it. gem_control_data is 9216 bytes, we have space for 173 * the padding buffer in the bus_dmamem_alloc()'d memory. 174 */ 175 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 176 sizeof(struct gem_control_data) + ETHER_MIN_TX, PAGE_SIZE, 177 0, &sc->sc_cdseg, 1, &sc->sc_cdnseg, 0)) != 0) { 178 aprint_error_dev(&sc->sc_dev, 179 "unable to allocate control data, error = %d\n", 180 error); 181 goto fail_0; 182 } 183 184 /* XXX should map this in with correct endianness */ 185 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 186 sizeof(struct gem_control_data), (void **)&sc->sc_control_data, 187 BUS_DMA_COHERENT)) != 0) { 188 aprint_error_dev(&sc->sc_dev, "unable to map control data, error = %d\n", 189 error); 190 goto fail_1; 191 } 192 193 nullbuf = 194 (char *)sc->sc_control_data + sizeof(struct gem_control_data); 195 196 if ((error = bus_dmamap_create(sc->sc_dmatag, 197 sizeof(struct gem_control_data), 1, 198 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 199 aprint_error_dev(&sc->sc_dev, "unable to create control data DMA map, " 200 "error = %d\n", error); 201 goto fail_2; 202 } 203 204 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 205 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 206 0)) != 0) { 207 aprint_error_dev(&sc->sc_dev, 208 "unable to load control data DMA map, error = %d\n", 209 error); 210 goto fail_3; 211 } 212 213 memset(nullbuf, 0, ETHER_MIN_TX); 214 if ((error = bus_dmamap_create(sc->sc_dmatag, 215 ETHER_MIN_TX, 1, ETHER_MIN_TX, 0, 0, &sc->sc_nulldmamap)) != 0) { 216 aprint_error_dev(&sc->sc_dev, "unable to create padding DMA map, " 217 "error = %d\n", error); 218 goto fail_4; 219 } 220 221 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_nulldmamap, 222 nullbuf, ETHER_MIN_TX, NULL, 0)) != 0) { 223 aprint_error_dev(&sc->sc_dev, 224 "unable to load padding DMA map, error = %d\n", 225 error); 226 goto fail_5; 227 } 228 229 bus_dmamap_sync(sc->sc_dmatag, sc->sc_nulldmamap, 0, ETHER_MIN_TX, 230 BUS_DMASYNC_PREWRITE); 231 232 /* 233 * Initialize the transmit job descriptors. 234 */ 235 SIMPLEQ_INIT(&sc->sc_txfreeq); 236 SIMPLEQ_INIT(&sc->sc_txdirtyq); 237 238 /* 239 * Create the transmit buffer DMA maps. 240 */ 241 for (i = 0; i < GEM_TXQUEUELEN; i++) { 242 struct gem_txsoft *txs; 243 244 txs = &sc->sc_txsoft[i]; 245 txs->txs_mbuf = NULL; 246 if ((error = bus_dmamap_create(sc->sc_dmatag, 247 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 248 ETHER_MAX_LEN_JUMBO, 0, 0, 249 &txs->txs_dmamap)) != 0) { 250 aprint_error_dev(&sc->sc_dev, "unable to create tx DMA map %d, " 251 "error = %d\n", i, error); 252 goto fail_6; 253 } 254 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 255 } 256 257 /* 258 * Create the receive buffer DMA maps. 259 */ 260 for (i = 0; i < GEM_NRXDESC; i++) { 261 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 262 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 263 aprint_error_dev(&sc->sc_dev, "unable to create rx DMA map %d, " 264 "error = %d\n", i, error); 265 goto fail_7; 266 } 267 sc->sc_rxsoft[i].rxs_mbuf = NULL; 268 } 269 270 /* Initialize ifmedia structures and MII info */ 271 mii->mii_ifp = ifp; 272 mii->mii_readreg = gem_mii_readreg; 273 mii->mii_writereg = gem_mii_writereg; 274 mii->mii_statchg = gem_mii_statchg; 275 276 sc->sc_ethercom.ec_mii = mii; 277 278 /* 279 * Initialization based on `GEM Gigabit Ethernet ASIC Specification' 280 * Section 3.2.1 `Initialization Sequence'. 281 * However, we can't assume SERDES or Serialink if neither 282 * GEM_MIF_CONFIG_MDI0 nor GEM_MIF_CONFIG_MDI1 are set 283 * being set, as both are set on Sun X1141A (with SERDES). So, 284 * we rely on our bus attachment setting GEM_SERDES or GEM_SERIAL. 285 * Also, for Apple variants with 2 PHY's, we prefer the external 286 * PHY over the internal PHY. 287 */ 288 gem_mifinit(sc); 289 290 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 291 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 292 ether_mediastatus); 293 mii_attach(&sc->sc_dev, mii, 0xffffffff, 294 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 295 if (LIST_EMPTY(&mii->mii_phys)) { 296 /* No PHY attached */ 297 aprint_error_dev(&sc->sc_dev, "PHY probe failed\n"); 298 goto fail_7; 299 } else { 300 struct mii_softc *child; 301 302 /* 303 * Walk along the list of attached MII devices and 304 * establish an `MII instance' to `PHY number' 305 * mapping. 306 */ 307 LIST_FOREACH(child, &mii->mii_phys, mii_list) { 308 /* 309 * Note: we support just one PHY: the internal 310 * or external MII is already selected for us 311 * by the GEM_MIF_CONFIG register. 312 */ 313 if (child->mii_phy > 1 || child->mii_inst > 0) { 314 aprint_error_dev(&sc->sc_dev, 315 "cannot accommodate MII device" 316 " %s at PHY %d, instance %d\n", 317 device_xname(child->mii_dev), 318 child->mii_phy, child->mii_inst); 319 continue; 320 } 321 sc->sc_phys[child->mii_inst] = child->mii_phy; 322 } 323 324 /* 325 * Now select and activate the PHY we will use. 326 * 327 * The order of preference is External (MDI1), 328 * then Internal (MDI0), 329 */ 330 if (sc->sc_phys[1]) { 331 #ifdef GEM_DEBUG 332 aprint_debug_dev(&sc->sc_dev, "using external PHY\n"); 333 #endif 334 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 335 } else { 336 #ifdef GEM_DEBUG 337 aprint_debug_dev(&sc->sc_dev, "using internal PHY\n"); 338 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 339 #endif 340 } 341 bus_space_write_4(t, h, GEM_MIF_CONFIG, 342 sc->sc_mif_config); 343 if (sc->sc_variant != GEM_SUN_ERI) 344 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 345 GEM_MII_DATAPATH_MII); 346 347 /* 348 * XXX - we can really do the following ONLY if the 349 * PHY indeed has the auto negotiation capability!! 350 */ 351 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 352 } 353 } else { 354 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_ser_mediachange, 355 gem_ser_mediastatus); 356 /* SERDES or Serialink */ 357 if (sc->sc_flags & GEM_SERDES) { 358 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 359 GEM_MII_DATAPATH_SERDES); 360 } else { 361 sc->sc_flags |= GEM_SERIAL; 362 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 363 GEM_MII_DATAPATH_SERIAL); 364 } 365 366 aprint_normal_dev(&sc->sc_dev, "using external PCS %s: ", 367 sc->sc_flags & GEM_SERDES ? "SERDES" : "Serialink"); 368 369 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO, 0, NULL); 370 /* Check for FDX and HDX capabilities */ 371 sc->sc_mii_anar = bus_space_read_4(t, h, GEM_MII_ANAR); 372 if (sc->sc_mii_anar & GEM_MII_ANEG_FUL_DUPLX) { 373 ifmedia_add(&sc->sc_mii.mii_media, 374 IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_FDX, 0, NULL); 375 aprint_normal("1000baseSX-FDX, "); 376 } 377 if (sc->sc_mii_anar & GEM_MII_ANEG_HLF_DUPLX) { 378 ifmedia_add(&sc->sc_mii.mii_media, 379 IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_HDX, 0, NULL); 380 aprint_normal("1000baseSX-HDX, "); 381 } 382 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 383 sc->sc_mii_media = IFM_AUTO; 384 aprint_normal("auto\n"); 385 386 gem_pcs_stop(sc, 1); 387 } 388 389 /* 390 * From this point forward, the attachment cannot fail. A failure 391 * before this point releases all resources that may have been 392 * allocated. 393 */ 394 395 /* Announce ourselves. */ 396 aprint_normal_dev(&sc->sc_dev, "Ethernet address %s", 397 ether_sprintf(enaddr)); 398 399 /* Get RX FIFO size */ 400 sc->sc_rxfifosize = 64 * 401 bus_space_read_4(t, h, GEM_RX_FIFO_SIZE); 402 aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 403 404 /* Get TX FIFO size */ 405 v = bus_space_read_4(t, h, GEM_TX_FIFO_SIZE); 406 aprint_normal(", %uKB TX fifo\n", v / 16); 407 408 /* Initialize ifnet structure. */ 409 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 410 ifp->if_softc = sc; 411 ifp->if_flags = 412 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 413 sc->sc_if_flags = ifp->if_flags; 414 /* 415 * The GEM hardware supports basic TCP checksum offloading only. 416 * Several (all?) revisions (Sun rev. 01 and Apple rev. 00 and 80) 417 * have bugs in the receive checksum, so don't enable it for now. 418 if ((GEM_IS_SUN(sc) && sc->sc_chiprev != 1) || 419 (GEM_IS_APPLE(sc) && 420 (sc->sc_chiprev != 0 && sc->sc_chiprev != 0x80))) 421 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx; 422 */ 423 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Tx; 424 ifp->if_start = gem_start; 425 ifp->if_ioctl = gem_ioctl; 426 ifp->if_watchdog = gem_watchdog; 427 ifp->if_stop = gem_stop; 428 ifp->if_init = gem_init; 429 IFQ_SET_READY(&ifp->if_snd); 430 431 /* 432 * If we support GigE media, we support jumbo frames too. 433 * Unless we are Apple. 434 */ 435 TAILQ_FOREACH(ifm, &sc->sc_mii.mii_media.ifm_list, ifm_list) { 436 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 437 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 438 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 439 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 440 if (!GEM_IS_APPLE(sc)) 441 sc->sc_ethercom.ec_capabilities 442 |= ETHERCAP_JUMBO_MTU; 443 sc->sc_flags |= GEM_GIGABIT; 444 break; 445 } 446 } 447 448 /* claim 802.1q capability */ 449 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 450 451 /* Attach the interface. */ 452 if_attach(ifp); 453 ether_ifattach(ifp, enaddr); 454 455 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 456 if (sc->sc_sh == NULL) 457 panic("gem_config: can't establish shutdownhook"); 458 459 #if NRND > 0 460 rnd_attach_source(&sc->rnd_source, device_xname(&sc->sc_dev), 461 RND_TYPE_NET, 0); 462 #endif 463 464 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 465 NULL, device_xname(&sc->sc_dev), "interrupts"); 466 #ifdef GEM_COUNTERS 467 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 468 &sc->sc_ev_intr, device_xname(&sc->sc_dev), "tx interrupts"); 469 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 470 &sc->sc_ev_intr, device_xname(&sc->sc_dev), "rx interrupts"); 471 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 472 &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx ring full"); 473 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 474 &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx malloc failure"); 475 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 476 &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx 0desc"); 477 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 478 &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx 1desc"); 479 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 480 &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx 2desc"); 481 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 482 &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx 3desc"); 483 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 484 &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx >3desc"); 485 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 486 &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx >7desc"); 487 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 488 &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx >15desc"); 489 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 490 &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx >31desc"); 491 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 492 &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx >63desc"); 493 #endif 494 495 #if notyet 496 /* 497 * Add a suspend hook to make sure we come back up after a 498 * resume. 499 */ 500 sc->sc_powerhook = powerhook_establish(device_xname(&sc->sc_dev), 501 gem_power, sc); 502 if (sc->sc_powerhook == NULL) 503 aprint_error_dev(&sc->sc_dev, "WARNING: unable to establish power hook\n"); 504 #endif 505 506 callout_init(&sc->sc_tick_ch, 0); 507 return; 508 509 /* 510 * Free any resources we've allocated during the failed attach 511 * attempt. Do this in reverse order and fall through. 512 */ 513 fail_7: 514 for (i = 0; i < GEM_NRXDESC; i++) { 515 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 516 bus_dmamap_destroy(sc->sc_dmatag, 517 sc->sc_rxsoft[i].rxs_dmamap); 518 } 519 fail_6: 520 for (i = 0; i < GEM_TXQUEUELEN; i++) { 521 if (sc->sc_txsoft[i].txs_dmamap != NULL) 522 bus_dmamap_destroy(sc->sc_dmatag, 523 sc->sc_txsoft[i].txs_dmamap); 524 } 525 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 526 fail_5: 527 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_nulldmamap); 528 fail_4: 529 bus_dmamem_unmap(sc->sc_dmatag, (void *)nullbuf, ETHER_MIN_TX); 530 fail_3: 531 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 532 fail_2: 533 bus_dmamem_unmap(sc->sc_dmatag, (void *)sc->sc_control_data, 534 sizeof(struct gem_control_data)); 535 fail_1: 536 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 537 fail_0: 538 return; 539 } 540 541 542 void 543 gem_tick(arg) 544 void *arg; 545 { 546 struct gem_softc *sc = arg; 547 int s; 548 549 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) { 550 /* 551 * We have to reset everything if we failed to get a 552 * PCS interrupt. Restarting the callout is handled 553 * in gem_pcs_start(). 554 */ 555 gem_init(&sc->sc_ethercom.ec_if); 556 } else { 557 s = splnet(); 558 mii_tick(&sc->sc_mii); 559 splx(s); 560 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 561 } 562 } 563 564 static int 565 gem_bitwait(sc, h, r, clr, set) 566 struct gem_softc *sc; 567 bus_space_handle_t h; 568 int r; 569 u_int32_t clr; 570 u_int32_t set; 571 { 572 int i; 573 u_int32_t reg; 574 575 for (i = TRIES; i--; DELAY(100)) { 576 reg = bus_space_read_4(sc->sc_bustag, h, r); 577 if ((reg & clr) == 0 && (reg & set) == set) 578 return (1); 579 } 580 return (0); 581 } 582 583 void 584 gem_reset(sc) 585 struct gem_softc *sc; 586 { 587 bus_space_tag_t t = sc->sc_bustag; 588 bus_space_handle_t h = sc->sc_h2; 589 int s; 590 591 s = splnet(); 592 DPRINTF(sc, ("%s: gem_reset\n", device_xname(&sc->sc_dev))); 593 gem_reset_rx(sc); 594 gem_reset_tx(sc); 595 596 /* Do a full reset */ 597 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 598 if (!gem_bitwait(sc, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 599 aprint_error_dev(&sc->sc_dev, "cannot reset device\n"); 600 splx(s); 601 } 602 603 604 /* 605 * gem_rxdrain: 606 * 607 * Drain the receive queue. 608 */ 609 static void 610 gem_rxdrain(struct gem_softc *sc) 611 { 612 struct gem_rxsoft *rxs; 613 int i; 614 615 for (i = 0; i < GEM_NRXDESC; i++) { 616 rxs = &sc->sc_rxsoft[i]; 617 if (rxs->rxs_mbuf != NULL) { 618 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 619 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 620 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 621 m_freem(rxs->rxs_mbuf); 622 rxs->rxs_mbuf = NULL; 623 } 624 } 625 } 626 627 /* 628 * Reset the whole thing. 629 */ 630 static void 631 gem_stop(struct ifnet *ifp, int disable) 632 { 633 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 634 struct gem_txsoft *txs; 635 636 DPRINTF(sc, ("%s: gem_stop\n", device_xname(&sc->sc_dev))); 637 638 callout_stop(&sc->sc_tick_ch); 639 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 640 gem_pcs_stop(sc, disable); 641 else 642 mii_down(&sc->sc_mii); 643 644 /* XXX - Should we reset these instead? */ 645 gem_disable_tx(sc); 646 gem_disable_rx(sc); 647 648 /* 649 * Release any queued transmit buffers. 650 */ 651 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 652 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 653 if (txs->txs_mbuf != NULL) { 654 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 0, 655 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 656 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 657 m_freem(txs->txs_mbuf); 658 txs->txs_mbuf = NULL; 659 } 660 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 661 } 662 663 /* 664 * Mark the interface down and cancel the watchdog timer. 665 */ 666 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 667 sc->sc_if_flags = ifp->if_flags; 668 ifp->if_timer = 0; 669 670 if (disable) 671 gem_rxdrain(sc); 672 } 673 674 675 /* 676 * Reset the receiver 677 */ 678 int 679 gem_reset_rx(struct gem_softc *sc) 680 { 681 bus_space_tag_t t = sc->sc_bustag; 682 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 683 684 /* 685 * Resetting while DMA is in progress can cause a bus hang, so we 686 * disable DMA first. 687 */ 688 gem_disable_rx(sc); 689 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 690 bus_space_barrier(t, h, GEM_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 691 /* Wait till it finishes */ 692 if (!gem_bitwait(sc, h, GEM_RX_CONFIG, 1, 0)) 693 aprint_error_dev(&sc->sc_dev, "cannot disable read dma\n"); 694 695 /* Finally, reset the ERX */ 696 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_RX); 697 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 698 /* Wait till it finishes */ 699 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_RX, 0)) { 700 aprint_error_dev(&sc->sc_dev, "cannot reset receiver\n"); 701 return (1); 702 } 703 return (0); 704 } 705 706 707 /* 708 * Reset the receiver DMA engine. 709 * 710 * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW 711 * etc in order to reset the receiver DMA engine only and not do a full 712 * reset which amongst others also downs the link and clears the FIFOs. 713 */ 714 static void 715 gem_reset_rxdma(struct gem_softc *sc) 716 { 717 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 718 bus_space_tag_t t = sc->sc_bustag; 719 bus_space_handle_t h = sc->sc_h1; 720 int i; 721 722 if (gem_reset_rx(sc) != 0) { 723 gem_init(ifp); 724 return; 725 } 726 for (i = 0; i < GEM_NRXDESC; i++) 727 if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 728 GEM_UPDATE_RXDESC(sc, i); 729 sc->sc_rxptr = 0; 730 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 731 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 732 733 /* Reprogram Descriptor Ring Base Addresses */ 734 /* NOTE: we use only 32-bit DMA addresses here. */ 735 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 736 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 737 738 /* Redo ERX Configuration */ 739 gem_rx_common(sc); 740 741 /* Give the reciever a swift kick */ 742 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC - 4); 743 } 744 745 /* 746 * Common RX configuration for gem_init() and gem_reset_rxdma(). 747 */ 748 static void 749 gem_rx_common(struct gem_softc *sc) 750 { 751 bus_space_tag_t t = sc->sc_bustag; 752 bus_space_handle_t h = sc->sc_h1; 753 u_int32_t v; 754 755 /* Encode Receive Descriptor ring size: four possible values */ 756 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 757 758 /* Set receive h/w checksum offset */ 759 #ifdef INET 760 v |= (ETHER_HDR_LEN + sizeof(struct ip) + 761 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 762 ETHER_VLAN_ENCAP_LEN : 0)) << GEM_RX_CONFIG_CXM_START_SHFT; 763 #endif 764 765 /* Enable RX DMA */ 766 bus_space_write_4(t, h, GEM_RX_CONFIG, 767 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 768 (2 << GEM_RX_CONFIG_FBOFF_SHFT) | GEM_RX_CONFIG_RXDMA_EN); 769 770 /* 771 * The following value is for an OFF Threshold of about 3/4 full 772 * and an ON Threshold of 1/4 full. 773 */ 774 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 775 (3 * sc->sc_rxfifosize / 256) | 776 ((sc->sc_rxfifosize / 256) << 12)); 777 bus_space_write_4(t, h, GEM_RX_BLANKING, 778 (6 << GEM_RX_BLANKING_TIME_SHIFT) | 6); 779 } 780 781 /* 782 * Reset the transmitter 783 */ 784 int 785 gem_reset_tx(struct gem_softc *sc) 786 { 787 bus_space_tag_t t = sc->sc_bustag; 788 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 789 790 /* 791 * Resetting while DMA is in progress can cause a bus hang, so we 792 * disable DMA first. 793 */ 794 gem_disable_tx(sc); 795 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 796 bus_space_barrier(t, h, GEM_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 797 /* Wait till it finishes */ 798 if (!gem_bitwait(sc, h, GEM_TX_CONFIG, 1, 0)) 799 aprint_error_dev(&sc->sc_dev, "cannot disable read dma\n"); 800 /* Wait 5ms extra. */ 801 delay(5000); 802 803 /* Finally, reset the ETX */ 804 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_TX); 805 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 806 /* Wait till it finishes */ 807 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_TX, 0)) { 808 aprint_error_dev(&sc->sc_dev, "cannot reset receiver\n"); 809 return (1); 810 } 811 return (0); 812 } 813 814 /* 815 * disable receiver. 816 */ 817 int 818 gem_disable_rx(struct gem_softc *sc) 819 { 820 bus_space_tag_t t = sc->sc_bustag; 821 bus_space_handle_t h = sc->sc_h1; 822 u_int32_t cfg; 823 824 /* Flip the enable bit */ 825 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 826 cfg &= ~GEM_MAC_RX_ENABLE; 827 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 828 bus_space_barrier(t, h, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 829 /* Wait for it to finish */ 830 return (gem_bitwait(sc, h, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 831 } 832 833 /* 834 * disable transmitter. 835 */ 836 int 837 gem_disable_tx(struct gem_softc *sc) 838 { 839 bus_space_tag_t t = sc->sc_bustag; 840 bus_space_handle_t h = sc->sc_h1; 841 u_int32_t cfg; 842 843 /* Flip the enable bit */ 844 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 845 cfg &= ~GEM_MAC_TX_ENABLE; 846 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 847 bus_space_barrier(t, h, GEM_MAC_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 848 /* Wait for it to finish */ 849 return (gem_bitwait(sc, h, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 850 } 851 852 /* 853 * Initialize interface. 854 */ 855 int 856 gem_meminit(struct gem_softc *sc) 857 { 858 struct gem_rxsoft *rxs; 859 int i, error; 860 861 /* 862 * Initialize the transmit descriptor ring. 863 */ 864 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 865 for (i = 0; i < GEM_NTXDESC; i++) { 866 sc->sc_txdescs[i].gd_flags = 0; 867 sc->sc_txdescs[i].gd_addr = 0; 868 } 869 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 870 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 871 sc->sc_txfree = GEM_NTXDESC-1; 872 sc->sc_txnext = 0; 873 sc->sc_txwin = 0; 874 875 /* 876 * Initialize the receive descriptor and receive job 877 * descriptor rings. 878 */ 879 for (i = 0; i < GEM_NRXDESC; i++) { 880 rxs = &sc->sc_rxsoft[i]; 881 if (rxs->rxs_mbuf == NULL) { 882 if ((error = gem_add_rxbuf(sc, i)) != 0) { 883 aprint_error_dev(&sc->sc_dev, "unable to allocate or map rx " 884 "buffer %d, error = %d\n", 885 i, error); 886 /* 887 * XXX Should attempt to run with fewer receive 888 * XXX buffers instead of just failing. 889 */ 890 gem_rxdrain(sc); 891 return (1); 892 } 893 } else 894 GEM_INIT_RXDESC(sc, i); 895 } 896 sc->sc_rxptr = 0; 897 sc->sc_meminited = 1; 898 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 899 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 900 901 return (0); 902 } 903 904 static int 905 gem_ringsize(int sz) 906 { 907 switch (sz) { 908 case 32: 909 return GEM_RING_SZ_32; 910 case 64: 911 return GEM_RING_SZ_64; 912 case 128: 913 return GEM_RING_SZ_128; 914 case 256: 915 return GEM_RING_SZ_256; 916 case 512: 917 return GEM_RING_SZ_512; 918 case 1024: 919 return GEM_RING_SZ_1024; 920 case 2048: 921 return GEM_RING_SZ_2048; 922 case 4096: 923 return GEM_RING_SZ_4096; 924 case 8192: 925 return GEM_RING_SZ_8192; 926 default: 927 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 928 return GEM_RING_SZ_32; 929 } 930 } 931 932 933 /* 934 * Start PCS 935 */ 936 void 937 gem_pcs_start(struct gem_softc *sc) 938 { 939 bus_space_tag_t t = sc->sc_bustag; 940 bus_space_handle_t h = sc->sc_h1; 941 uint32_t v; 942 943 #ifdef GEM_DEBUG 944 aprint_debug_dev(&sc->sc_dev, "gem_pcs_start()\n"); 945 #endif 946 947 /* 948 * Set up. We must disable the MII before modifying the 949 * GEM_MII_ANAR register 950 */ 951 if (sc->sc_flags & GEM_SERDES) { 952 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 953 GEM_MII_DATAPATH_SERDES); 954 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 955 GEM_MII_SLINK_LOOPBACK); 956 } else { 957 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 958 GEM_MII_DATAPATH_SERIAL); 959 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 0); 960 } 961 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 962 v = bus_space_read_4(t, h, GEM_MII_ANAR); 963 v |= (GEM_MII_ANEG_SYM_PAUSE | GEM_MII_ANEG_ASYM_PAUSE); 964 if (sc->sc_mii_media == IFM_AUTO) 965 v |= (GEM_MII_ANEG_FUL_DUPLX | GEM_MII_ANEG_HLF_DUPLX); 966 else if (sc->sc_mii_media == IFM_FDX) { 967 v |= GEM_MII_ANEG_FUL_DUPLX; 968 v &= ~GEM_MII_ANEG_HLF_DUPLX; 969 } else if (sc->sc_mii_media == IFM_HDX) { 970 v &= ~GEM_MII_ANEG_FUL_DUPLX; 971 v |= GEM_MII_ANEG_HLF_DUPLX; 972 } 973 974 /* Configure link. */ 975 bus_space_write_4(t, h, GEM_MII_ANAR, v); 976 bus_space_write_4(t, h, GEM_MII_CONTROL, 977 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 978 bus_space_write_4(t, h, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 979 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_ANEG_CPT); 980 981 /* Start the 10 second timer */ 982 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 983 } 984 985 /* 986 * Stop PCS 987 */ 988 void 989 gem_pcs_stop(struct gem_softc *sc, int disable) 990 { 991 bus_space_tag_t t = sc->sc_bustag; 992 bus_space_handle_t h = sc->sc_h1; 993 994 #ifdef GEM_DEBUG 995 aprint_debug_dev(&sc->sc_dev, "gem_pcs_stop()\n"); 996 #endif 997 998 /* Tell link partner that we're going away */ 999 bus_space_write_4(t, h, GEM_MII_ANAR, GEM_MII_ANEG_RF); 1000 1001 /* 1002 * Disable PCS MII. The documentation suggests that setting 1003 * GEM_MII_CONFIG_ENABLE to zero and then restarting auto- 1004 * negotiation will shut down the link. However, it appears 1005 * that we also need to unset the datapath mode. 1006 */ 1007 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1008 bus_space_write_4(t, h, GEM_MII_CONTROL, 1009 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1010 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, GEM_MII_DATAPATH_MII); 1011 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1012 1013 if (disable) { 1014 if (sc->sc_flags & GEM_SERDES) 1015 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1016 GEM_MII_SLINK_POWER_OFF); 1017 else 1018 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1019 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_POWER_OFF); 1020 } 1021 1022 sc->sc_flags &= ~GEM_LINK; 1023 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 1024 sc->sc_mii.mii_media_status = IFM_AVALID; 1025 } 1026 1027 1028 /* 1029 * Initialization of interface; set up initialization block 1030 * and transmit/receive descriptor rings. 1031 */ 1032 int 1033 gem_init(struct ifnet *ifp) 1034 { 1035 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 1036 bus_space_tag_t t = sc->sc_bustag; 1037 bus_space_handle_t h = sc->sc_h1; 1038 int rc = 0, s; 1039 u_int max_frame_size; 1040 u_int32_t v; 1041 1042 s = splnet(); 1043 1044 DPRINTF(sc, ("%s: gem_init: calling stop\n", device_xname(&sc->sc_dev))); 1045 /* 1046 * Initialization sequence. The numbered steps below correspond 1047 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1048 * Channel Engine manual (part of the PCIO manual). 1049 * See also the STP2002-STQ document from Sun Microsystems. 1050 */ 1051 1052 /* step 1 & 2. Reset the Ethernet Channel */ 1053 gem_stop(ifp, 0); 1054 gem_reset(sc); 1055 DPRINTF(sc, ("%s: gem_init: restarting\n", device_xname(&sc->sc_dev))); 1056 1057 /* Re-initialize the MIF */ 1058 gem_mifinit(sc); 1059 1060 /* Set up correct datapath for non-SERDES/Serialink */ 1061 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1062 sc->sc_variant != GEM_SUN_ERI) 1063 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1064 GEM_MII_DATAPATH_MII); 1065 1066 /* Call MI reset function if any */ 1067 if (sc->sc_hwreset) 1068 (*sc->sc_hwreset)(sc); 1069 1070 /* step 3. Setup data structures in host memory */ 1071 if (gem_meminit(sc) != 0) 1072 return 1; 1073 1074 /* step 4. TX MAC registers & counters */ 1075 gem_init_regs(sc); 1076 max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 1077 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 1078 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1079 max_frame_size += ETHER_VLAN_ENCAP_LEN; 1080 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1081 max_frame_size|/* burst size */(0x2000<<16)); 1082 1083 /* step 5. RX MAC registers & counters */ 1084 gem_setladrf(sc); 1085 1086 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1087 /* NOTE: we use only 32-bit DMA addresses here. */ 1088 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 1089 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 1090 1091 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 1092 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 1093 1094 /* step 8. Global Configuration & Interrupt Mask */ 1095 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 1096 v = GEM_INTR_PCS; 1097 else 1098 v = GEM_INTR_MIF; 1099 bus_space_write_4(t, h, GEM_INTMASK, 1100 ~(GEM_INTR_TX_INTME | 1101 GEM_INTR_TX_EMPTY | 1102 GEM_INTR_TX_MAC | 1103 GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF| 1104 GEM_INTR_RX_TAG_ERR | GEM_INTR_MAC_CONTROL| 1105 GEM_INTR_BERR | v)); 1106 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 1107 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 1108 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXX */ 1109 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 1110 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 1111 1112 /* step 9. ETX Configuration: use mostly default values */ 1113 1114 /* Enable TX DMA */ 1115 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 1116 bus_space_write_4(t, h, GEM_TX_CONFIG, 1117 v|GEM_TX_CONFIG_TXDMA_EN| 1118 ((0x4FF<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 1119 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 1120 1121 /* step 10. ERX Configuration */ 1122 gem_rx_common(sc); 1123 1124 /* step 11. Configure Media */ 1125 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1126 (rc = mii_ifmedia_change(&sc->sc_mii)) != 0) 1127 goto out; 1128 1129 /* step 12. RX_MAC Configuration Register */ 1130 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1131 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 1132 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1133 1134 /* step 14. Issue Transmit Pending command */ 1135 1136 /* Call MI initialization function if any */ 1137 if (sc->sc_hwinit) 1138 (*sc->sc_hwinit)(sc); 1139 1140 1141 /* step 15. Give the reciever a swift kick */ 1142 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 1143 1144 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 1145 /* Configure PCS */ 1146 gem_pcs_start(sc); 1147 else 1148 /* Start the one second timer. */ 1149 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 1150 1151 sc->sc_flags &= ~GEM_LINK; 1152 ifp->if_flags |= IFF_RUNNING; 1153 ifp->if_flags &= ~IFF_OACTIVE; 1154 ifp->if_timer = 0; 1155 sc->sc_if_flags = ifp->if_flags; 1156 out: 1157 splx(s); 1158 1159 return (0); 1160 } 1161 1162 void 1163 gem_init_regs(struct gem_softc *sc) 1164 { 1165 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1166 bus_space_tag_t t = sc->sc_bustag; 1167 bus_space_handle_t h = sc->sc_h1; 1168 const u_char *laddr = CLLADDR(ifp->if_sadl); 1169 u_int32_t v; 1170 1171 /* These regs are not cleared on reset */ 1172 if (!sc->sc_inited) { 1173 1174 /* Load recommended values */ 1175 bus_space_write_4(t, h, GEM_MAC_IPG0, 0x00); 1176 bus_space_write_4(t, h, GEM_MAC_IPG1, 0x08); 1177 bus_space_write_4(t, h, GEM_MAC_IPG2, 0x04); 1178 1179 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1180 /* Max frame and max burst size */ 1181 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1182 ETHER_MAX_LEN | (0x2000<<16)); 1183 1184 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x07); 1185 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x04); 1186 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1187 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 1188 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 1189 ((laddr[5]<<8)|laddr[4])&0x3ff); 1190 1191 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 1192 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 1193 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 1194 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 1195 1196 /* MAC control addr set to 01:80:c2:00:00:01 */ 1197 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 1198 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 1199 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 1200 1201 /* MAC filter addr set to 0:0:0:0:0:0 */ 1202 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 1203 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 1204 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 1205 1206 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 1207 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 1208 1209 sc->sc_inited = 1; 1210 } 1211 1212 /* Counters need to be zeroed */ 1213 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 1214 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 1215 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 1216 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 1217 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 1218 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 1219 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 1220 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1221 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1222 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1223 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1224 1225 /* Set XOFF PAUSE time. */ 1226 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1227 1228 /* 1229 * Set the internal arbitration to "infinite" bursts of the 1230 * maximum length of 31 * 64 bytes so DMA transfers aren't 1231 * split up in cache line size chunks. This greatly improves 1232 * especially RX performance. 1233 * Enable silicon bug workarounds for the Apple variants. 1234 */ 1235 bus_space_write_4(t, h, GEM_CONFIG, 1236 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 1237 ((sc->sc_flags & GEM_PCI) ? 1238 GEM_CONFIG_BURST_INF : GEM_CONFIG_BURST_64) | (GEM_IS_APPLE(sc) ? 1239 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 1240 1241 /* 1242 * Set the station address. 1243 */ 1244 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 1245 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 1246 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 1247 1248 /* 1249 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 1250 */ 1251 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 1252 v = GEM_MAC_XIF_TX_MII_ENA; 1253 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 1254 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 1255 v |= GEM_MAC_XIF_FDPLX_LED; 1256 if (sc->sc_flags & GEM_GIGABIT) 1257 v |= GEM_MAC_XIF_GMII_MODE; 1258 } 1259 } else { 1260 v |= GEM_MAC_XIF_GMII_MODE; 1261 } 1262 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 1263 } 1264 1265 #ifdef GEM_DEBUG 1266 static void 1267 gem_txsoft_print(const struct gem_softc *sc, int firstdesc, int lastdesc) 1268 { 1269 int i; 1270 1271 for (i = firstdesc;; i = GEM_NEXTTX(i)) { 1272 printf("descriptor %d:\t", i); 1273 printf("gd_flags: 0x%016" PRIx64 "\t", 1274 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1275 printf("gd_addr: 0x%016" PRIx64 "\n", 1276 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1277 if (i == lastdesc) 1278 break; 1279 } 1280 } 1281 #endif 1282 1283 static void 1284 gem_start(ifp) 1285 struct ifnet *ifp; 1286 { 1287 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 1288 struct mbuf *m0, *m; 1289 struct gem_txsoft *txs; 1290 bus_dmamap_t dmamap; 1291 int error, firsttx, nexttx = -1, lasttx = -1, ofree, seg; 1292 uint64_t flags = 0; 1293 1294 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1295 return; 1296 1297 /* 1298 * Remember the previous number of free descriptors and 1299 * the first descriptor we'll use. 1300 */ 1301 ofree = sc->sc_txfree; 1302 firsttx = sc->sc_txnext; 1303 1304 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 1305 device_xname(&sc->sc_dev), ofree, firsttx)); 1306 1307 /* 1308 * Loop through the send queue, setting up transmit descriptors 1309 * until we drain the queue, or use up all available transmit 1310 * descriptors. 1311 */ 1312 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1313 sc->sc_txfree != 0) { 1314 /* 1315 * Grab a packet off the queue. 1316 */ 1317 IFQ_POLL(&ifp->if_snd, m0); 1318 if (m0 == NULL) 1319 break; 1320 m = NULL; 1321 1322 dmamap = txs->txs_dmamap; 1323 1324 /* 1325 * Load the DMA map. If this fails, the packet either 1326 * didn't fit in the alloted number of segments, or we were 1327 * short on resources. In this case, we'll copy and try 1328 * again. 1329 */ 1330 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1331 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0 || 1332 (m0->m_pkthdr.len < ETHER_MIN_TX && 1333 dmamap->dm_nsegs == GEM_NTXSEGS)) { 1334 if (m0->m_pkthdr.len > MCLBYTES) { 1335 aprint_error_dev(&sc->sc_dev, "unable to allocate jumbo Tx " 1336 "cluster\n"); 1337 IFQ_DEQUEUE(&ifp->if_snd, m0); 1338 m_freem(m0); 1339 continue; 1340 } 1341 MGETHDR(m, M_DONTWAIT, MT_DATA); 1342 if (m == NULL) { 1343 aprint_error_dev(&sc->sc_dev, "unable to allocate Tx mbuf\n"); 1344 break; 1345 } 1346 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1347 if (m0->m_pkthdr.len > MHLEN) { 1348 MCLGET(m, M_DONTWAIT); 1349 if ((m->m_flags & M_EXT) == 0) { 1350 aprint_error_dev(&sc->sc_dev, "unable to allocate Tx " 1351 "cluster\n"); 1352 m_freem(m); 1353 break; 1354 } 1355 } 1356 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1357 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1358 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1359 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1360 if (error) { 1361 aprint_error_dev(&sc->sc_dev, "unable to load Tx buffer, " 1362 "error = %d\n", error); 1363 break; 1364 } 1365 } 1366 1367 /* 1368 * Ensure we have enough descriptors free to describe 1369 * the packet. 1370 */ 1371 if (dmamap->dm_nsegs > ((m0->m_pkthdr.len < ETHER_MIN_TX) ? 1372 (sc->sc_txfree - 1) : sc->sc_txfree)) { 1373 /* 1374 * Not enough free descriptors to transmit this 1375 * packet. We haven't committed to anything yet, 1376 * so just unload the DMA map, put the packet 1377 * back on the queue, and punt. Notify the upper 1378 * layer that there are no more slots left. 1379 * 1380 * XXX We could allocate an mbuf and copy, but 1381 * XXX it is worth it? 1382 */ 1383 ifp->if_flags |= IFF_OACTIVE; 1384 sc->sc_if_flags = ifp->if_flags; 1385 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1386 if (m != NULL) 1387 m_freem(m); 1388 break; 1389 } 1390 1391 IFQ_DEQUEUE(&ifp->if_snd, m0); 1392 if (m != NULL) { 1393 m_freem(m0); 1394 m0 = m; 1395 } 1396 1397 /* 1398 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1399 */ 1400 1401 /* Sync the DMA map. */ 1402 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1403 BUS_DMASYNC_PREWRITE); 1404 1405 /* 1406 * Initialize the transmit descriptors. 1407 */ 1408 for (nexttx = sc->sc_txnext, seg = 0; 1409 seg < dmamap->dm_nsegs; 1410 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1411 1412 /* 1413 * If this is the first descriptor we're 1414 * enqueueing, set the start of packet flag, 1415 * and the checksum stuff if we want the hardware 1416 * to do it. 1417 */ 1418 sc->sc_txdescs[nexttx].gd_addr = 1419 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1420 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1421 if (nexttx == firsttx) { 1422 flags |= GEM_TD_START_OF_PACKET; 1423 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1424 sc->sc_txwin = 0; 1425 flags |= GEM_TD_INTERRUPT_ME; 1426 } 1427 1428 #ifdef INET 1429 /* h/w checksum */ 1430 if (ifp->if_csum_flags_tx & M_CSUM_TCPv4 && 1431 m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1432 struct ether_header *eh; 1433 uint16_t offset, start; 1434 1435 eh = mtod(m0, struct ether_header *); 1436 switch (ntohs(eh->ether_type)) { 1437 case ETHERTYPE_IP: 1438 start = ETHER_HDR_LEN; 1439 break; 1440 case ETHERTYPE_VLAN: 1441 start = ETHER_HDR_LEN + 1442 ETHER_VLAN_ENCAP_LEN; 1443 break; 1444 default: 1445 /* unsupported, drop it */ 1446 m_free(m0); 1447 continue; 1448 } 1449 start += M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1450 offset = M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data) + start; 1451 flags |= (start << 1452 GEM_TD_CXSUM_STARTSHFT) | 1453 (offset << 1454 GEM_TD_CXSUM_STUFFSHFT) | 1455 GEM_TD_CXSUM_ENABLE; 1456 } 1457 #endif 1458 } 1459 if (seg == dmamap->dm_nsegs - 1) { 1460 flags |= GEM_TD_END_OF_PACKET; 1461 } else { 1462 /* last flag set outside of loop */ 1463 sc->sc_txdescs[nexttx].gd_flags = 1464 GEM_DMA_WRITE(sc, flags); 1465 } 1466 lasttx = nexttx; 1467 } 1468 if (m0->m_pkthdr.len < ETHER_MIN_TX) { 1469 /* add padding buffer at end of chain */ 1470 flags &= ~GEM_TD_END_OF_PACKET; 1471 sc->sc_txdescs[lasttx].gd_flags = 1472 GEM_DMA_WRITE(sc, flags); 1473 1474 sc->sc_txdescs[nexttx].gd_addr = 1475 GEM_DMA_WRITE(sc, 1476 sc->sc_nulldmamap->dm_segs[0].ds_addr); 1477 flags = ((ETHER_MIN_TX - m0->m_pkthdr.len) & 1478 GEM_TD_BUFSIZE) | GEM_TD_END_OF_PACKET; 1479 lasttx = nexttx; 1480 nexttx = GEM_NEXTTX(nexttx); 1481 seg++; 1482 } 1483 sc->sc_txdescs[lasttx].gd_flags = GEM_DMA_WRITE(sc, flags); 1484 1485 KASSERT(lasttx != -1); 1486 1487 /* 1488 * Store a pointer to the packet so we can free it later, 1489 * and remember what txdirty will be once the packet is 1490 * done. 1491 */ 1492 txs->txs_mbuf = m0; 1493 txs->txs_firstdesc = sc->sc_txnext; 1494 txs->txs_lastdesc = lasttx; 1495 txs->txs_ndescs = seg; 1496 1497 #ifdef GEM_DEBUG 1498 if (ifp->if_flags & IFF_DEBUG) { 1499 printf(" gem_start %p transmit chain:\n", txs); 1500 gem_txsoft_print(sc, txs->txs_firstdesc, 1501 txs->txs_lastdesc); 1502 } 1503 #endif 1504 1505 /* Sync the descriptors we're using. */ 1506 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1507 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1508 1509 /* Advance the tx pointer. */ 1510 sc->sc_txfree -= txs->txs_ndescs; 1511 sc->sc_txnext = nexttx; 1512 1513 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1514 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1515 1516 #if NBPFILTER > 0 1517 /* 1518 * Pass the packet to any BPF listeners. 1519 */ 1520 if (ifp->if_bpf) 1521 bpf_mtap(ifp->if_bpf, m0); 1522 #endif /* NBPFILTER > 0 */ 1523 } 1524 1525 if (txs == NULL || sc->sc_txfree == 0) { 1526 /* No more slots left; notify upper layer. */ 1527 ifp->if_flags |= IFF_OACTIVE; 1528 sc->sc_if_flags = ifp->if_flags; 1529 } 1530 1531 if (sc->sc_txfree != ofree) { 1532 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1533 device_xname(&sc->sc_dev), lasttx, firsttx)); 1534 /* 1535 * The entire packet chain is set up. 1536 * Kick the transmitter. 1537 */ 1538 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1539 device_xname(&sc->sc_dev), nexttx)); 1540 bus_space_write_4(sc->sc_bustag, sc->sc_h1, GEM_TX_KICK, 1541 sc->sc_txnext); 1542 1543 /* Set a watchdog timer in case the chip flakes out. */ 1544 ifp->if_timer = 5; 1545 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1546 device_xname(&sc->sc_dev), ifp->if_timer)); 1547 } 1548 } 1549 1550 /* 1551 * Transmit interrupt. 1552 */ 1553 int 1554 gem_tint(sc) 1555 struct gem_softc *sc; 1556 { 1557 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1558 bus_space_tag_t t = sc->sc_bustag; 1559 bus_space_handle_t mac = sc->sc_h1; 1560 struct gem_txsoft *txs; 1561 int txlast; 1562 int progress = 0; 1563 u_int32_t v; 1564 1565 DPRINTF(sc, ("%s: gem_tint\n", device_xname(&sc->sc_dev))); 1566 1567 /* Unload collision counters ... */ 1568 v = bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1569 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1570 ifp->if_collisions += v + 1571 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1572 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT); 1573 ifp->if_oerrors += v; 1574 1575 /* ... then clear the hardware counters. */ 1576 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1577 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1578 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1579 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1580 1581 /* 1582 * Go through our Tx list and free mbufs for those 1583 * frames that have been transmitted. 1584 */ 1585 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1586 /* 1587 * In theory, we could harvest some descriptors before 1588 * the ring is empty, but that's a bit complicated. 1589 * 1590 * GEM_TX_COMPLETION points to the last descriptor 1591 * processed +1. 1592 * 1593 * Let's assume that the NIC writes back to the Tx 1594 * descriptors before it updates the completion 1595 * register. If the NIC has posted writes to the 1596 * Tx descriptors, PCI ordering requires that the 1597 * posted writes flush to RAM before the register-read 1598 * finishes. So let's read the completion register, 1599 * before syncing the descriptors, so that we 1600 * examine Tx descriptors that are at least as 1601 * current as the completion register. 1602 */ 1603 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1604 DPRINTF(sc, 1605 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1606 txs->txs_lastdesc, txlast)); 1607 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1608 if (txlast >= txs->txs_firstdesc && 1609 txlast <= txs->txs_lastdesc) 1610 break; 1611 } else if (txlast >= txs->txs_firstdesc || 1612 txlast <= txs->txs_lastdesc) 1613 break; 1614 1615 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1616 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1617 1618 #ifdef GEM_DEBUG /* XXX DMA synchronization? */ 1619 if (ifp->if_flags & IFF_DEBUG) { 1620 printf(" txsoft %p transmit chain:\n", txs); 1621 gem_txsoft_print(sc, txs->txs_firstdesc, 1622 txs->txs_lastdesc); 1623 } 1624 #endif 1625 1626 1627 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1628 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1629 1630 sc->sc_txfree += txs->txs_ndescs; 1631 1632 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1633 0, txs->txs_dmamap->dm_mapsize, 1634 BUS_DMASYNC_POSTWRITE); 1635 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1636 if (txs->txs_mbuf != NULL) { 1637 m_freem(txs->txs_mbuf); 1638 txs->txs_mbuf = NULL; 1639 } 1640 1641 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1642 1643 ifp->if_opackets++; 1644 progress = 1; 1645 } 1646 1647 #if 0 1648 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1649 "GEM_TX_DATA_PTR %" PRIx64 "GEM_TX_COMPLETION %" PRIx32 "\n", 1650 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_STATE_MACHINE), 1651 ((uint64_t)bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1652 GEM_TX_DATA_PTR_HI) << 32) | 1653 bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1654 GEM_TX_DATA_PTR_LO), 1655 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_COMPLETION))); 1656 #endif 1657 1658 if (progress) { 1659 if (sc->sc_txfree == GEM_NTXDESC - 1) 1660 sc->sc_txwin = 0; 1661 1662 /* Freed some descriptors, so reset IFF_OACTIVE and restart. */ 1663 ifp->if_flags &= ~IFF_OACTIVE; 1664 sc->sc_if_flags = ifp->if_flags; 1665 ifp->if_timer = SIMPLEQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 1666 gem_start(ifp); 1667 } 1668 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1669 device_xname(&sc->sc_dev), ifp->if_timer)); 1670 1671 return (1); 1672 } 1673 1674 /* 1675 * Receive interrupt. 1676 */ 1677 int 1678 gem_rint(sc) 1679 struct gem_softc *sc; 1680 { 1681 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1682 bus_space_tag_t t = sc->sc_bustag; 1683 bus_space_handle_t h = sc->sc_h1; 1684 struct gem_rxsoft *rxs; 1685 struct mbuf *m; 1686 u_int64_t rxstat; 1687 u_int32_t rxcomp; 1688 int i, len, progress = 0; 1689 1690 DPRINTF(sc, ("%s: gem_rint\n", device_xname(&sc->sc_dev))); 1691 1692 /* 1693 * Ignore spurious interrupt that sometimes occurs before 1694 * we are set up when we network boot. 1695 */ 1696 if (!sc->sc_meminited) 1697 return 1; 1698 1699 /* 1700 * Read the completion register once. This limits 1701 * how long the following loop can execute. 1702 */ 1703 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1704 1705 /* 1706 * XXX Read the lastrx only once at the top for speed. 1707 */ 1708 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1709 sc->sc_rxptr, rxcomp)); 1710 1711 /* 1712 * Go into the loop at least once. 1713 */ 1714 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1715 i = GEM_NEXTRX(i)) { 1716 rxs = &sc->sc_rxsoft[i]; 1717 1718 GEM_CDRXSYNC(sc, i, 1719 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1720 1721 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1722 1723 if (rxstat & GEM_RD_OWN) { 1724 GEM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1725 /* 1726 * We have processed all of the receive buffers. 1727 */ 1728 break; 1729 } 1730 1731 progress++; 1732 ifp->if_ipackets++; 1733 1734 if (rxstat & GEM_RD_BAD_CRC) { 1735 ifp->if_ierrors++; 1736 aprint_error_dev(&sc->sc_dev, "receive error: CRC error\n"); 1737 GEM_INIT_RXDESC(sc, i); 1738 continue; 1739 } 1740 1741 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1742 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1743 #ifdef GEM_DEBUG 1744 if (ifp->if_flags & IFF_DEBUG) { 1745 printf(" rxsoft %p descriptor %d: ", rxs, i); 1746 printf("gd_flags: 0x%016llx\t", (long long) 1747 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1748 printf("gd_addr: 0x%016llx\n", (long long) 1749 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1750 } 1751 #endif 1752 1753 /* No errors; receive the packet. */ 1754 len = GEM_RD_BUFLEN(rxstat); 1755 1756 /* 1757 * Allocate a new mbuf cluster. If that fails, we are 1758 * out of memory, and must drop the packet and recycle 1759 * the buffer that's already attached to this descriptor. 1760 */ 1761 m = rxs->rxs_mbuf; 1762 if (gem_add_rxbuf(sc, i) != 0) { 1763 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1764 ifp->if_ierrors++; 1765 GEM_INIT_RXDESC(sc, i); 1766 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1767 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1768 continue; 1769 } 1770 m->m_data += 2; /* We're already off by two */ 1771 1772 m->m_pkthdr.rcvif = ifp; 1773 m->m_pkthdr.len = m->m_len = len; 1774 1775 #if NBPFILTER > 0 1776 /* 1777 * Pass this up to any BPF listeners, but only 1778 * pass it up the stack if it's for us. 1779 */ 1780 if (ifp->if_bpf) 1781 bpf_mtap(ifp->if_bpf, m); 1782 #endif /* NBPFILTER > 0 */ 1783 1784 #ifdef INET 1785 /* hardware checksum */ 1786 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1787 struct ether_header *eh; 1788 struct ip *ip; 1789 int32_t hlen, pktlen; 1790 1791 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1792 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN - 1793 ETHER_VLAN_ENCAP_LEN; 1794 eh = (struct ether_header *) (mtod(m, char *) + 1795 ETHER_VLAN_ENCAP_LEN); 1796 } else { 1797 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN; 1798 eh = mtod(m, struct ether_header *); 1799 } 1800 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1801 goto swcsum; 1802 ip = (struct ip *) ((char *)eh + ETHER_HDR_LEN); 1803 1804 /* IPv4 only */ 1805 if (ip->ip_v != IPVERSION) 1806 goto swcsum; 1807 1808 hlen = ip->ip_hl << 2; 1809 if (hlen < sizeof(struct ip)) 1810 goto swcsum; 1811 1812 /* 1813 * bail if too short, has random trailing garbage, 1814 * truncated, fragment, or has ethernet pad. 1815 */ 1816 if ((ntohs(ip->ip_len) < hlen) || 1817 (ntohs(ip->ip_len) != pktlen) || 1818 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 1819 goto swcsum; 1820 1821 switch (ip->ip_p) { 1822 case IPPROTO_TCP: 1823 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 1824 goto swcsum; 1825 if (pktlen < (hlen + sizeof(struct tcphdr))) 1826 goto swcsum; 1827 m->m_pkthdr.csum_flags = M_CSUM_TCPv4; 1828 break; 1829 case IPPROTO_UDP: 1830 /* FALLTHROUGH */ 1831 default: 1832 goto swcsum; 1833 } 1834 1835 /* the uncomplemented sum is expected */ 1836 m->m_pkthdr.csum_data = (~rxstat) & GEM_RD_CHECKSUM; 1837 1838 /* if the pkt had ip options, we have to deduct them */ 1839 if (hlen > sizeof(struct ip)) { 1840 uint16_t *opts; 1841 uint32_t optsum, temp; 1842 1843 optsum = 0; 1844 temp = hlen - sizeof(struct ip); 1845 opts = (uint16_t *) ((char *) ip + 1846 sizeof(struct ip)); 1847 1848 while (temp > 1) { 1849 optsum += ntohs(*opts++); 1850 temp -= 2; 1851 } 1852 while (optsum >> 16) 1853 optsum = (optsum >> 16) + 1854 (optsum & 0xffff); 1855 1856 /* Deduct ip opts sum from hwsum. */ 1857 m->m_pkthdr.csum_data += (uint16_t)~optsum; 1858 1859 while (m->m_pkthdr.csum_data >> 16) 1860 m->m_pkthdr.csum_data = 1861 (m->m_pkthdr.csum_data >> 16) + 1862 (m->m_pkthdr.csum_data & 1863 0xffff); 1864 } 1865 1866 m->m_pkthdr.csum_flags |= M_CSUM_DATA | 1867 M_CSUM_NO_PSEUDOHDR; 1868 } else 1869 swcsum: 1870 m->m_pkthdr.csum_flags = 0; 1871 #endif 1872 /* Pass it on. */ 1873 (*ifp->if_input)(ifp, m); 1874 } 1875 1876 if (progress) { 1877 /* Update the receive pointer. */ 1878 if (i == sc->sc_rxptr) { 1879 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1880 #ifdef GEM_DEBUG 1881 if (ifp->if_flags & IFF_DEBUG) 1882 printf("%s: rint: ring wrap\n", 1883 device_xname(&sc->sc_dev)); 1884 #endif 1885 } 1886 sc->sc_rxptr = i; 1887 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1888 } 1889 #ifdef GEM_COUNTERS 1890 if (progress <= 4) { 1891 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1892 } else if (progress < 32) { 1893 if (progress < 16) 1894 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1895 else 1896 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1897 1898 } else { 1899 if (progress < 64) 1900 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1901 else 1902 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1903 } 1904 #endif 1905 1906 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1907 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1908 1909 /* Read error counters ... */ 1910 ifp->if_ierrors += 1911 bus_space_read_4(t, h, GEM_MAC_RX_LEN_ERR_CNT) + 1912 bus_space_read_4(t, h, GEM_MAC_RX_ALIGN_ERR) + 1913 bus_space_read_4(t, h, GEM_MAC_RX_CRC_ERR_CNT) + 1914 bus_space_read_4(t, h, GEM_MAC_RX_CODE_VIOL); 1915 1916 /* ... then clear the hardware counters. */ 1917 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1918 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1919 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1920 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1921 1922 return (1); 1923 } 1924 1925 1926 /* 1927 * gem_add_rxbuf: 1928 * 1929 * Add a receive buffer to the indicated descriptor. 1930 */ 1931 int 1932 gem_add_rxbuf(struct gem_softc *sc, int idx) 1933 { 1934 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1935 struct mbuf *m; 1936 int error; 1937 1938 MGETHDR(m, M_DONTWAIT, MT_DATA); 1939 if (m == NULL) 1940 return (ENOBUFS); 1941 1942 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1943 MCLGET(m, M_DONTWAIT); 1944 if ((m->m_flags & M_EXT) == 0) { 1945 m_freem(m); 1946 return (ENOBUFS); 1947 } 1948 1949 #ifdef GEM_DEBUG 1950 /* bzero the packet to check DMA */ 1951 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1952 #endif 1953 1954 if (rxs->rxs_mbuf != NULL) 1955 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1956 1957 rxs->rxs_mbuf = m; 1958 1959 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1960 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1961 BUS_DMA_READ|BUS_DMA_NOWAIT); 1962 if (error) { 1963 aprint_error_dev(&sc->sc_dev, "can't load rx DMA map %d, error = %d\n", 1964 idx, error); 1965 panic("gem_add_rxbuf"); /* XXX */ 1966 } 1967 1968 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1969 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1970 1971 GEM_INIT_RXDESC(sc, idx); 1972 1973 return (0); 1974 } 1975 1976 1977 int 1978 gem_eint(struct gem_softc *sc, u_int status) 1979 { 1980 char bits[128]; 1981 u_int32_t r, v; 1982 1983 if ((status & GEM_INTR_MIF) != 0) { 1984 printf("%s: XXXlink status changed\n", device_xname(&sc->sc_dev)); 1985 return (1); 1986 } 1987 1988 if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 1989 gem_reset_rxdma(sc); 1990 return (1); 1991 } 1992 1993 if (status & GEM_INTR_BERR) { 1994 if (sc->sc_flags & GEM_PCI) 1995 r = GEM_ERROR_STATUS; 1996 else 1997 r = GEM_SBUS_ERROR_STATUS; 1998 bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 1999 v = bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 2000 aprint_error_dev(&sc->sc_dev, "bus error interrupt: 0x%02x\n", 2001 v); 2002 return (1); 2003 } 2004 2005 printf("%s: status=%s\n", device_xname(&sc->sc_dev), 2006 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits))); 2007 return (1); 2008 } 2009 2010 2011 /* 2012 * PCS interrupts. 2013 * We should receive these when the link status changes, but sometimes 2014 * we don't receive them for link up. We compensate for this in the 2015 * gem_tick() callout. 2016 */ 2017 int 2018 gem_pint(struct gem_softc *sc) 2019 { 2020 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2021 bus_space_tag_t t = sc->sc_bustag; 2022 bus_space_handle_t h = sc->sc_h1; 2023 u_int32_t v, v2; 2024 2025 /* 2026 * Clear the PCS interrupt from GEM_STATUS. The PCS register is 2027 * latched, so we have to read it twice. There is only one bit in 2028 * use, so the value is meaningless. 2029 */ 2030 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2031 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2032 2033 if ((ifp->if_flags & IFF_UP) == 0) 2034 return 1; 2035 2036 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) 2037 return 1; 2038 2039 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2040 /* If we see remote fault, our link partner is probably going away */ 2041 if ((v & GEM_MII_STATUS_REM_FLT) != 0) { 2042 gem_bitwait(sc, h, GEM_MII_STATUS, GEM_MII_STATUS_REM_FLT, 0); 2043 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2044 /* Otherwise, we may need to wait after auto-negotiation completes */ 2045 } else if ((v & (GEM_MII_STATUS_LINK_STS | GEM_MII_STATUS_ANEG_CPT)) == 2046 GEM_MII_STATUS_ANEG_CPT) { 2047 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_LINK_STS); 2048 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2049 } 2050 if ((v & GEM_MII_STATUS_LINK_STS) != 0) { 2051 if (sc->sc_flags & GEM_LINK) { 2052 return 1; 2053 } 2054 callout_stop(&sc->sc_tick_ch); 2055 v = bus_space_read_4(t, h, GEM_MII_ANAR); 2056 v2 = bus_space_read_4(t, h, GEM_MII_ANLPAR); 2057 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_1000_SX; 2058 sc->sc_mii.mii_media_status = IFM_AVALID | IFM_ACTIVE; 2059 v &= v2; 2060 if (v & GEM_MII_ANEG_FUL_DUPLX) { 2061 sc->sc_mii.mii_media_active |= IFM_FDX; 2062 #ifdef GEM_DEBUG 2063 aprint_debug_dev(&sc->sc_dev, "link up: full duplex\n"); 2064 #endif 2065 } else if (v & GEM_MII_ANEG_HLF_DUPLX) { 2066 sc->sc_mii.mii_media_active |= IFM_HDX; 2067 #ifdef GEM_DEBUG 2068 aprint_debug_dev(&sc->sc_dev, "link up: half duplex\n"); 2069 #endif 2070 } else { 2071 #ifdef GEM_DEBUG 2072 aprint_debug_dev(&sc->sc_dev, "duplex mismatch\n"); 2073 #endif 2074 } 2075 gem_statuschange(sc); 2076 } else { 2077 if ((sc->sc_flags & GEM_LINK) == 0) { 2078 return 1; 2079 } 2080 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 2081 sc->sc_mii.mii_media_status = IFM_AVALID; 2082 #ifdef GEM_DEBUG 2083 aprint_debug_dev(&sc->sc_dev, "link down\n"); 2084 #endif 2085 gem_statuschange(sc); 2086 2087 /* Start the 10 second timer */ 2088 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 2089 } 2090 return 1; 2091 } 2092 2093 2094 2095 int 2096 gem_intr(v) 2097 void *v; 2098 { 2099 struct gem_softc *sc = (struct gem_softc *)v; 2100 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2101 bus_space_tag_t t = sc->sc_bustag; 2102 bus_space_handle_t h = sc->sc_h1; 2103 u_int32_t status; 2104 int r = 0; 2105 #ifdef GEM_DEBUG 2106 char bits[128]; 2107 #endif 2108 2109 /* XXX We should probably mask out interrupts until we're done */ 2110 2111 sc->sc_ev_intr.ev_count++; 2112 2113 status = bus_space_read_4(t, h, GEM_STATUS); 2114 DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n", 2115 device_xname(&sc->sc_dev), (status >> 19), 2116 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits)))); 2117 2118 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 2119 r |= gem_eint(sc, status); 2120 2121 /* We don't bother with GEM_INTR_TX_DONE */ 2122 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 2123 GEM_COUNTER_INCR(sc, sc_ev_txint); 2124 r |= gem_tint(sc); 2125 } 2126 2127 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 2128 GEM_COUNTER_INCR(sc, sc_ev_rxint); 2129 r |= gem_rint(sc); 2130 } 2131 2132 /* We should eventually do more than just print out error stats. */ 2133 if (status & GEM_INTR_TX_MAC) { 2134 int txstat = bus_space_read_4(t, h, GEM_MAC_TX_STATUS); 2135 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 2136 printf("%s: MAC tx fault, status %x\n", 2137 device_xname(&sc->sc_dev), txstat); 2138 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 2139 gem_init(ifp); 2140 } 2141 if (status & GEM_INTR_RX_MAC) { 2142 int rxstat = bus_space_read_4(t, h, GEM_MAC_RX_STATUS); 2143 /* 2144 * At least with GEM_SUN_GEM and some GEM_SUN_ERI 2145 * revisions GEM_MAC_RX_OVERFLOW happen often due to a 2146 * silicon bug so handle them silently. Moreover, it's 2147 * likely that the receiver has hung so we reset it. 2148 */ 2149 if (rxstat & GEM_MAC_RX_OVERFLOW) { 2150 ifp->if_ierrors++; 2151 gem_reset_rxdma(sc); 2152 } else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 2153 printf("%s: MAC rx fault, status 0x%02x\n", 2154 device_xname(&sc->sc_dev), rxstat); 2155 } 2156 if (status & GEM_INTR_PCS) { 2157 r |= gem_pint(sc); 2158 } 2159 2160 /* Do we need to do anything with these? 2161 if ((status & GEM_MAC_CONTROL_STATUS) != 0) { 2162 status2 = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_STATUS); 2163 if ((status2 & GEM_MAC_PAUSED) != 0) 2164 aprintf_debug_dev(&sc->sc_dev, "PAUSE received (%d slots)\n", 2165 GEM_MAC_PAUSE_TIME(status2)); 2166 if ((status2 & GEM_MAC_PAUSE) != 0) 2167 aprintf_debug_dev(&sc->sc_dev, "transited to PAUSE state\n"); 2168 if ((status2 & GEM_MAC_RESUME) != 0) 2169 aprintf_debug_dev(&sc->sc_dev, "transited to non-PAUSE state\n"); 2170 } 2171 if ((status & GEM_INTR_MIF) != 0) 2172 aprintf_debug_dev(&sc->sc_dev, "MIF interrupt\n"); 2173 */ 2174 #if NRND > 0 2175 rnd_add_uint32(&sc->rnd_source, status); 2176 #endif 2177 return (r); 2178 } 2179 2180 2181 void 2182 gem_watchdog(ifp) 2183 struct ifnet *ifp; 2184 { 2185 struct gem_softc *sc = ifp->if_softc; 2186 2187 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 2188 "GEM_MAC_RX_CONFIG %x\n", 2189 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_CONFIG), 2190 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_STATUS), 2191 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_CONFIG))); 2192 2193 log(LOG_ERR, "%s: device timeout\n", device_xname(&sc->sc_dev)); 2194 ++ifp->if_oerrors; 2195 2196 /* Try to get more packets going. */ 2197 gem_start(ifp); 2198 } 2199 2200 /* 2201 * Initialize the MII Management Interface 2202 */ 2203 void 2204 gem_mifinit(sc) 2205 struct gem_softc *sc; 2206 { 2207 bus_space_tag_t t = sc->sc_bustag; 2208 bus_space_handle_t mif = sc->sc_h1; 2209 2210 /* Configure the MIF in frame mode */ 2211 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 2212 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 2213 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 2214 } 2215 2216 /* 2217 * MII interface 2218 * 2219 * The GEM MII interface supports at least three different operating modes: 2220 * 2221 * Bitbang mode is implemented using data, clock and output enable registers. 2222 * 2223 * Frame mode is implemented by loading a complete frame into the frame 2224 * register and polling the valid bit for completion. 2225 * 2226 * Polling mode uses the frame register but completion is indicated by 2227 * an interrupt. 2228 * 2229 */ 2230 static int 2231 gem_mii_readreg(self, phy, reg) 2232 struct device *self; 2233 int phy, reg; 2234 { 2235 struct gem_softc *sc = (void *)self; 2236 bus_space_tag_t t = sc->sc_bustag; 2237 bus_space_handle_t mif = sc->sc_h1; 2238 int n; 2239 u_int32_t v; 2240 2241 #ifdef GEM_DEBUG1 2242 if (sc->sc_debug) 2243 printf("gem_mii_readreg: PHY %d reg %d\n", phy, reg); 2244 #endif 2245 2246 /* Construct the frame command */ 2247 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 2248 GEM_MIF_FRAME_READ; 2249 2250 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2251 for (n = 0; n < 100; n++) { 2252 DELAY(1); 2253 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2254 if (v & GEM_MIF_FRAME_TA0) 2255 return (v & GEM_MIF_FRAME_DATA); 2256 } 2257 2258 printf("%s: mii_read timeout\n", device_xname(&sc->sc_dev)); 2259 return (0); 2260 } 2261 2262 static void 2263 gem_mii_writereg(self, phy, reg, val) 2264 struct device *self; 2265 int phy, reg, val; 2266 { 2267 struct gem_softc *sc = (void *)self; 2268 bus_space_tag_t t = sc->sc_bustag; 2269 bus_space_handle_t mif = sc->sc_h1; 2270 int n; 2271 u_int32_t v; 2272 2273 #ifdef GEM_DEBUG1 2274 if (sc->sc_debug) 2275 printf("gem_mii_writereg: PHY %d reg %d val %x\n", 2276 phy, reg, val); 2277 #endif 2278 2279 /* Construct the frame command */ 2280 v = GEM_MIF_FRAME_WRITE | 2281 (phy << GEM_MIF_PHY_SHIFT) | 2282 (reg << GEM_MIF_REG_SHIFT) | 2283 (val & GEM_MIF_FRAME_DATA); 2284 2285 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2286 for (n = 0; n < 100; n++) { 2287 DELAY(1); 2288 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2289 if (v & GEM_MIF_FRAME_TA0) 2290 return; 2291 } 2292 2293 printf("%s: mii_write timeout\n", device_xname(&sc->sc_dev)); 2294 } 2295 2296 static void 2297 gem_mii_statchg(dev) 2298 struct device *dev; 2299 { 2300 struct gem_softc *sc = (void *)dev; 2301 #ifdef GEM_DEBUG 2302 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 2303 #endif 2304 2305 #ifdef GEM_DEBUG 2306 if (sc->sc_debug) 2307 printf("gem_mii_statchg: status change: phy = %d\n", 2308 sc->sc_phys[instance]); 2309 #endif 2310 gem_statuschange(sc); 2311 } 2312 2313 /* 2314 * Common status change for gem_mii_statchg() and gem_pint() 2315 */ 2316 void 2317 gem_statuschange(struct gem_softc* sc) 2318 { 2319 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2320 bus_space_tag_t t = sc->sc_bustag; 2321 bus_space_handle_t mac = sc->sc_h1; 2322 int gigabit; 2323 u_int32_t rxcfg, txcfg, v; 2324 2325 if ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0 && 2326 IFM_SUBTYPE(sc->sc_mii.mii_media_active) != IFM_NONE) 2327 sc->sc_flags |= GEM_LINK; 2328 else 2329 sc->sc_flags &= ~GEM_LINK; 2330 2331 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2332 gigabit = 1; 2333 else 2334 gigabit = 0; 2335 2336 /* 2337 * The configuration done here corresponds to the steps F) and 2338 * G) and as far as enabling of RX and TX MAC goes also step H) 2339 * of the initialization sequence outlined in section 3.2.1 of 2340 * the GEM Gigabit Ethernet ASIC Specification. 2341 */ 2342 2343 rxcfg = bus_space_read_4(t, mac, GEM_MAC_RX_CONFIG); 2344 rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE); 2345 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT; 2346 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2347 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS; 2348 else if (gigabit) { 2349 rxcfg |= GEM_MAC_RX_CARR_EXTEND; 2350 txcfg |= GEM_MAC_RX_CARR_EXTEND; 2351 } 2352 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 2353 bus_space_barrier(t, mac, GEM_MAC_TX_CONFIG, 4, 2354 BUS_SPACE_BARRIER_WRITE); 2355 if (!gem_bitwait(sc, mac, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 2356 aprint_normal_dev(&sc->sc_dev, "cannot disable TX MAC\n"); 2357 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, txcfg); 2358 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 0); 2359 bus_space_barrier(t, mac, GEM_MAC_RX_CONFIG, 4, 2360 BUS_SPACE_BARRIER_WRITE); 2361 if (!gem_bitwait(sc, mac, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 2362 aprint_normal_dev(&sc->sc_dev, "cannot disable RX MAC\n"); 2363 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, rxcfg); 2364 2365 v = bus_space_read_4(t, mac, GEM_MAC_CONTROL_CONFIG) & 2366 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 2367 bus_space_write_4(t, mac, GEM_MAC_CONTROL_CONFIG, v); 2368 2369 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) == 0 && 2370 gigabit != 0) 2371 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2372 GEM_MAC_SLOT_TIME_CARR_EXTEND); 2373 else 2374 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2375 GEM_MAC_SLOT_TIME_NORMAL); 2376 2377 /* XIF Configuration */ 2378 if (sc->sc_flags & GEM_LINK) 2379 v = GEM_MAC_XIF_LINK_LED; 2380 else 2381 v = 0; 2382 v |= GEM_MAC_XIF_TX_MII_ENA; 2383 2384 /* If an external transceiver is connected, enable its MII drivers */ 2385 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 2386 if ((sc->sc_flags &(GEM_SERDES | GEM_SERIAL)) == 0) { 2387 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 2388 /* External MII needs echo disable if half duplex. */ 2389 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & 2390 IFM_FDX) != 0) 2391 /* turn on full duplex LED */ 2392 v |= GEM_MAC_XIF_FDPLX_LED; 2393 else 2394 /* half duplex -- disable echo */ 2395 v |= GEM_MAC_XIF_ECHO_DISABL; 2396 if (gigabit) 2397 v |= GEM_MAC_XIF_GMII_MODE; 2398 else 2399 v &= ~GEM_MAC_XIF_GMII_MODE; 2400 } else 2401 /* Internal MII needs buf enable */ 2402 v |= GEM_MAC_XIF_MII_BUF_ENA; 2403 } else { 2404 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2405 v |= GEM_MAC_XIF_FDPLX_LED; 2406 v |= GEM_MAC_XIF_GMII_MODE; 2407 } 2408 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 2409 2410 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2411 (sc->sc_flags & GEM_LINK) != 0) { 2412 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 2413 txcfg | GEM_MAC_TX_ENABLE); 2414 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 2415 rxcfg | GEM_MAC_RX_ENABLE); 2416 } 2417 } 2418 2419 int 2420 gem_ser_mediachange(struct ifnet *ifp) 2421 { 2422 struct gem_softc *sc = ifp->if_softc; 2423 u_int s, t; 2424 2425 if (IFM_TYPE(sc->sc_mii.mii_media.ifm_media) != IFM_ETHER) 2426 return EINVAL; 2427 2428 s = IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media); 2429 if (s == IFM_AUTO) { 2430 if (sc->sc_mii_media != s) { 2431 #ifdef GEM_DEBUG 2432 aprint_debug_dev(&sc->sc_dev, "setting media to auto\n"); 2433 #endif 2434 sc->sc_mii_media = s; 2435 if (ifp->if_flags & IFF_UP) { 2436 gem_pcs_stop(sc, 0); 2437 gem_pcs_start(sc); 2438 } 2439 } 2440 return 0; 2441 } 2442 if (s == IFM_1000_SX) { 2443 t = IFM_OPTIONS(sc->sc_mii.mii_media.ifm_media); 2444 if (t == IFM_FDX || t == IFM_HDX) { 2445 if (sc->sc_mii_media != t) { 2446 sc->sc_mii_media = t; 2447 #ifdef GEM_DEBUG 2448 aprint_debug_dev(&sc->sc_dev, 2449 "setting media to 1000baseSX-%s\n", 2450 t == IFM_FDX ? "FDX" : "HDX"); 2451 #endif 2452 if (ifp->if_flags & IFF_UP) { 2453 gem_pcs_stop(sc, 0); 2454 gem_pcs_start(sc); 2455 } 2456 } 2457 return 0; 2458 } 2459 } 2460 return EINVAL; 2461 } 2462 2463 void 2464 gem_ser_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2465 { 2466 struct gem_softc *sc = ifp->if_softc; 2467 2468 if ((ifp->if_flags & IFF_UP) == 0) 2469 return; 2470 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2471 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2472 } 2473 2474 /* 2475 * Process an ioctl request. 2476 */ 2477 int 2478 gem_ioctl(ifp, cmd, data) 2479 struct ifnet *ifp; 2480 u_long cmd; 2481 void *data; 2482 { 2483 struct gem_softc *sc = ifp->if_softc; 2484 int s, error = 0; 2485 2486 s = splnet(); 2487 2488 switch (cmd) { 2489 case SIOCSIFFLAGS: 2490 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 2491 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 2492 == (IFF_UP|IFF_RUNNING)) 2493 && ((ifp->if_flags & (~RESETIGN)) 2494 == (sc->sc_if_flags & (~RESETIGN)))) { 2495 gem_setladrf(sc); 2496 break; 2497 } 2498 #undef RESETIGN 2499 /*FALLTHROUGH*/ 2500 default: 2501 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 2502 break; 2503 2504 error = 0; 2505 2506 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2507 ; 2508 else if (ifp->if_flags & IFF_RUNNING) { 2509 /* 2510 * Multicast list has changed; set the hardware filter 2511 * accordingly. 2512 */ 2513 gem_setladrf(sc); 2514 } 2515 break; 2516 } 2517 2518 /* Try to get things going again */ 2519 if (ifp->if_flags & IFF_UP) 2520 gem_start(ifp); 2521 splx(s); 2522 return (error); 2523 } 2524 2525 2526 void 2527 gem_shutdown(arg) 2528 void *arg; 2529 { 2530 struct gem_softc *sc = (struct gem_softc *)arg; 2531 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2532 2533 gem_stop(ifp, 1); 2534 } 2535 2536 /* 2537 * Set up the logical address filter. 2538 */ 2539 void 2540 gem_setladrf(sc) 2541 struct gem_softc *sc; 2542 { 2543 struct ethercom *ec = &sc->sc_ethercom; 2544 struct ifnet *ifp = &ec->ec_if; 2545 struct ether_multi *enm; 2546 struct ether_multistep step; 2547 bus_space_tag_t t = sc->sc_bustag; 2548 bus_space_handle_t h = sc->sc_h1; 2549 u_int32_t crc; 2550 u_int32_t hash[16]; 2551 u_int32_t v; 2552 int i; 2553 2554 /* Get current RX configuration */ 2555 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 2556 2557 /* 2558 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2559 * and hash filter. Depending on the case, the right bit will be 2560 * enabled. 2561 */ 2562 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 2563 GEM_MAC_RX_PROMISC_GRP); 2564 2565 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2566 /* Turn on promiscuous mode */ 2567 v |= GEM_MAC_RX_PROMISCUOUS; 2568 ifp->if_flags |= IFF_ALLMULTI; 2569 goto chipit; 2570 } 2571 2572 /* 2573 * Set up multicast address filter by passing all multicast addresses 2574 * through a crc generator, and then using the high order 8 bits as an 2575 * index into the 256 bit logical address filter. The high order 4 2576 * bits selects the word, while the other 4 bits select the bit within 2577 * the word (where bit 0 is the MSB). 2578 */ 2579 2580 /* Clear hash table */ 2581 memset(hash, 0, sizeof(hash)); 2582 2583 ETHER_FIRST_MULTI(step, ec, enm); 2584 while (enm != NULL) { 2585 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2586 /* 2587 * We must listen to a range of multicast addresses. 2588 * For now, just accept all multicasts, rather than 2589 * trying to set only those filter bits needed to match 2590 * the range. (At this time, the only use of address 2591 * ranges is for IP multicast routing, for which the 2592 * range is big enough to require all bits set.) 2593 * XXX should use the address filters for this 2594 */ 2595 ifp->if_flags |= IFF_ALLMULTI; 2596 v |= GEM_MAC_RX_PROMISC_GRP; 2597 goto chipit; 2598 } 2599 2600 /* Get the LE CRC32 of the address */ 2601 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 2602 2603 /* Just want the 8 most significant bits. */ 2604 crc >>= 24; 2605 2606 /* Set the corresponding bit in the filter. */ 2607 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2608 2609 ETHER_NEXT_MULTI(step, enm); 2610 } 2611 2612 v |= GEM_MAC_RX_HASH_FILTER; 2613 ifp->if_flags &= ~IFF_ALLMULTI; 2614 2615 /* Now load the hash table into the chip (if we are using it) */ 2616 for (i = 0; i < 16; i++) { 2617 bus_space_write_4(t, h, 2618 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 2619 hash[i]); 2620 } 2621 2622 chipit: 2623 sc->sc_if_flags = ifp->if_flags; 2624 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 2625 } 2626 2627 #if notyet 2628 2629 /* 2630 * gem_power: 2631 * 2632 * Power management (suspend/resume) hook. 2633 */ 2634 void 2635 gem_power(why, arg) 2636 int why; 2637 void *arg; 2638 { 2639 struct gem_softc *sc = arg; 2640 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2641 int s; 2642 2643 s = splnet(); 2644 switch (why) { 2645 case PWR_SUSPEND: 2646 case PWR_STANDBY: 2647 gem_stop(ifp, 1); 2648 if (sc->sc_power != NULL) 2649 (*sc->sc_power)(sc, why); 2650 break; 2651 case PWR_RESUME: 2652 if (ifp->if_flags & IFF_UP) { 2653 if (sc->sc_power != NULL) 2654 (*sc->sc_power)(sc, why); 2655 gem_init(ifp); 2656 } 2657 break; 2658 case PWR_SOFTSUSPEND: 2659 case PWR_SOFTSTANDBY: 2660 case PWR_SOFTRESUME: 2661 break; 2662 } 2663 splx(s); 2664 } 2665 #endif
Cache object: 997f3b8810e3c77cfaf8f3285e18aa12
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]