gemvar.h

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    1 /*      $OpenBSD: gemvar.h,v 1.31 2015/11/28 09:42:10 jmatthew Exp $    */
    2 /*      $NetBSD: gemvar.h,v 1.1 2001/09/16 00:11:43 eeh Exp $ */
    3 
    4 /*
    5  *
    6  * Copyright (C) 2001 Eduardo Horvath.
    7  * All rights reserved.
    8  *
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR  ``AS IS'' AND
   20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR  BE LIABLE
   23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   29  * SUCH DAMAGE.
   30  *
   31  */
   32 
   33 #ifndef _IF_GEMVAR_H
   34 #define _IF_GEMVAR_H
   35 
   36 #include <sys/queue.h>
   37 #include <sys/timeout.h>
   38 
   39 /*
   40  * Misc. definitions for the Sun ``Gem'' Ethernet controller family driver.
   41  */
   42 
   43 /*
   44  * Transmit descriptor list size.  This is arbitrary, but allocate
   45  * enough descriptors for 64 pending transmissions and 16 segments
   46  * per packet.
   47  */
   48 #define GEM_NTXSEGS             16
   49 
   50 #define GEM_TXQUEUELEN          64
   51 #define GEM_NTXDESC             (GEM_TXQUEUELEN * GEM_NTXSEGS)
   52 #define GEM_NTXDESC_MASK        (GEM_NTXDESC - 1)
   53 #define GEM_NEXTTX(x)           ((x + 1) & GEM_NTXDESC_MASK)
   54 
   55 struct gem_sxd {
   56         struct mbuf *sd_mbuf;
   57         bus_dmamap_t sd_map;
   58 };
   59 
   60 /*
   61  * Receive descriptor list size.  We have one Rx buffer per incoming
   62  * packet, so this logic is a little simpler.
   63  */
   64 #define GEM_NRXDESC             128
   65 #define GEM_NRXDESC_MASK        (GEM_NRXDESC - 1)
   66 #define GEM_NEXTRX(x)           ((x + 1) & GEM_NRXDESC_MASK)
   67 
   68 /*
   69  * Control structures are DMA'd to the GEM chip.  We allocate them in
   70  * a single clump that maps to a single DMA segment to make several things
   71  * easier.
   72  */
   73 struct gem_control_data {
   74         /*
   75          * The transmit descriptors.
   76          */
   77         struct gem_desc gcd_txdescs[GEM_NTXDESC];
   78 
   79         /*
   80          * The receive descriptors.
   81          */
   82         struct gem_desc gcd_rxdescs[GEM_NRXDESC];
   83 };
   84 
   85 #define GEM_CDOFF(x)            offsetof(struct gem_control_data, x)
   86 #define GEM_CDTXOFF(x)          GEM_CDOFF(gcd_txdescs[(x)])
   87 #define GEM_CDRXOFF(x)          GEM_CDOFF(gcd_rxdescs[(x)])
   88 
   89 /*
   90  * Software state for receive jobs.
   91  */
   92 struct gem_rxsoft {
   93         struct mbuf *rxs_mbuf;          /* head of our mbuf chain */
   94         bus_dmamap_t rxs_dmamap;        /* our DMA map */
   95 };
   96 
   97 
   98 /*
   99  * Table which describes the transmit threshold mode.  We generally
  100  * start at index 0.  Whenever we get a transmit underrun, we increment
  101  * our index, falling back if we encounter the NULL terminator.
  102  */
  103 struct gem_txthresh_tab {
  104         u_int32_t txth_opmode;          /* OPMODE bits */
  105         const char *txth_name;          /* name of mode */
  106 };
  107 
  108 /*
  109  * Some misc. statics, useful for debugging.
  110  */
  111 struct gem_stats {
  112         u_long          ts_tx_uf;       /* transmit underflow errors */
  113         u_long          ts_tx_to;       /* transmit jabber timeouts */
  114         u_long          ts_tx_ec;       /* excessive collision count */
  115         u_long          ts_tx_lc;       /* late collision count */
  116 };
  117 
  118 /*
  119  * Software state per device.
  120  */
  121 struct gem_softc {
  122         struct device   sc_dev;         /* generic device information */
  123         struct arpcom   sc_arpcom;      /* ethernet common data */
  124         struct mii_data sc_mii;         /* MII media control */
  125 #define sc_media        sc_mii.mii_media/* shorthand */
  126         struct timeout  sc_tick_ch;     /* tick callout */
  127         void            *sc_ih;         /* interrupt handler */
  128 
  129         /* The following bus handles are to be provided by the bus front-end */
  130         bus_space_tag_t sc_bustag;      /* bus tag */
  131         bus_dma_tag_t   sc_dmatag;      /* bus dma tag */
  132         bus_dmamap_t    sc_dmamap;      /* bus dma handle */
  133         bus_space_handle_t sc_h1;       /* bus space handle for bank 1 regs */
  134         bus_space_handle_t sc_h2;       /* bus space handle for bank 2 regs */
  135 #if 0
  136         /* The following may be needed for SBus */
  137         bus_space_handle_t sc_seb;      /* HME Global registers */
  138         bus_space_handle_t sc_erx;      /* HME ERX registers */
  139         bus_space_handle_t sc_etx;      /* HME ETX registers */
  140         bus_space_handle_t sc_mac;      /* HME MAC registers */
  141         bus_space_handle_t sc_mif;      /* HME MIF registers */
  142 #endif
  143         int             sc_burst;       /* DVMA burst size in effect */
  144 
  145         int             sc_mif_config;  /* Selected MII reg setting */
  146 
  147         int             sc_pci;         /* XXXXX -- PCI buses are LE. */
  148         u_int           sc_variant;     /* which GEM are we dealing with? */
  149 #define GEM_UNKNOWN                     0       /* don't know */
  150 #define GEM_SUN_GEM                     1       /* Sun GEM */
  151 #define GEM_SUN_ERI                     2       /* Sun ERI */
  152 #define GEM_APPLE_GMAC                  3       /* Apple GMAC */
  153 #define GEM_APPLE_K2_GMAC               4       /* Apple K2 GMAC */
  154 
  155 #define GEM_IS_APPLE(sc)                                                \
  156         ((sc)->sc_variant == GEM_APPLE_GMAC ||                          \
  157          (sc)->sc_variant == GEM_APPLE_K2_GMAC)
  158 
  159         u_int           sc_flags;       /* */
  160 #define GEM_GIGABIT             0x0001  /* has a gigabit PHY */
  161 
  162 
  163         struct gem_stats sc_stats;      /* debugging stats */
  164 
  165         /*
  166          * Ring buffer DMA stuff.
  167          */
  168         bus_dma_segment_t sc_cdseg;     /* control data memory */
  169         int             sc_cdnseg;      /* number of segments */
  170         bus_dmamap_t sc_cddmamap;       /* control data DMA map */
  171 #define sc_cddma        sc_cddmamap->dm_segs[0].ds_addr
  172 
  173         /*
  174          * Software state for transmit and receive descriptors.
  175          */
  176         struct gem_sxd sc_txd[GEM_NTXDESC];
  177         u_int32_t sc_tx_cnt, sc_tx_prod, sc_tx_cons;
  178 
  179         struct gem_rxsoft sc_rxsoft[GEM_NRXDESC];
  180         struct if_rxring sc_rx_ring;
  181         u_int32_t sc_rx_prod, sc_rx_cons;
  182 
  183         /*
  184          * Control data structures.
  185          */
  186         struct gem_control_data *sc_control_data;
  187 #define sc_txdescs      sc_control_data->gcd_txdescs
  188 #define sc_rxdescs      sc_control_data->gcd_rxdescs
  189 
  190         int                     sc_txfree;              /* number of free Tx descriptors */
  191         int                     sc_txnext;              /* next ready Tx descriptor */
  192 
  193         u_int32_t               sc_tdctl_ch;            /* conditional desc chaining */
  194         u_int32_t               sc_tdctl_er;            /* conditional desc end-of-ring */
  195 
  196         u_int32_t               sc_setup_fsls;  /* FS|LS on setup descriptor */
  197 
  198         int                     sc_rxfifosize;
  199 
  200         u_int32_t               sc_rx_fifo_wr_ptr;
  201         u_int32_t               sc_rx_fifo_rd_ptr;
  202         struct timeout          sc_rx_watchdog;
  203 
  204         /* ========== */
  205         int                     sc_inited;
  206         int                     sc_debug;
  207 
  208         /* Special hardware hooks */
  209         void    (*sc_hwreset)(struct gem_softc *);
  210         void    (*sc_hwinit)(struct gem_softc *);
  211 };
  212 
  213 #define GEM_DMA_READ(_sc, _a) \
  214         (((_sc)->sc_pci) ? lemtoh64(_a) : bemtoh64(_a))
  215 #define GEM_DMA_WRITE(_sc, _a, _v) \
  216         (((_sc)->sc_pci) ? htolem64((_a), (_v)) : htobem64((_a), (_v)))
  217 
  218 /*
  219  * This macro determines if a change to media-related OPMODE bits requires
  220  * a chip reset.
  221  */
  222 #define GEM_MEDIA_NEEDSRESET(sc, newbits)                               \
  223         (((sc)->sc_opmode & OPMODE_MEDIA_BITS) !=                       \
  224          ((newbits) & OPMODE_MEDIA_BITS))
  225 
  226 #define GEM_CDTXADDR(sc, x)     ((sc)->sc_cddma + GEM_CDTXOFF((x)))
  227 #define GEM_CDRXADDR(sc, x)     ((sc)->sc_cddma + GEM_CDRXOFF((x)))
  228 
  229 #define GEM_CDSPADDR(sc)        ((sc)->sc_cddma + GEM_CDSPOFF)
  230 
  231 #define GEM_CDTXSYNC(sc, x, n, ops)                                     \
  232 do {                                                                    \
  233         int __x, __n;                                                   \
  234                                                                         \
  235         __x = (x);                                                      \
  236         __n = (n);                                                      \
  237                                                                         \
  238         /* If it will wrap around, sync to the end of the ring. */      \
  239         if ((__x + __n) > GEM_NTXDESC) {                                \
  240                 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap,     \
  241                     GEM_CDTXOFF(__x), sizeof(struct gem_desc) *         \
  242                     (GEM_NTXDESC - __x), (ops));                        \
  243                 __n -= (GEM_NTXDESC - __x);                             \
  244                 __x = 0;                                                \
  245         }                                                               \
  246                                                                         \
  247         /* Now sync whatever is left. */                                \
  248         bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap,             \
  249             GEM_CDTXOFF(__x), sizeof(struct gem_desc) * __n, (ops));    \
  250 } while (0)
  251 
  252 #define GEM_CDRXSYNC(sc, x, ops)                                        \
  253         bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap,             \
  254             GEM_CDRXOFF((x)), sizeof(struct gem_desc), (ops))
  255 
  256 #define GEM_CDSPSYNC(sc, ops)                                           \
  257         bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap,             \
  258             GEM_CDSPOFF, GEM_SETUP_PACKET_LEN, (ops))
  259 
  260 #define GEM_INIT_RXDESC(sc, x)                                          \
  261 do {                                                                    \
  262         struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)];                 \
  263         struct gem_desc *__rxd = &sc->sc_rxdescs[(x)];                  \
  264         struct mbuf *__m = __rxs->rxs_mbuf;                             \
  265                                                                         \
  266         GEM_DMA_WRITE((sc), &__rxd->gd_addr,                            \
  267             __rxs->rxs_dmamap->dm_segs[0].ds_addr);                     \
  268         GEM_DMA_WRITE((sc), &__rxd->gd_flags,                           \
  269                 (((__m->m_ext.ext_size)<<GEM_RD_BUFSHIFT)               \
  270             & GEM_RD_BUFSIZE) | GEM_RD_OWN);                            \
  271         GEM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
  272 } while (0)
  273 
  274 #ifdef _KERNEL
  275 void    gem_attach(struct gem_softc *, const u_int8_t *);
  276 int     gem_activate(struct device *, int);
  277 int     gem_detach(struct gem_softc *);
  278 int     gem_intr(void *);
  279 int     gem_read_srom(struct gem_softc *);
  280 int     gem_srom_crcok(const u_int8_t *);
  281 int     gem_isv_srom(const u_int8_t *);
  282 int     gem_isv_srom_enaddr(struct gem_softc *, u_int8_t *);
  283 int     gem_parse_old_srom(struct gem_softc *, u_int8_t *);
  284 
  285 int     gem_mediachange(struct ifnet *);
  286 void    gem_mediastatus(struct ifnet *, struct ifmediareq *);
  287 
  288 void    gem_config(struct gem_softc *);
  289 void    gem_unconfig(struct gem_softc *);
  290 void    gem_reset(struct gem_softc *);
  291 int     gem_intr(void *);
  292 #endif /* _KERNEL */
  293 
  294 #endif
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FreeBSD/Linux Kernel Cross Reference sys/dev/ic/gemvar.h

FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/gemvar.h
