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sys/dev/ic/hd64570.c
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1 /* $NetBSD: hd64570.c,v 1.34 2006/11/16 01:32:51 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1999 Christian E. Hopps 5 * Copyright (c) 1998 Vixie Enterprises 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Vixie Enterprises nor the names 18 * of its contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY VIXIE ENTERPRISES AND 22 * CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 23 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL VIXIE ENTERPRISES OR 26 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * This software has been written for Vixie Enterprises by Michael Graff 36 * <explorer@flame.org>. To learn more about Vixie Enterprises, see 37 * ``http://www.vix.com''. 38 */ 39 40 /* 41 * TODO: 42 * 43 * o teach the receive logic about errors, and about long frames that 44 * span more than one input buffer. (Right now, receive/transmit is 45 * limited to one descriptor's buffer space, which is MTU + 4 bytes. 46 * This is currently 1504, which is large enough to hold the HDLC 47 * header and the packet itself. Packets which are too long are 48 * silently dropped on transmit and silently dropped on receive. 49 * o write code to handle the msci interrupts, needed only for CD 50 * and CTS changes. 51 * o consider switching back to a "queue tx with DMA active" model which 52 * should help sustain outgoing traffic 53 * o through clever use of bus_dma*() functions, it should be possible 54 * to map the mbuf's data area directly into a descriptor transmit 55 * buffer, removing the need to allocate extra memory. If, however, 56 * we run out of descriptors for this, we will need to then allocate 57 * one large mbuf, copy the fragmented chain into it, and put it onto 58 * a single descriptor. 59 * o use bus_dmamap_sync() with the right offset and lengths, rather 60 * than cheating and always sync'ing the whole region. 61 * 62 * o perhaps allow rx and tx to be in more than one page 63 * if not using DMA. currently the assumption is that 64 * rx uses a page and tx uses a page. 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: hd64570.c,v 1.34 2006/11/16 01:32:51 christos Exp $"); 69 70 #include "bpfilter.h" 71 #include "opt_inet.h" 72 #include "opt_iso.h" 73 74 #include <sys/param.h> 75 #include <sys/systm.h> 76 #include <sys/device.h> 77 #include <sys/mbuf.h> 78 #include <sys/socket.h> 79 #include <sys/sockio.h> 80 #include <sys/kernel.h> 81 82 #include <net/if.h> 83 #include <net/if_types.h> 84 #include <net/netisr.h> 85 86 #if defined(INET) || defined(INET6) 87 #include <netinet/in.h> 88 #include <netinet/in_systm.h> 89 #include <netinet/in_var.h> 90 #include <netinet/ip.h> 91 #ifdef INET6 92 #include <netinet6/in6_var.h> 93 #endif 94 #endif 95 96 #ifdef ISO 97 #include <net/if_llc.h> 98 #include <netiso/iso.h> 99 #include <netiso/iso_var.h> 100 #endif 101 102 #if NBPFILTER > 0 103 #include <net/bpf.h> 104 #endif 105 106 #include <machine/cpu.h> 107 #include <machine/bus.h> 108 #include <machine/intr.h> 109 110 #include <dev/pci/pcivar.h> 111 #include <dev/pci/pcireg.h> 112 #include <dev/pci/pcidevs.h> 113 114 #include <dev/ic/hd64570reg.h> 115 #include <dev/ic/hd64570var.h> 116 117 #define SCA_DEBUG_RX 0x0001 118 #define SCA_DEBUG_TX 0x0002 119 #define SCA_DEBUG_CISCO 0x0004 120 #define SCA_DEBUG_DMA 0x0008 121 #define SCA_DEBUG_RXPKT 0x0010 122 #define SCA_DEBUG_TXPKT 0x0020 123 #define SCA_DEBUG_INTR 0x0040 124 #define SCA_DEBUG_CLOCK 0x0080 125 126 #if 0 127 #define SCA_DEBUG_LEVEL ( 0xFFFF ) 128 #else 129 #define SCA_DEBUG_LEVEL 0 130 #endif 131 132 u_int32_t sca_debug = SCA_DEBUG_LEVEL; 133 134 #if SCA_DEBUG_LEVEL > 0 135 #define SCA_DPRINTF(l, x) do { \ 136 if ((l) & sca_debug) \ 137 printf x;\ 138 } while (0) 139 #else 140 #define SCA_DPRINTF(l, x) 141 #endif 142 143 #if 0 144 #define SCA_USE_FASTQ /* use a split queue, one for fast traffic */ 145 #endif 146 147 static inline void msci_write_1(sca_port_t *, u_int, u_int8_t); 148 static inline u_int8_t msci_read_1(sca_port_t *, u_int); 149 150 static inline void dmac_write_1(sca_port_t *, u_int, u_int8_t); 151 static inline void dmac_write_2(sca_port_t *, u_int, u_int16_t); 152 static inline u_int8_t dmac_read_1(sca_port_t *, u_int); 153 static inline u_int16_t dmac_read_2(sca_port_t *, u_int); 154 155 static void sca_msci_init(struct sca_softc *, sca_port_t *); 156 static void sca_dmac_init(struct sca_softc *, sca_port_t *); 157 static void sca_dmac_rxinit(sca_port_t *); 158 159 static int sca_dmac_intr(sca_port_t *, u_int8_t); 160 static int sca_msci_intr(sca_port_t *, u_int8_t); 161 162 static void sca_get_packets(sca_port_t *); 163 static int sca_frame_avail(sca_port_t *); 164 static void sca_frame_process(sca_port_t *); 165 static void sca_frame_read_done(sca_port_t *); 166 167 static void sca_port_starttx(sca_port_t *); 168 169 static void sca_port_up(sca_port_t *); 170 static void sca_port_down(sca_port_t *); 171 172 static int sca_output(struct ifnet *, struct mbuf *, struct sockaddr *, 173 struct rtentry *); 174 static int sca_ioctl(struct ifnet *, u_long, caddr_t); 175 static void sca_start(struct ifnet *); 176 static void sca_watchdog(struct ifnet *); 177 178 static struct mbuf *sca_mbuf_alloc(struct sca_softc *, caddr_t, u_int); 179 180 #if SCA_DEBUG_LEVEL > 0 181 static void sca_frame_print(sca_port_t *, sca_desc_t *, u_int8_t *); 182 #endif 183 184 185 #define sca_read_1(sc, reg) (sc)->sc_read_1(sc, reg) 186 #define sca_read_2(sc, reg) (sc)->sc_read_2(sc, reg) 187 #define sca_write_1(sc, reg, val) (sc)->sc_write_1(sc, reg, val) 188 #define sca_write_2(sc, reg, val) (sc)->sc_write_2(sc, reg, val) 189 190 #define sca_page_addr(sc, addr) ((bus_addr_t)(u_long)(addr) & (sc)->scu_pagemask) 191 192 static inline void 193 msci_write_1(sca_port_t *scp, u_int reg, u_int8_t val) 194 { 195 sca_write_1(scp->sca, scp->msci_off + reg, val); 196 } 197 198 static inline u_int8_t 199 msci_read_1(sca_port_t *scp, u_int reg) 200 { 201 return sca_read_1(scp->sca, scp->msci_off + reg); 202 } 203 204 static inline void 205 dmac_write_1(sca_port_t *scp, u_int reg, u_int8_t val) 206 { 207 sca_write_1(scp->sca, scp->dmac_off + reg, val); 208 } 209 210 static inline void 211 dmac_write_2(sca_port_t *scp, u_int reg, u_int16_t val) 212 { 213 sca_write_2(scp->sca, scp->dmac_off + reg, val); 214 } 215 216 static inline u_int8_t 217 dmac_read_1(sca_port_t *scp, u_int reg) 218 { 219 return sca_read_1(scp->sca, scp->dmac_off + reg); 220 } 221 222 static inline u_int16_t 223 dmac_read_2(sca_port_t *scp, u_int reg) 224 { 225 return sca_read_2(scp->sca, scp->dmac_off + reg); 226 } 227 228 /* 229 * read the chain pointer 230 */ 231 static inline u_int16_t 232 sca_desc_read_chainp(struct sca_softc *sc, struct sca_desc *dp) 233 { 234 if (sc->sc_usedma) 235 return ((dp)->sd_chainp); 236 return (bus_space_read_2(sc->scu_memt, sc->scu_memh, 237 sca_page_addr(sc, dp) + offsetof(struct sca_desc, sd_chainp))); 238 } 239 240 /* 241 * write the chain pointer 242 */ 243 static inline void 244 sca_desc_write_chainp(struct sca_softc *sc, struct sca_desc *dp, u_int16_t cp) 245 { 246 if (sc->sc_usedma) 247 (dp)->sd_chainp = cp; 248 else 249 bus_space_write_2(sc->scu_memt, sc->scu_memh, 250 sca_page_addr(sc, dp) 251 + offsetof(struct sca_desc, sd_chainp), cp); 252 } 253 254 /* 255 * read the buffer pointer 256 */ 257 static inline u_int32_t 258 sca_desc_read_bufp(struct sca_softc *sc, struct sca_desc *dp) 259 { 260 u_int32_t address; 261 262 if (sc->sc_usedma) 263 address = dp->sd_bufp | dp->sd_hbufp << 16; 264 else { 265 address = bus_space_read_2(sc->scu_memt, sc->scu_memh, 266 sca_page_addr(sc, dp) + offsetof(struct sca_desc, sd_bufp)); 267 address |= bus_space_read_1(sc->scu_memt, sc->scu_memh, 268 sca_page_addr(sc, dp) 269 + offsetof(struct sca_desc, sd_hbufp)) << 16; 270 } 271 return (address); 272 } 273 274 /* 275 * write the buffer pointer 276 */ 277 static inline void 278 sca_desc_write_bufp(struct sca_softc *sc, struct sca_desc *dp, u_int32_t bufp) 279 { 280 if (sc->sc_usedma) { 281 dp->sd_bufp = bufp & 0xFFFF; 282 dp->sd_hbufp = (bufp & 0x00FF0000) >> 16; 283 } else { 284 bus_space_write_2(sc->scu_memt, sc->scu_memh, 285 sca_page_addr(sc, dp) + offsetof(struct sca_desc, sd_bufp), 286 bufp & 0xFFFF); 287 bus_space_write_1(sc->scu_memt, sc->scu_memh, 288 sca_page_addr(sc, dp) + offsetof(struct sca_desc, sd_hbufp), 289 (bufp & 0x00FF0000) >> 16); 290 } 291 } 292 293 /* 294 * read the buffer length 295 */ 296 static inline u_int16_t 297 sca_desc_read_buflen(struct sca_softc *sc, struct sca_desc *dp) 298 { 299 if (sc->sc_usedma) 300 return ((dp)->sd_buflen); 301 return (bus_space_read_2(sc->scu_memt, sc->scu_memh, 302 sca_page_addr(sc, dp) + offsetof(struct sca_desc, sd_buflen))); 303 } 304 305 /* 306 * write the buffer length 307 */ 308 static inline void 309 sca_desc_write_buflen(struct sca_softc *sc, struct sca_desc *dp, u_int16_t len) 310 { 311 if (sc->sc_usedma) 312 (dp)->sd_buflen = len; 313 else 314 bus_space_write_2(sc->scu_memt, sc->scu_memh, 315 sca_page_addr(sc, dp) 316 + offsetof(struct sca_desc, sd_buflen), len); 317 } 318 319 /* 320 * read the descriptor status 321 */ 322 static inline u_int8_t 323 sca_desc_read_stat(struct sca_softc *sc, struct sca_desc *dp) 324 { 325 if (sc->sc_usedma) 326 return ((dp)->sd_stat); 327 return (bus_space_read_1(sc->scu_memt, sc->scu_memh, 328 sca_page_addr(sc, dp) + offsetof(struct sca_desc, sd_stat))); 329 } 330 331 /* 332 * write the descriptor status 333 */ 334 static inline void 335 sca_desc_write_stat(struct sca_softc *sc, struct sca_desc *dp, u_int8_t stat) 336 { 337 if (sc->sc_usedma) 338 (dp)->sd_stat = stat; 339 else 340 bus_space_write_1(sc->scu_memt, sc->scu_memh, 341 sca_page_addr(sc, dp) + offsetof(struct sca_desc, sd_stat), 342 stat); 343 } 344 345 void 346 sca_init(struct sca_softc *sc) 347 { 348 /* 349 * Do a little sanity check: check number of ports. 350 */ 351 if (sc->sc_numports < 1 || sc->sc_numports > 2) 352 panic("sca can\'t handle more than 2 or less than 1 ports"); 353 354 /* 355 * disable DMA and MSCI interrupts 356 */ 357 sca_write_1(sc, SCA_DMER, 0); 358 sca_write_1(sc, SCA_IER0, 0); 359 sca_write_1(sc, SCA_IER1, 0); 360 sca_write_1(sc, SCA_IER2, 0); 361 362 /* 363 * configure interrupt system 364 */ 365 sca_write_1(sc, SCA_ITCR, 366 SCA_ITCR_INTR_PRI_MSCI | SCA_ITCR_ACK_NONE | SCA_ITCR_VOUT_IVR); 367 #if 0 368 /* these are for the intrerrupt ack cycle which we don't use */ 369 sca_write_1(sc, SCA_IVR, 0x40); 370 sca_write_1(sc, SCA_IMVR, 0x40); 371 #endif 372 373 /* 374 * set wait control register to zero wait states 375 */ 376 sca_write_1(sc, SCA_PABR0, 0); 377 sca_write_1(sc, SCA_PABR1, 0); 378 sca_write_1(sc, SCA_WCRL, 0); 379 sca_write_1(sc, SCA_WCRM, 0); 380 sca_write_1(sc, SCA_WCRH, 0); 381 382 /* 383 * disable DMA and reset status 384 */ 385 sca_write_1(sc, SCA_PCR, SCA_PCR_PR2); 386 387 /* 388 * disable transmit DMA for all channels 389 */ 390 sca_write_1(sc, SCA_DSR0 + SCA_DMAC_OFF_0, 0); 391 sca_write_1(sc, SCA_DCR0 + SCA_DMAC_OFF_0, SCA_DCR_ABRT); 392 sca_write_1(sc, SCA_DSR1 + SCA_DMAC_OFF_0, 0); 393 sca_write_1(sc, SCA_DCR1 + SCA_DMAC_OFF_0, SCA_DCR_ABRT); 394 sca_write_1(sc, SCA_DSR0 + SCA_DMAC_OFF_1, 0); 395 sca_write_1(sc, SCA_DCR0 + SCA_DMAC_OFF_1, SCA_DCR_ABRT); 396 sca_write_1(sc, SCA_DSR1 + SCA_DMAC_OFF_1, 0); 397 sca_write_1(sc, SCA_DCR1 + SCA_DMAC_OFF_1, SCA_DCR_ABRT); 398 399 /* 400 * enable DMA based on channel enable flags for each channel 401 */ 402 sca_write_1(sc, SCA_DMER, SCA_DMER_EN); 403 404 /* 405 * Should check to see if the chip is responding, but for now 406 * assume it is. 407 */ 408 } 409 410 /* 411 * initialize the port and attach it to the networking layer 412 */ 413 void 414 sca_port_attach(struct sca_softc *sc, u_int port) 415 { 416 struct timeval now; 417 sca_port_t *scp = &sc->sc_ports[port]; 418 struct ifnet *ifp; 419 static u_int ntwo_unit = 0; 420 421 scp->sca = sc; /* point back to the parent */ 422 423 scp->sp_port = port; 424 425 if (port == 0) { 426 scp->msci_off = SCA_MSCI_OFF_0; 427 scp->dmac_off = SCA_DMAC_OFF_0; 428 if(sc->sc_parent != NULL) 429 ntwo_unit = device_unit(sc->sc_parent) * 2 + 0; 430 else 431 ntwo_unit = 0; /* XXX */ 432 } else { 433 scp->msci_off = SCA_MSCI_OFF_1; 434 scp->dmac_off = SCA_DMAC_OFF_1; 435 if(sc->sc_parent != NULL) 436 ntwo_unit = device_unit(sc->sc_parent) * 2 + 1; 437 else 438 ntwo_unit = 1; /* XXX */ 439 } 440 441 sca_msci_init(sc, scp); 442 sca_dmac_init(sc, scp); 443 444 /* 445 * attach to the network layer 446 */ 447 ifp = &scp->sp_if; 448 snprintf(ifp->if_xname, sizeof(ifp->if_xname), "ntwo%d", ntwo_unit); 449 ifp->if_softc = scp; 450 ifp->if_mtu = SCA_MTU; 451 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST; 452 ifp->if_type = IFT_PTPSERIAL; 453 ifp->if_hdrlen = HDLC_HDRLEN; 454 ifp->if_ioctl = sca_ioctl; 455 ifp->if_output = sca_output; 456 ifp->if_watchdog = sca_watchdog; 457 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 458 scp->linkq.ifq_maxlen = 5; /* if we exceed this we are hosed already */ 459 #ifdef SCA_USE_FASTQ 460 scp->fastq.ifq_maxlen = IFQ_MAXLEN; 461 #endif 462 IFQ_SET_READY(&ifp->if_snd); 463 if_attach(ifp); 464 if_alloc_sadl(ifp); 465 466 #if NBPFILTER > 0 467 bpfattach(ifp, DLT_HDLC, HDLC_HDRLEN); 468 #endif 469 470 if (sc->sc_parent == NULL) 471 printf("%s: port %d\n", ifp->if_xname, port); 472 else 473 printf("%s at %s port %d\n", 474 ifp->if_xname, sc->sc_parent->dv_xname, port); 475 476 /* 477 * reset the last seen times on the cisco keepalive protocol 478 */ 479 getmicrotime(&now); 480 scp->cka_lasttx = now.tv_usec; 481 scp->cka_lastrx = 0; 482 } 483 484 #if 0 485 /* 486 * returns log2(div), sets 'tmc' for the required freq 'hz' 487 */ 488 static u_int8_t 489 sca_msci_get_baud_rate_values(u_int32_t hz, u_int8_t *tmcp) 490 { 491 u_int32_t tmc, div; 492 u_int32_t clock; 493 494 /* clock hz = (chipclock / tmc) / 2^(div); */ 495 /* 496 * TD == tmc * 2^(n) 497 * 498 * note: 499 * 1 <= TD <= 256 TD is inc of 1 500 * 2 <= TD <= 512 TD is inc of 2 501 * 4 <= TD <= 1024 TD is inc of 4 502 * ... 503 * 512 <= TD <= 256*512 TD is inc of 512 504 * 505 * so note there are overlaps. We lose prec 506 * as div increases so we wish to minize div. 507 * 508 * basically we want to do 509 * 510 * tmc = chip / hz, but have tmc <= 256 511 */ 512 513 /* assume system clock is 9.8304MHz or 9830400Hz */ 514 clock = clock = 9830400 >> 1; 515 516 /* round down */ 517 div = 0; 518 while ((tmc = clock / hz) > 256 || (tmc == 256 && (clock / tmc) > hz)) { 519 clock >>= 1; 520 div++; 521 } 522 if (clock / tmc > hz) 523 tmc++; 524 if (!tmc) 525 tmc = 1; 526 527 if (div > SCA_RXS_DIV_512) { 528 /* set to maximums */ 529 div = SCA_RXS_DIV_512; 530 tmc = 0; 531 } 532 533 *tmcp = (tmc & 0xFF); /* 0 == 256 */ 534 return (div & 0xFF); 535 } 536 #endif 537 538 /* 539 * initialize the port's MSCI 540 */ 541 static void 542 sca_msci_init(struct sca_softc *sc, sca_port_t *scp) 543 { 544 /* reset the channel */ 545 msci_write_1(scp, SCA_CMD0, SCA_CMD_RESET); 546 547 msci_write_1(scp, SCA_MD00, 548 ( SCA_MD0_CRC_1 549 | SCA_MD0_CRC_CCITT 550 | SCA_MD0_CRC_ENABLE 551 | SCA_MD0_MODE_HDLC)); 552 #if 0 553 /* immediately send receive reset so the above takes */ 554 msci_write_1(scp, SCA_CMD0, SCA_CMD_RXRESET); 555 #endif 556 557 msci_write_1(scp, SCA_MD10, SCA_MD1_NOADDRCHK); 558 msci_write_1(scp, SCA_MD20, 559 (SCA_MD2_DUPLEX | SCA_MD2_ADPLLx8 | SCA_MD2_NRZ)); 560 561 /* be safe and do it again */ 562 msci_write_1(scp, SCA_CMD0, SCA_CMD_RXRESET); 563 564 /* setup underrun and idle control, and initial RTS state */ 565 msci_write_1(scp, SCA_CTL0, 566 (SCA_CTL_IDLC_PATTERN 567 | SCA_CTL_UDRNC_AFTER_FCS 568 | SCA_CTL_RTS_LOW)); 569 570 /* reset the transmitter */ 571 msci_write_1(scp, SCA_CMD0, SCA_CMD_TXRESET); 572 573 /* 574 * set the clock sources 575 */ 576 msci_write_1(scp, SCA_RXS0, scp->sp_rxs); 577 msci_write_1(scp, SCA_TXS0, scp->sp_txs); 578 msci_write_1(scp, SCA_TMC0, scp->sp_tmc); 579 580 /* set external clock generate as requested */ 581 sc->sc_clock_callback(sc->sc_aux, scp->sp_port, scp->sp_eclock); 582 583 /* 584 * XXX don't pay attention to CTS or CD changes right now. I can't 585 * simulate one, and the transmitter will try to transmit even if 586 * CD isn't there anyway, so nothing bad SHOULD happen. 587 */ 588 #if 0 589 msci_write_1(scp, SCA_IE00, 0); 590 msci_write_1(scp, SCA_IE10, 0); /* 0x0c == CD and CTS changes only */ 591 #else 592 /* this would deliver transmitter underrun to ST1/ISR1 */ 593 msci_write_1(scp, SCA_IE10, SCA_ST1_UDRN); 594 msci_write_1(scp, SCA_IE00, SCA_ST0_TXINT); 595 #endif 596 msci_write_1(scp, SCA_IE20, 0); 597 598 msci_write_1(scp, SCA_FIE0, 0); 599 600 msci_write_1(scp, SCA_SA00, 0); 601 msci_write_1(scp, SCA_SA10, 0); 602 603 msci_write_1(scp, SCA_IDL0, 0x7e); 604 605 msci_write_1(scp, SCA_RRC0, 0x0e); 606 /* msci_write_1(scp, SCA_TRC00, 0x10); */ 607 /* 608 * the correct values here are important for avoiding underruns 609 * for any value less than or equal to TRC0 txrdy is activated 610 * which will start the dmac transfer to the fifo. 611 * for buffer size >= TRC1 + 1 txrdy is cleared which will stop DMA. 612 * 613 * thus if we are using a very fast clock that empties the fifo 614 * quickly, delays in the dmac starting to fill the fifo can 615 * lead to underruns so we want a fairly full fifo to still 616 * cause the dmac to start. for cards with on board ram this 617 * has no effect on system performance. For cards that DMA 618 * to/from system memory it will cause more, shorter, 619 * bus accesses rather than fewer longer ones. 620 */ 621 msci_write_1(scp, SCA_TRC00, 0x00); 622 msci_write_1(scp, SCA_TRC10, 0x1f); 623 } 624 625 /* 626 * Take the memory for the port and construct two circular linked lists of 627 * descriptors (one tx, one rx) and set the pointers in these descriptors 628 * to point to the buffer space for this port. 629 */ 630 static void 631 sca_dmac_init(struct sca_softc *sc, sca_port_t *scp) 632 { 633 sca_desc_t *desc; 634 u_int32_t desc_p; 635 u_int32_t buf_p; 636 int i; 637 638 if (sc->sc_usedma) 639 bus_dmamap_sync(sc->scu_dmat, sc->scu_dmam, 0, sc->scu_allocsize, 640 BUS_DMASYNC_PREWRITE); 641 else { 642 /* 643 * XXX assumes that all tx desc and bufs in same page 644 */ 645 sc->scu_page_on(sc); 646 sc->scu_set_page(sc, scp->sp_txdesc_p); 647 } 648 649 desc = scp->sp_txdesc; 650 desc_p = scp->sp_txdesc_p; 651 buf_p = scp->sp_txbuf_p; 652 scp->sp_txcur = 0; 653 scp->sp_txinuse = 0; 654 655 #ifdef DEBUG 656 /* make sure that we won't wrap */ 657 if ((desc_p & 0xffff0000) != 658 ((desc_p + sizeof(*desc) * scp->sp_ntxdesc) & 0xffff0000)) 659 panic("sca: tx descriptors cross architecural boundary"); 660 if ((buf_p & 0xff000000) != 661 ((buf_p + SCA_BSIZE * scp->sp_ntxdesc) & 0xff000000)) 662 panic("sca: tx buffers cross architecural boundary"); 663 #endif 664 665 for (i = 0 ; i < scp->sp_ntxdesc ; i++) { 666 /* 667 * desc_p points to the physcial address of the NEXT desc 668 */ 669 desc_p += sizeof(sca_desc_t); 670 671 sca_desc_write_chainp(sc, desc, desc_p & 0x0000ffff); 672 sca_desc_write_bufp(sc, desc, buf_p); 673 sca_desc_write_buflen(sc, desc, SCA_BSIZE); 674 sca_desc_write_stat(sc, desc, 0); 675 676 desc++; /* point to the next descriptor */ 677 buf_p += SCA_BSIZE; 678 } 679 680 /* 681 * "heal" the circular list by making the last entry point to the 682 * first. 683 */ 684 sca_desc_write_chainp(sc, desc - 1, scp->sp_txdesc_p & 0x0000ffff); 685 686 /* 687 * Now, initialize the transmit DMA logic 688 * 689 * CPB == chain pointer base address 690 */ 691 dmac_write_1(scp, SCA_DSR1, 0); 692 dmac_write_1(scp, SCA_DCR1, SCA_DCR_ABRT); 693 dmac_write_1(scp, SCA_DMR1, SCA_DMR_TMOD | SCA_DMR_NF); 694 /* XXX1 695 dmac_write_1(scp, SCA_DIR1, 696 (SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF)); 697 */ 698 dmac_write_1(scp, SCA_DIR1, 699 (SCA_DIR_EOM | SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF)); 700 dmac_write_1(scp, SCA_CPB1, 701 (u_int8_t)((scp->sp_txdesc_p & 0x00ff0000) >> 16)); 702 703 /* 704 * now, do the same thing for receive descriptors 705 * 706 * XXX assumes that all rx desc and bufs in same page 707 */ 708 if (!sc->sc_usedma) 709 sc->scu_set_page(sc, scp->sp_rxdesc_p); 710 711 desc = scp->sp_rxdesc; 712 desc_p = scp->sp_rxdesc_p; 713 buf_p = scp->sp_rxbuf_p; 714 715 #ifdef DEBUG 716 /* make sure that we won't wrap */ 717 if ((desc_p & 0xffff0000) != 718 ((desc_p + sizeof(*desc) * scp->sp_nrxdesc) & 0xffff0000)) 719 panic("sca: rx descriptors cross architecural boundary"); 720 if ((buf_p & 0xff000000) != 721 ((buf_p + SCA_BSIZE * scp->sp_nrxdesc) & 0xff000000)) 722 panic("sca: rx buffers cross architecural boundary"); 723 #endif 724 725 for (i = 0 ; i < scp->sp_nrxdesc; i++) { 726 /* 727 * desc_p points to the physcial address of the NEXT desc 728 */ 729 desc_p += sizeof(sca_desc_t); 730 731 sca_desc_write_chainp(sc, desc, desc_p & 0x0000ffff); 732 sca_desc_write_bufp(sc, desc, buf_p); 733 /* sca_desc_write_buflen(sc, desc, SCA_BSIZE); */ 734 sca_desc_write_buflen(sc, desc, 0); 735 sca_desc_write_stat(sc, desc, 0); 736 737 desc++; /* point to the next descriptor */ 738 buf_p += SCA_BSIZE; 739 } 740 741 /* 742 * "heal" the circular list by making the last entry point to the 743 * first. 744 */ 745 sca_desc_write_chainp(sc, desc - 1, scp->sp_rxdesc_p & 0x0000ffff); 746 747 sca_dmac_rxinit(scp); 748 749 if (sc->sc_usedma) 750 bus_dmamap_sync(sc->scu_dmat, sc->scu_dmam, 751 0, sc->scu_allocsize, BUS_DMASYNC_POSTWRITE); 752 else 753 sc->scu_page_off(sc); 754 } 755 756 /* 757 * reset and reinitialize the receive DMA logic 758 */ 759 static void 760 sca_dmac_rxinit(sca_port_t *scp) 761 { 762 /* 763 * ... and the receive DMA logic ... 764 */ 765 dmac_write_1(scp, SCA_DSR0, 0); /* disable DMA */ 766 dmac_write_1(scp, SCA_DCR0, SCA_DCR_ABRT); 767 768 dmac_write_1(scp, SCA_DMR0, SCA_DMR_TMOD | SCA_DMR_NF); 769 dmac_write_2(scp, SCA_BFLL0, SCA_BSIZE); 770 771 /* reset descriptors to initial state */ 772 scp->sp_rxstart = 0; 773 scp->sp_rxend = scp->sp_nrxdesc - 1; 774 775 /* 776 * CPB == chain pointer base 777 * CDA == current descriptor address 778 * EDA == error descriptor address (overwrite position) 779 * because cda can't be eda when starting we always 780 * have a single buffer gap between cda and eda 781 */ 782 dmac_write_1(scp, SCA_CPB0, 783 (u_int8_t)((scp->sp_rxdesc_p & 0x00ff0000) >> 16)); 784 dmac_write_2(scp, SCA_CDAL0, (u_int16_t)(scp->sp_rxdesc_p & 0xffff)); 785 dmac_write_2(scp, SCA_EDAL0, (u_int16_t) 786 (scp->sp_rxdesc_p + (sizeof(sca_desc_t) * scp->sp_rxend))); 787 788 /* 789 * enable receiver DMA 790 */ 791 dmac_write_1(scp, SCA_DIR0, 792 (SCA_DIR_EOT | SCA_DIR_EOM | SCA_DIR_BOF | SCA_DIR_COF)); 793 dmac_write_1(scp, SCA_DSR0, SCA_DSR_DE); 794 } 795 796 /* 797 * Queue the packet for our start routine to transmit 798 */ 799 static int 800 sca_output( 801 struct ifnet *ifp, 802 struct mbuf *m, 803 struct sockaddr *dst, 804 struct rtentry *rt0) 805 { 806 #ifdef ISO 807 struct hdlc_llc_header *llc; 808 #endif 809 struct hdlc_header *hdlc; 810 struct ifqueue *ifq = NULL; 811 int s, error, len; 812 short mflags; 813 ALTQ_DECL(struct altq_pktattr pktattr;) 814 815 error = 0; 816 817 if ((ifp->if_flags & IFF_UP) != IFF_UP) { 818 error = ENETDOWN; 819 goto bad; 820 } 821 822 /* 823 * If the queueing discipline needs packet classification, 824 * do it before prepending link headers. 825 */ 826 IFQ_CLASSIFY(&ifp->if_snd, m, dst->sa_family, &pktattr); 827 828 /* 829 * determine address family, and priority for this packet 830 */ 831 switch (dst->sa_family) { 832 #ifdef INET 833 case AF_INET: 834 #ifdef SCA_USE_FASTQ 835 if ((mtod(m, struct ip *)->ip_tos & IPTOS_LOWDELAY) 836 == IPTOS_LOWDELAY) 837 ifq = &((sca_port_t *)ifp->if_softc)->fastq; 838 #endif 839 /* 840 * Add cisco serial line header. If there is no 841 * space in the first mbuf, allocate another. 842 */ 843 M_PREPEND(m, sizeof(struct hdlc_header), M_DONTWAIT); 844 if (m == 0) 845 return (ENOBUFS); 846 hdlc = mtod(m, struct hdlc_header *); 847 hdlc->h_proto = htons(HDLC_PROTOCOL_IP); 848 break; 849 #endif 850 #ifdef INET6 851 case AF_INET6: 852 /* 853 * Add cisco serial line header. If there is no 854 * space in the first mbuf, allocate another. 855 */ 856 M_PREPEND(m, sizeof(struct hdlc_header), M_DONTWAIT); 857 if (m == 0) 858 return (ENOBUFS); 859 hdlc = mtod(m, struct hdlc_header *); 860 hdlc->h_proto = htons(HDLC_PROTOCOL_IPV6); 861 break; 862 #endif 863 #ifdef ISO 864 case AF_ISO: 865 /* 866 * Add cisco llc serial line header. If there is no 867 * space in the first mbuf, allocate another. 868 */ 869 M_PREPEND(m, sizeof(struct hdlc_llc_header), M_DONTWAIT); 870 if (m == 0) 871 return (ENOBUFS); 872 hdlc = mtod(m, struct hdlc_header *); 873 llc = mtod(m, struct hdlc_llc_header *); 874 llc->hl_dsap = llc->hl_ssap = LLC_ISO_LSAP; 875 llc->hl_ffb = 0; 876 break; 877 #endif 878 default: 879 printf("%s: address family %d unsupported\n", 880 ifp->if_xname, dst->sa_family); 881 error = EAFNOSUPPORT; 882 goto bad; 883 } 884 885 /* finish */ 886 if ((m->m_flags & (M_BCAST | M_MCAST)) != 0) 887 hdlc->h_addr = CISCO_MULTICAST; 888 else 889 hdlc->h_addr = CISCO_UNICAST; 890 hdlc->h_resv = 0; 891 892 /* 893 * queue the packet. If interactive, use the fast queue. 894 */ 895 mflags = m->m_flags; 896 len = m->m_pkthdr.len; 897 s = splnet(); 898 if (ifq != NULL) { 899 if (IF_QFULL(ifq)) { 900 IF_DROP(ifq); 901 m_freem(m); 902 error = ENOBUFS; 903 } else 904 IF_ENQUEUE(ifq, m); 905 } else 906 IFQ_ENQUEUE(&ifp->if_snd, m, &pktattr, error); 907 if (error != 0) { 908 splx(s); 909 ifp->if_oerrors++; 910 ifp->if_collisions++; 911 return (error); 912 } 913 ifp->if_obytes += len; 914 if (mflags & M_MCAST) 915 ifp->if_omcasts++; 916 917 sca_start(ifp); 918 splx(s); 919 920 return (error); 921 922 bad: 923 if (m) 924 m_freem(m); 925 return (error); 926 } 927 928 static int 929 sca_ioctl(ifp, cmd, addr) 930 struct ifnet *ifp; 931 u_long cmd; 932 caddr_t addr; 933 { 934 struct ifreq *ifr; 935 struct ifaddr *ifa; 936 int error; 937 int s; 938 939 s = splnet(); 940 941 ifr = (struct ifreq *)addr; 942 ifa = (struct ifaddr *)addr; 943 error = 0; 944 945 switch (cmd) { 946 case SIOCSIFADDR: 947 switch(ifa->ifa_addr->sa_family) { 948 #ifdef INET 949 case AF_INET: 950 #endif 951 #ifdef INET6 952 case AF_INET6: 953 #endif 954 #if defined(INET) || defined(INET6) 955 ifp->if_flags |= IFF_UP; 956 sca_port_up(ifp->if_softc); 957 break; 958 #endif 959 default: 960 error = EAFNOSUPPORT; 961 break; 962 } 963 break; 964 965 case SIOCSIFDSTADDR: 966 #ifdef INET 967 if (ifa->ifa_addr->sa_family == AF_INET) 968 break; 969 #endif 970 #ifdef INET6 971 if (ifa->ifa_addr->sa_family == AF_INET6) 972 break; 973 #endif 974 error = EAFNOSUPPORT; 975 break; 976 977 case SIOCADDMULTI: 978 case SIOCDELMULTI: 979 /* XXX need multicast group management code */ 980 if (ifr == 0) { 981 error = EAFNOSUPPORT; /* XXX */ 982 break; 983 } 984 switch (ifr->ifr_addr.sa_family) { 985 #ifdef INET 986 case AF_INET: 987 break; 988 #endif 989 #ifdef INET6 990 case AF_INET6: 991 break; 992 #endif 993 default: 994 error = EAFNOSUPPORT; 995 break; 996 } 997 break; 998 999 case SIOCSIFFLAGS: 1000 if (ifr->ifr_flags & IFF_UP) { 1001 ifp->if_flags |= IFF_UP; 1002 sca_port_up(ifp->if_softc); 1003 } else { 1004 ifp->if_flags &= ~IFF_UP; 1005 sca_port_down(ifp->if_softc); 1006 } 1007 1008 break; 1009 1010 default: 1011 error = EINVAL; 1012 } 1013 1014 splx(s); 1015 return error; 1016 } 1017 1018 /* 1019 * start packet transmission on the interface 1020 * 1021 * MUST BE CALLED AT splnet() 1022 */ 1023 static void 1024 sca_start(ifp) 1025 struct ifnet *ifp; 1026 { 1027 sca_port_t *scp = ifp->if_softc; 1028 struct sca_softc *sc = scp->sca; 1029 struct mbuf *m, *mb_head; 1030 sca_desc_t *desc; 1031 u_int8_t *buf, stat; 1032 u_int32_t buf_p; 1033 int nexttx; 1034 int trigger_xmit; 1035 u_int len; 1036 1037 SCA_DPRINTF(SCA_DEBUG_TX, ("TX: enter start\n")); 1038 1039 /* 1040 * can't queue when we are full or transmitter is busy 1041 */ 1042 #ifdef oldcode 1043 if ((scp->sp_txinuse >= (scp->sp_ntxdesc - 1)) 1044 || ((ifp->if_flags & IFF_OACTIVE) == IFF_OACTIVE)) 1045 return; 1046 #else 1047 if (scp->sp_txinuse 1048 || ((ifp->if_flags & IFF_OACTIVE) == IFF_OACTIVE)) 1049 return; 1050 #endif 1051 SCA_DPRINTF(SCA_DEBUG_TX, ("TX: txinuse %d\n", scp->sp_txinuse)); 1052 1053 /* 1054 * XXX assume that all tx desc and bufs in same page 1055 */ 1056 if (sc->sc_usedma) 1057 bus_dmamap_sync(sc->scu_dmat, sc->scu_dmam, 1058 0, sc->scu_allocsize, 1059 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1060 else { 1061 sc->scu_page_on(sc); 1062 sc->scu_set_page(sc, scp->sp_txdesc_p); 1063 } 1064 1065 trigger_xmit = 0; 1066 1067 txloop: 1068 IF_DEQUEUE(&scp->linkq, mb_head); 1069 if (mb_head == NULL) 1070 #ifdef SCA_USE_FASTQ 1071 IF_DEQUEUE(&scp->fastq, mb_head); 1072 if (mb_head == NULL) 1073 #endif 1074 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1075 if (mb_head == NULL) 1076 goto start_xmit; 1077 1078 SCA_DPRINTF(SCA_DEBUG_TX, ("TX: got mbuf\n")); 1079 #ifdef oldcode 1080 if (scp->txinuse != 0) { 1081 /* Kill EOT interrupts on the previous descriptor. */ 1082 desc = &scp->sp_txdesc[scp->txcur]; 1083 stat = sca_desc_read_stat(sc, desc); 1084 sca_desc_write_stat(sc, desc, stat & ~SCA_DESC_EOT); 1085 1086 /* Figure out what the next free descriptor is. */ 1087 nexttx = (scp->sp_txcur + 1) % scp->sp_ntxdesc; 1088 } else 1089 nexttx = 0; 1090 #endif /* oldcode */ 1091 1092 if (scp->sp_txinuse) 1093 nexttx = (scp->sp_txcur + 1) % scp->sp_ntxdesc; 1094 else 1095 nexttx = 0; 1096 1097 SCA_DPRINTF(SCA_DEBUG_TX, ("TX: nexttx %d\n", nexttx)); 1098 1099 buf = scp->sp_txbuf + SCA_BSIZE * nexttx; 1100 buf_p = scp->sp_txbuf_p + SCA_BSIZE * nexttx; 1101 1102 /* XXX hoping we can delay the desc write till after we don't drop. */ 1103 desc = &scp->sp_txdesc[nexttx]; 1104 1105 /* XXX isn't this set already?? */ 1106 sca_desc_write_bufp(sc, desc, buf_p); 1107 len = 0; 1108 1109 SCA_DPRINTF(SCA_DEBUG_TX, ("TX: buf %x buf_p %x\n", (u_int)buf, buf_p)); 1110 1111 #if 0 /* uncomment this for a core in cc1 */ 1112 X 1113 #endif 1114 /* 1115 * Run through the chain, copying data into the descriptor as we 1116 * go. If it won't fit in one transmission block, drop the packet. 1117 * No, this isn't nice, but most of the time it _will_ fit. 1118 */ 1119 for (m = mb_head ; m != NULL ; m = m->m_next) { 1120 if (m->m_len != 0) { 1121 len += m->m_len; 1122 if (len > SCA_BSIZE) { 1123 m_freem(mb_head); 1124 goto txloop; 1125 } 1126 SCA_DPRINTF(SCA_DEBUG_TX, 1127 ("TX: about to mbuf len %d\n", m->m_len)); 1128 1129 if (sc->sc_usedma) 1130 memcpy(buf, mtod(m, u_int8_t *), m->m_len); 1131 else 1132 bus_space_write_region_1(sc->scu_memt, 1133 sc->scu_memh, sca_page_addr(sc, buf_p), 1134 mtod(m, u_int8_t *), m->m_len); 1135 buf += m->m_len; 1136 buf_p += m->m_len; 1137 } 1138 } 1139 1140 /* set the buffer, the length, and mark end of frame and end of xfer */ 1141 sca_desc_write_buflen(sc, desc, len); 1142 sca_desc_write_stat(sc, desc, SCA_DESC_EOM); 1143 1144 ifp->if_opackets++; 1145 1146 #if NBPFILTER > 0 1147 /* 1148 * Pass packet to bpf if there is a listener. 1149 */ 1150 if (ifp->if_bpf) 1151 bpf_mtap(ifp->if_bpf, mb_head); 1152 #endif 1153 1154 m_freem(mb_head); 1155 1156 scp->sp_txcur = nexttx; 1157 scp->sp_txinuse++; 1158 trigger_xmit = 1; 1159 1160 SCA_DPRINTF(SCA_DEBUG_TX, 1161 ("TX: inuse %d index %d\n", scp->sp_txinuse, scp->sp_txcur)); 1162 1163 /* 1164 * XXX so didn't this used to limit us to 1?! - multi may be untested 1165 * sp_ntxdesc used to be hard coded to 2 with claim of a too hard 1166 * to find bug 1167 */ 1168 #ifdef oldcode 1169 if (scp->sp_txinuse < (scp->sp_ntxdesc - 1)) 1170 #endif 1171 if (scp->sp_txinuse < scp->sp_ntxdesc) 1172 goto txloop; 1173 1174 start_xmit: 1175 SCA_DPRINTF(SCA_DEBUG_TX, ("TX: trigger_xmit %d\n", trigger_xmit)); 1176 1177 if (trigger_xmit != 0) { 1178 /* set EOT on final descriptor */ 1179 desc = &scp->sp_txdesc[scp->sp_txcur]; 1180 stat = sca_desc_read_stat(sc, desc); 1181 sca_desc_write_stat(sc, desc, stat | SCA_DESC_EOT); 1182 } 1183 1184 if (sc->sc_usedma) 1185 bus_dmamap_sync(sc->scu_dmat, sc->scu_dmam, 0, 1186 sc->scu_allocsize, 1187 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1188 1189 if (trigger_xmit != 0) 1190 sca_port_starttx(scp); 1191 1192 if (!sc->sc_usedma) 1193 sc->scu_page_off(sc); 1194 } 1195 1196 static void 1197 sca_watchdog(struct ifnet *ifp) 1198 { 1199 } 1200 1201 int 1202 sca_hardintr(struct sca_softc *sc) 1203 { 1204 u_int8_t isr0, isr1, isr2; 1205 int ret; 1206 1207 ret = 0; /* non-zero means we processed at least one interrupt */ 1208 1209 SCA_DPRINTF(SCA_DEBUG_INTR, ("sca_hardintr entered\n")); 1210 1211 while (1) { 1212 /* 1213 * read SCA interrupts 1214 */ 1215 isr0 = sca_read_1(sc, SCA_ISR0); 1216 isr1 = sca_read_1(sc, SCA_ISR1); 1217 isr2 = sca_read_1(sc, SCA_ISR2); 1218 1219 if (isr0 == 0 && isr1 == 0 && isr2 == 0) 1220 break; 1221 1222 SCA_DPRINTF(SCA_DEBUG_INTR, 1223 ("isr0 = %02x, isr1 = %02x, isr2 = %02x\n", 1224 isr0, isr1, isr2)); 1225 1226 /* 1227 * check DMAC interrupt 1228 */ 1229 if (isr1 & 0x0f) 1230 ret += sca_dmac_intr(&sc->sc_ports[0], 1231 isr1 & 0x0f); 1232 1233 if (isr1 & 0xf0) 1234 ret += sca_dmac_intr(&sc->sc_ports[1], 1235 (isr1 & 0xf0) >> 4); 1236 1237 /* 1238 * mcsi intterupts 1239 */ 1240 if (isr0 & 0x0f) 1241 ret += sca_msci_intr(&sc->sc_ports[0], isr0 & 0x0f); 1242 1243 if (isr0 & 0xf0) 1244 ret += sca_msci_intr(&sc->sc_ports[1], 1245 (isr0 & 0xf0) >> 4); 1246 1247 #if 0 /* We don't GET timer interrupts, we have them disabled (msci IE20) */ 1248 if (isr2) 1249 ret += sca_timer_intr(sc, isr2); 1250 #endif 1251 } 1252 1253 return (ret); 1254 } 1255 1256 static int 1257 sca_dmac_intr(sca_port_t *scp, u_int8_t isr) 1258 { 1259 u_int8_t dsr; 1260 int ret; 1261 1262 ret = 0; 1263 1264 /* 1265 * Check transmit channel 1266 */ 1267 if (isr & (SCA_ISR1_DMAC_TX0A | SCA_ISR1_DMAC_TX0B)) { 1268 SCA_DPRINTF(SCA_DEBUG_INTR, 1269 ("TX INTERRUPT port %d\n", scp->sp_port)); 1270 1271 dsr = 1; 1272 while (dsr != 0) { 1273 ret++; 1274 /* 1275 * reset interrupt 1276 */ 1277 dsr = dmac_read_1(scp, SCA_DSR1); 1278 dmac_write_1(scp, SCA_DSR1, 1279 dsr | SCA_DSR_DEWD); 1280 1281 /* 1282 * filter out the bits we don't care about 1283 */ 1284 dsr &= ( SCA_DSR_COF | SCA_DSR_BOF | SCA_DSR_EOT); 1285 if (dsr == 0) 1286 break; 1287 1288 /* 1289 * check for counter overflow 1290 */ 1291 if (dsr & SCA_DSR_COF) { 1292 printf("%s: TXDMA counter overflow\n", 1293 scp->sp_if.if_xname); 1294 1295 scp->sp_if.if_flags &= ~IFF_OACTIVE; 1296 scp->sp_txcur = 0; 1297 scp->sp_txinuse = 0; 1298 } 1299 1300 /* 1301 * check for buffer overflow 1302 */ 1303 if (dsr & SCA_DSR_BOF) { 1304 printf("%s: TXDMA buffer overflow, cda 0x%04x, eda 0x%04x, cpb 0x%02x\n", 1305 scp->sp_if.if_xname, 1306 dmac_read_2(scp, SCA_CDAL1), 1307 dmac_read_2(scp, SCA_EDAL1), 1308 dmac_read_1(scp, SCA_CPB1)); 1309 1310 /* 1311 * Yikes. Arrange for a full 1312 * transmitter restart. 1313 */ 1314 scp->sp_if.if_flags &= ~IFF_OACTIVE; 1315 scp->sp_txcur = 0; 1316 scp->sp_txinuse = 0; 1317 } 1318 1319 /* 1320 * check for end of transfer, which is not 1321 * an error. It means that all data queued 1322 * was transmitted, and we mark ourself as 1323 * not in use and stop the watchdog timer. 1324 */ 1325 if (dsr & SCA_DSR_EOT) { 1326 SCA_DPRINTF(SCA_DEBUG_TX, 1327 ("Transmit completed. cda %x eda %x dsr %x\n", 1328 dmac_read_2(scp, SCA_CDAL1), 1329 dmac_read_2(scp, SCA_EDAL1), 1330 dsr)); 1331 1332 scp->sp_if.if_flags &= ~IFF_OACTIVE; 1333 scp->sp_txcur = 0; 1334 scp->sp_txinuse = 0; 1335 1336 /* 1337 * check for more packets 1338 */ 1339 sca_start(&scp->sp_if); 1340 } 1341 } 1342 } 1343 /* 1344 * receive channel check 1345 */ 1346 if (isr & (SCA_ISR1_DMAC_RX0A | SCA_ISR1_DMAC_RX0B)) { 1347 SCA_DPRINTF(SCA_DEBUG_INTR, ("RX INTERRUPT port %d\n", 1348 (scp == &scp->sca->sc_ports[0] ? 0 : 1))); 1349 1350 dsr = 1; 1351 while (dsr != 0) { 1352 ret++; 1353 1354 dsr = dmac_read_1(scp, SCA_DSR0); 1355 dmac_write_1(scp, SCA_DSR0, dsr | SCA_DSR_DEWD); 1356 1357 /* 1358 * filter out the bits we don't care about 1359 */ 1360 dsr &= (SCA_DSR_EOM | SCA_DSR_COF 1361 | SCA_DSR_BOF | SCA_DSR_EOT); 1362 if (dsr == 0) 1363 break; 1364 1365 /* 1366 * End of frame 1367 */ 1368 if (dsr & SCA_DSR_EOM) { 1369 SCA_DPRINTF(SCA_DEBUG_RX, ("Got a frame!\n")); 1370 1371 sca_get_packets(scp); 1372 } 1373 1374 /* 1375 * check for counter overflow 1376 */ 1377 if (dsr & SCA_DSR_COF) { 1378 printf("%s: RXDMA counter overflow\n", 1379 scp->sp_if.if_xname); 1380 1381 sca_dmac_rxinit(scp); 1382 } 1383 1384 /* 1385 * check for end of transfer, which means we 1386 * ran out of descriptors to receive into. 1387 * This means the line is much faster than 1388 * we can handle. 1389 */ 1390 if (dsr & (SCA_DSR_BOF | SCA_DSR_EOT)) { 1391 printf("%s: RXDMA buffer overflow\n", 1392 scp->sp_if.if_xname); 1393 1394 sca_dmac_rxinit(scp); 1395 } 1396 } 1397 } 1398 1399 return ret; 1400 } 1401 1402 static int 1403 sca_msci_intr(sca_port_t *scp, u_int8_t isr) 1404 { 1405 u_int8_t st1, trc0; 1406 1407 /* get and clear the specific interrupt -- should act on it :)*/ 1408 if ((st1 = msci_read_1(scp, SCA_ST10))) { 1409 /* clear the interrupt */ 1410 msci_write_1(scp, SCA_ST10, st1); 1411 1412 if (st1 & SCA_ST1_UDRN) { 1413 /* underrun -- try to increase ready control */ 1414 trc0 = msci_read_1(scp, SCA_TRC00); 1415 if (trc0 == 0x1f) 1416 printf("TX: underrun - fifo depth maxed\n"); 1417 else { 1418 if ((trc0 += 2) > 0x1f) 1419 trc0 = 0x1f; 1420 SCA_DPRINTF(SCA_DEBUG_TX, 1421 ("TX: udrn - incr fifo to %d\n", trc0)); 1422 msci_write_1(scp, SCA_TRC00, trc0); 1423 } 1424 } 1425 } 1426 return (0); 1427 } 1428 1429 static void 1430 sca_get_packets(sca_port_t *scp) 1431 { 1432 struct sca_softc *sc; 1433 1434 SCA_DPRINTF(SCA_DEBUG_RX, ("RX: sca_get_packets\n")); 1435 1436 sc = scp->sca; 1437 if (sc->sc_usedma) 1438 bus_dmamap_sync(sc->scu_dmat, sc->scu_dmam, 1439 0, sc->scu_allocsize, 1440 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1441 else { 1442 /* 1443 * XXX this code is unable to deal with rx stuff 1444 * in more than 1 page 1445 */ 1446 sc->scu_page_on(sc); 1447 sc->scu_set_page(sc, scp->sp_rxdesc_p); 1448 } 1449 1450 /* process as many frames as are available */ 1451 while (sca_frame_avail(scp)) { 1452 sca_frame_process(scp); 1453 sca_frame_read_done(scp); 1454 } 1455 1456 if (sc->sc_usedma) 1457 bus_dmamap_sync(sc->scu_dmat, sc->scu_dmam, 1458 0, sc->scu_allocsize, 1459 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1460 else 1461 sc->scu_page_off(sc); 1462 } 1463 1464 /* 1465 * Starting with the first descriptor we wanted to read into, up to but 1466 * not including the current SCA read descriptor, look for a packet. 1467 * 1468 * must be called at splnet() 1469 */ 1470 static int 1471 sca_frame_avail(sca_port_t *scp) 1472 { 1473 u_int16_t cda; 1474 u_int32_t desc_p; /* physical address (lower 16 bits) */ 1475 sca_desc_t *desc; 1476 u_int8_t rxstat; 1477 int cdaidx, toolong; 1478 1479 /* 1480 * Read the current descriptor from the SCA. 1481 */ 1482 cda = dmac_read_2(scp, SCA_CDAL0); 1483 1484 /* 1485 * calculate the index of the current descriptor 1486 */ 1487 desc_p = (scp->sp_rxdesc_p & 0xFFFF); 1488 desc_p = cda - desc_p; 1489 cdaidx = desc_p / sizeof(sca_desc_t); 1490 1491 SCA_DPRINTF(SCA_DEBUG_RX, 1492 ("RX: cda %x desc_p %x cdaidx %u, nrxdesc %d rxstart %d\n", 1493 cda, desc_p, cdaidx, scp->sp_nrxdesc, scp->sp_rxstart)); 1494 1495 /* note confusion */ 1496 if (cdaidx >= scp->sp_nrxdesc) 1497 panic("current descriptor index out of range"); 1498 1499 /* see if we have a valid frame available */ 1500 toolong = 0; 1501 for (; scp->sp_rxstart != cdaidx; sca_frame_read_done(scp)) { 1502 /* 1503 * We might have a valid descriptor. Set up a pointer 1504 * to the kva address for it so we can more easily examine 1505 * the contents. 1506 */ 1507 desc = &scp->sp_rxdesc[scp->sp_rxstart]; 1508 rxstat = sca_desc_read_stat(scp->sca, desc); 1509 1510 SCA_DPRINTF(SCA_DEBUG_RX, ("port %d RX: idx %d rxstat %x\n", 1511 scp->sp_port, scp->sp_rxstart, rxstat)); 1512 1513 SCA_DPRINTF(SCA_DEBUG_RX, ("port %d RX: buflen %d\n", 1514 scp->sp_port, sca_desc_read_buflen(scp->sca, desc))); 1515 1516 /* 1517 * check for errors 1518 */ 1519 if (rxstat & SCA_DESC_ERRORS) { 1520 /* 1521 * consider an error condition the end 1522 * of a frame 1523 */ 1524 scp->sp_if.if_ierrors++; 1525 toolong = 0; 1526 continue; 1527 } 1528 1529 /* 1530 * if we aren't skipping overlong frames 1531 * we are done, otherwise reset and look for 1532 * another good frame 1533 */ 1534 if (rxstat & SCA_DESC_EOM) { 1535 if (!toolong) 1536 return (1); 1537 toolong = 0; 1538 } else if (!toolong) { 1539 /* 1540 * we currently don't deal with frames 1541 * larger than a single buffer (fixed MTU) 1542 */ 1543 scp->sp_if.if_ierrors++; 1544 toolong = 1; 1545 } 1546 SCA_DPRINTF(SCA_DEBUG_RX, ("RX: idx %d no EOM\n", 1547 scp->sp_rxstart)); 1548 } 1549 1550 SCA_DPRINTF(SCA_DEBUG_RX, ("RX: returning none\n")); 1551 return 0; 1552 } 1553 1554 /* 1555 * Pass the packet up to the kernel if it is a packet we want to pay 1556 * attention to. 1557 * 1558 * MUST BE CALLED AT splnet() 1559 */ 1560 static void 1561 sca_frame_process(sca_port_t *scp) 1562 { 1563 struct ifqueue *ifq; 1564 struct hdlc_header *hdlc; 1565 struct cisco_pkt *cisco; 1566 sca_desc_t *desc; 1567 struct mbuf *m; 1568 u_int8_t *bufp; 1569 u_int16_t len; 1570 u_int32_t t; 1571 1572 t = time_uptime * 1000; 1573 desc = &scp->sp_rxdesc[scp->sp_rxstart]; 1574 bufp = scp->sp_rxbuf + SCA_BSIZE * scp->sp_rxstart; 1575 len = sca_desc_read_buflen(scp->sca, desc); 1576 1577 SCA_DPRINTF(SCA_DEBUG_RX, 1578 ("RX: desc %lx bufp %lx len %d\n", (bus_addr_t)desc, 1579 (bus_addr_t)bufp, len)); 1580 1581 #if SCA_DEBUG_LEVEL > 0 1582 if (sca_debug & SCA_DEBUG_RXPKT) 1583 sca_frame_print(scp, desc, bufp); 1584 #endif 1585 /* 1586 * skip packets that are too short 1587 */ 1588 if (len < sizeof(struct hdlc_header)) { 1589 scp->sp_if.if_ierrors++; 1590 return; 1591 } 1592 1593 m = sca_mbuf_alloc(scp->sca, bufp, len); 1594 if (m == NULL) { 1595 SCA_DPRINTF(SCA_DEBUG_RX, ("RX: no mbuf!\n")); 1596 return; 1597 } 1598 1599 /* 1600 * read and then strip off the HDLC information 1601 */ 1602 m = m_pullup(m, sizeof(struct hdlc_header)); 1603 if (m == NULL) { 1604 SCA_DPRINTF(SCA_DEBUG_RX, ("RX: no m_pullup!\n")); 1605 return; 1606 } 1607 1608 #if NBPFILTER > 0 1609 if (scp->sp_if.if_bpf) 1610 bpf_mtap(scp->sp_if.if_bpf, m); 1611 #endif 1612 1613 scp->sp_if.if_ipackets++; 1614 1615 hdlc = mtod(m, struct hdlc_header *); 1616 switch (ntohs(hdlc->h_proto)) { 1617 #ifdef INET 1618 case HDLC_PROTOCOL_IP: 1619 SCA_DPRINTF(SCA_DEBUG_RX, ("Received IP packet\n")); 1620 m->m_pkthdr.rcvif = &scp->sp_if; 1621 m->m_pkthdr.len -= sizeof(struct hdlc_header); 1622 m->m_data += sizeof(struct hdlc_header); 1623 m->m_len -= sizeof(struct hdlc_header); 1624 ifq = &ipintrq; 1625 schednetisr(NETISR_IP); 1626 break; 1627 #endif /* INET */ 1628 #ifdef INET6 1629 case HDLC_PROTOCOL_IPV6: 1630 SCA_DPRINTF(SCA_DEBUG_RX, ("Received IP packet\n")); 1631 m->m_pkthdr.rcvif = &scp->sp_if; 1632 m->m_pkthdr.len -= sizeof(struct hdlc_header); 1633 m->m_data += sizeof(struct hdlc_header); 1634 m->m_len -= sizeof(struct hdlc_header); 1635 ifq = &ip6intrq; 1636 schednetisr(NETISR_IPV6); 1637 break; 1638 #endif /* INET6 */ 1639 #ifdef ISO 1640 case HDLC_PROTOCOL_ISO: 1641 if (m->m_pkthdr.len < sizeof(struct hdlc_llc_header)) 1642 goto dropit; 1643 m->m_pkthdr.rcvif = &scp->sp_if; 1644 m->m_pkthdr.len -= sizeof(struct hdlc_llc_header); 1645 m->m_data += sizeof(struct hdlc_llc_header); 1646 m->m_len -= sizeof(struct hdlc_llc_header); 1647 ifq = &clnlintrq; 1648 schednetisr(NETISR_ISO); 1649 break; 1650 #endif /* ISO */ 1651 case CISCO_KEEPALIVE: 1652 SCA_DPRINTF(SCA_DEBUG_CISCO, 1653 ("Received CISCO keepalive packet\n")); 1654 1655 if (len < CISCO_PKT_LEN) { 1656 SCA_DPRINTF(SCA_DEBUG_CISCO, 1657 ("short CISCO packet %d, wanted %d\n", 1658 len, CISCO_PKT_LEN)); 1659 scp->sp_if.if_ierrors++; 1660 goto dropit; 1661 } 1662 1663 m = m_pullup(m, sizeof(struct cisco_pkt)); 1664 if (m == NULL) { 1665 SCA_DPRINTF(SCA_DEBUG_RX, ("RX: no m_pullup!\n")); 1666 return; 1667 } 1668 1669 cisco = (struct cisco_pkt *) 1670 (mtod(m, u_int8_t *) + HDLC_HDRLEN); 1671 m->m_pkthdr.rcvif = &scp->sp_if; 1672 1673 switch (ntohl(cisco->type)) { 1674 case CISCO_ADDR_REQ: 1675 printf("Got CISCO addr_req, ignoring\n"); 1676 scp->sp_if.if_ierrors++; 1677 goto dropit; 1678 1679 case CISCO_ADDR_REPLY: 1680 printf("Got CISCO addr_reply, ignoring\n"); 1681 scp->sp_if.if_ierrors++; 1682 goto dropit; 1683 1684 case CISCO_KEEPALIVE_REQ: 1685 1686 SCA_DPRINTF(SCA_DEBUG_CISCO, 1687 ("Received KA, mseq %d," 1688 " yseq %d, rel 0x%04x, t0" 1689 " %04x, t1 %04x\n", 1690 ntohl(cisco->par1), ntohl(cisco->par2), 1691 ntohs(cisco->rel), ntohs(cisco->time0), 1692 ntohs(cisco->time1))); 1693 1694 scp->cka_lastrx = ntohl(cisco->par1); 1695 scp->cka_lasttx++; 1696 1697 /* 1698 * schedule the transmit right here. 1699 */ 1700 cisco->par2 = cisco->par1; 1701 cisco->par1 = htonl(scp->cka_lasttx); 1702 cisco->time0 = htons((u_int16_t)(t >> 16)); 1703 cisco->time1 = htons((u_int16_t)(t & 0x0000ffff)); 1704 1705 ifq = &scp->linkq; 1706 if (IF_QFULL(ifq)) { 1707 IF_DROP(ifq); 1708 goto dropit; 1709 } 1710 IF_ENQUEUE(ifq, m); 1711 1712 sca_start(&scp->sp_if); 1713 1714 /* since start may have reset this fix */ 1715 if (!scp->sca->sc_usedma) { 1716 scp->sca->scu_set_page(scp->sca, 1717 scp->sp_rxdesc_p); 1718 scp->sca->scu_page_on(scp->sca); 1719 } 1720 return; 1721 default: 1722 SCA_DPRINTF(SCA_DEBUG_CISCO, 1723 ("Unknown CISCO keepalive protocol 0x%04x\n", 1724 ntohl(cisco->type))); 1725 1726 scp->sp_if.if_noproto++; 1727 goto dropit; 1728 } 1729 return; 1730 default: 1731 SCA_DPRINTF(SCA_DEBUG_RX, 1732 ("Unknown/unexpected ethertype 0x%04x\n", 1733 ntohs(hdlc->h_proto))); 1734 scp->sp_if.if_noproto++; 1735 goto dropit; 1736 } 1737 1738 /* queue the packet */ 1739 if (!IF_QFULL(ifq)) { 1740 IF_ENQUEUE(ifq, m); 1741 } else { 1742 IF_DROP(ifq); 1743 scp->sp_if.if_iqdrops++; 1744 goto dropit; 1745 } 1746 return; 1747 dropit: 1748 if (m) 1749 m_freem(m); 1750 return; 1751 } 1752 1753 #if SCA_DEBUG_LEVEL > 0 1754 /* 1755 * do a hex dump of the packet received into descriptor "desc" with 1756 * data buffer "p" 1757 */ 1758 static void 1759 sca_frame_print(sca_port_t *scp, sca_desc_t *desc, u_int8_t *p) 1760 { 1761 int i; 1762 int nothing_yet = 1; 1763 struct sca_softc *sc; 1764 u_int len; 1765 1766 sc = scp->sca; 1767 printf("desc va %p: chainp 0x%x bufp 0x%0x stat 0x%0x len %d\n", 1768 desc, 1769 sca_desc_read_chainp(sc, desc), 1770 sca_desc_read_bufp(sc, desc), 1771 sca_desc_read_stat(sc, desc), 1772 (len = sca_desc_read_buflen(sc, desc))); 1773 1774 for (i = 0 ; i < len && i < 256; i++) { 1775 if (nothing_yet == 1 && 1776 (sc->sc_usedma ? *p 1777 : bus_space_read_1(sc->scu_memt, sc->scu_memh, 1778 sca_page_addr(sc, p))) == 0) { 1779 p++; 1780 continue; 1781 } 1782 nothing_yet = 0; 1783 if (i % 16 == 0) 1784 printf("\n"); 1785 printf("%02x ", 1786 (sc->sc_usedma ? *p 1787 : bus_space_read_1(sc->scu_memt, sc->scu_memh, 1788 sca_page_addr(sc, p)))); 1789 p++; 1790 } 1791 1792 if (i % 16 != 1) 1793 printf("\n"); 1794 } 1795 #endif 1796 1797 /* 1798 * adjust things because we have just read the current starting 1799 * frame 1800 * 1801 * must be called at splnet() 1802 */ 1803 static void 1804 sca_frame_read_done(sca_port_t *scp) 1805 { 1806 u_int16_t edesc_p; 1807 1808 /* update where our indicies are */ 1809 scp->sp_rxend = scp->sp_rxstart; 1810 scp->sp_rxstart = (scp->sp_rxstart + 1) % scp->sp_nrxdesc; 1811 1812 /* update the error [end] descriptor */ 1813 edesc_p = (u_int16_t)scp->sp_rxdesc_p + 1814 (sizeof(sca_desc_t) * scp->sp_rxend); 1815 dmac_write_2(scp, SCA_EDAL0, edesc_p); 1816 } 1817 1818 /* 1819 * set a port to the "up" state 1820 */ 1821 static void 1822 sca_port_up(sca_port_t *scp) 1823 { 1824 struct sca_softc *sc = scp->sca; 1825 struct timeval now; 1826 #if 0 1827 u_int8_t ier0, ier1; 1828 #endif 1829 1830 /* 1831 * reset things 1832 */ 1833 #if 0 1834 msci_write_1(scp, SCA_CMD0, SCA_CMD_TXRESET); 1835 msci_write_1(scp, SCA_CMD0, SCA_CMD_RXRESET); 1836 #endif 1837 /* 1838 * clear in-use flag 1839 */ 1840 scp->sp_if.if_flags &= ~IFF_OACTIVE; 1841 scp->sp_if.if_flags |= IFF_RUNNING; 1842 1843 /* 1844 * raise DTR 1845 */ 1846 sc->sc_dtr_callback(sc->sc_aux, scp->sp_port, 1); 1847 1848 /* 1849 * raise RTS 1850 */ 1851 msci_write_1(scp, SCA_CTL0, 1852 (msci_read_1(scp, SCA_CTL0) & ~SCA_CTL_RTS_MASK) 1853 | SCA_CTL_RTS_HIGH); 1854 1855 #if 0 1856 /* 1857 * enable interrupts (no timer IER2) 1858 */ 1859 ier0 = SCA_IER0_MSCI_RXRDY0 | SCA_IER0_MSCI_TXRDY0 1860 | SCA_IER0_MSCI_RXINT0 | SCA_IER0_MSCI_TXINT0; 1861 ier1 = SCA_IER1_DMAC_RX0A | SCA_IER1_DMAC_RX0B 1862 | SCA_IER1_DMAC_TX0A | SCA_IER1_DMAC_TX0B; 1863 if (scp->sp_port == 1) { 1864 ier0 <<= 4; 1865 ier1 <<= 4; 1866 } 1867 sca_write_1(sc, SCA_IER0, sca_read_1(sc, SCA_IER0) | ier0); 1868 sca_write_1(sc, SCA_IER1, sca_read_1(sc, SCA_IER1) | ier1); 1869 #else 1870 if (scp->sp_port == 0) { 1871 sca_write_1(sc, SCA_IER0, sca_read_1(sc, SCA_IER0) | 0x0f); 1872 sca_write_1(sc, SCA_IER1, sca_read_1(sc, SCA_IER1) | 0x0f); 1873 } else { 1874 sca_write_1(sc, SCA_IER0, sca_read_1(sc, SCA_IER0) | 0xf0); 1875 sca_write_1(sc, SCA_IER1, sca_read_1(sc, SCA_IER1) | 0xf0); 1876 } 1877 #endif 1878 1879 /* 1880 * enable transmit and receive 1881 */ 1882 msci_write_1(scp, SCA_CMD0, SCA_CMD_TXENABLE); 1883 msci_write_1(scp, SCA_CMD0, SCA_CMD_RXENABLE); 1884 1885 /* 1886 * reset internal state 1887 */ 1888 scp->sp_txinuse = 0; 1889 scp->sp_txcur = 0; 1890 getmicrotime(&now); 1891 scp->cka_lasttx = now.tv_usec; 1892 scp->cka_lastrx = 0; 1893 } 1894 1895 /* 1896 * set a port to the "down" state 1897 */ 1898 static void 1899 sca_port_down(sca_port_t *scp) 1900 { 1901 struct sca_softc *sc = scp->sca; 1902 #if 0 1903 u_int8_t ier0, ier1; 1904 #endif 1905 1906 /* 1907 * lower DTR 1908 */ 1909 sc->sc_dtr_callback(sc->sc_aux, scp->sp_port, 0); 1910 1911 /* 1912 * lower RTS 1913 */ 1914 msci_write_1(scp, SCA_CTL0, 1915 (msci_read_1(scp, SCA_CTL0) & ~SCA_CTL_RTS_MASK) 1916 | SCA_CTL_RTS_LOW); 1917 1918 /* 1919 * disable interrupts 1920 */ 1921 #if 0 1922 ier0 = SCA_IER0_MSCI_RXRDY0 | SCA_IER0_MSCI_TXRDY0 1923 | SCA_IER0_MSCI_RXINT0 | SCA_IER0_MSCI_TXINT0; 1924 ier1 = SCA_IER1_DMAC_RX0A | SCA_IER1_DMAC_RX0B 1925 | SCA_IER1_DMAC_TX0A | SCA_IER1_DMAC_TX0B; 1926 if (scp->sp_port == 1) { 1927 ier0 <<= 4; 1928 ier1 <<= 4; 1929 } 1930 sca_write_1(sc, SCA_IER0, sca_read_1(sc, SCA_IER0) & ~ier0); 1931 sca_write_1(sc, SCA_IER1, sca_read_1(sc, SCA_IER1) & ~ier1); 1932 #else 1933 if (scp->sp_port == 0) { 1934 sca_write_1(sc, SCA_IER0, sca_read_1(sc, SCA_IER0) & 0xf0); 1935 sca_write_1(sc, SCA_IER1, sca_read_1(sc, SCA_IER1) & 0xf0); 1936 } else { 1937 sca_write_1(sc, SCA_IER0, sca_read_1(sc, SCA_IER0) & 0x0f); 1938 sca_write_1(sc, SCA_IER1, sca_read_1(sc, SCA_IER1) & 0x0f); 1939 } 1940 #endif 1941 1942 /* 1943 * disable transmit and receive 1944 */ 1945 msci_write_1(scp, SCA_CMD0, SCA_CMD_RXDISABLE); 1946 msci_write_1(scp, SCA_CMD0, SCA_CMD_TXDISABLE); 1947 1948 /* 1949 * no, we're not in use anymore 1950 */ 1951 scp->sp_if.if_flags &= ~(IFF_OACTIVE|IFF_RUNNING); 1952 } 1953 1954 /* 1955 * disable all DMA and interrupts for all ports at once. 1956 */ 1957 void 1958 sca_shutdown(struct sca_softc *sca) 1959 { 1960 /* 1961 * disable DMA and interrupts 1962 */ 1963 sca_write_1(sca, SCA_DMER, 0); 1964 sca_write_1(sca, SCA_IER0, 0); 1965 sca_write_1(sca, SCA_IER1, 0); 1966 } 1967 1968 /* 1969 * If there are packets to transmit, start the transmit DMA logic. 1970 */ 1971 static void 1972 sca_port_starttx(sca_port_t *scp) 1973 { 1974 u_int32_t startdesc_p, enddesc_p; 1975 int enddesc; 1976 1977 SCA_DPRINTF(SCA_DEBUG_TX, ("TX: starttx\n")); 1978 1979 if (((scp->sp_if.if_flags & IFF_OACTIVE) == IFF_OACTIVE) 1980 || scp->sp_txinuse == 0) 1981 return; 1982 1983 SCA_DPRINTF(SCA_DEBUG_TX, ("TX: setting oactive\n")); 1984 1985 scp->sp_if.if_flags |= IFF_OACTIVE; 1986 1987 /* 1988 * We have something to do, since we have at least one packet 1989 * waiting, and we are not already marked as active. 1990 */ 1991 enddesc = (scp->sp_txcur + 1) % scp->sp_ntxdesc; 1992 startdesc_p = scp->sp_txdesc_p; 1993 enddesc_p = scp->sp_txdesc_p + sizeof(sca_desc_t) * enddesc; 1994 1995 SCA_DPRINTF(SCA_DEBUG_TX, ("TX: start %x end %x\n", 1996 startdesc_p, enddesc_p)); 1997 1998 dmac_write_2(scp, SCA_EDAL1, (u_int16_t)(enddesc_p & 0x0000ffff)); 1999 dmac_write_2(scp, SCA_CDAL1, 2000 (u_int16_t)(startdesc_p & 0x0000ffff)); 2001 2002 /* 2003 * enable the DMA 2004 */ 2005 dmac_write_1(scp, SCA_DSR1, SCA_DSR_DE); 2006 } 2007 2008 /* 2009 * allocate an mbuf at least long enough to hold "len" bytes. 2010 * If "p" is non-NULL, copy "len" bytes from it into the new mbuf, 2011 * otherwise let the caller handle copying the data in. 2012 */ 2013 static struct mbuf * 2014 sca_mbuf_alloc(struct sca_softc *sc, caddr_t p, u_int len) 2015 { 2016 struct mbuf *m; 2017 2018 /* 2019 * allocate an mbuf and copy the important bits of data 2020 * into it. If the packet won't fit in the header, 2021 * allocate a cluster for it and store it there. 2022 */ 2023 MGETHDR(m, M_DONTWAIT, MT_DATA); 2024 if (m == NULL) 2025 return NULL; 2026 if (len > MHLEN) { 2027 if (len > MCLBYTES) { 2028 m_freem(m); 2029 return NULL; 2030 } 2031 MCLGET(m, M_DONTWAIT); 2032 if ((m->m_flags & M_EXT) == 0) { 2033 m_freem(m); 2034 return NULL; 2035 } 2036 } 2037 if (p != NULL) { 2038 /* XXX do we need to sync here? */ 2039 if (sc->sc_usedma) 2040 memcpy(mtod(m, caddr_t), p, len); 2041 else 2042 bus_space_read_region_1(sc->scu_memt, sc->scu_memh, 2043 sca_page_addr(sc, p), mtod(m, u_int8_t *), len); 2044 } 2045 m->m_len = len; 2046 m->m_pkthdr.len = len; 2047 2048 return (m); 2049 } 2050 2051 /* 2052 * get the base clock 2053 */ 2054 void 2055 sca_get_base_clock(struct sca_softc *sc) 2056 { 2057 struct timeval btv, ctv, dtv; 2058 u_int64_t bcnt; 2059 u_int32_t cnt; 2060 u_int16_t subcnt; 2061 2062 /* disable the timer, set prescale to 0 */ 2063 sca_write_1(sc, SCA_TCSR0, 0); 2064 sca_write_1(sc, SCA_TEPR0, 0); 2065 2066 /* reset the counter */ 2067 (void)sca_read_1(sc, SCA_TCSR0); 2068 subcnt = sca_read_2(sc, SCA_TCNTL0); 2069 2070 /* count to max */ 2071 sca_write_2(sc, SCA_TCONRL0, 0xffff); 2072 2073 cnt = 0; 2074 microtime(&btv); 2075 /* start the timer -- no interrupt enable */ 2076 sca_write_1(sc, SCA_TCSR0, SCA_TCSR_TME); 2077 for (;;) { 2078 microtime(&ctv); 2079 2080 /* end around 3/4 of a second */ 2081 timersub(&ctv, &btv, &dtv); 2082 if (dtv.tv_usec >= 750000) 2083 break; 2084 2085 /* spin */ 2086 while (!(sca_read_1(sc, SCA_TCSR0) & SCA_TCSR_CMF)) 2087 ; 2088 /* reset the timer */ 2089 (void)sca_read_2(sc, SCA_TCNTL0); 2090 cnt++; 2091 } 2092 2093 /* stop the timer */ 2094 sca_write_1(sc, SCA_TCSR0, 0); 2095 2096 subcnt = sca_read_2(sc, SCA_TCNTL0); 2097 /* add the slop in and get the total timer ticks */ 2098 cnt = (cnt << 16) | subcnt; 2099 2100 /* cnt is 1/8 the actual time */ 2101 bcnt = cnt * 8; 2102 /* make it proportional to 3/4 of a second */ 2103 bcnt *= (u_int64_t)750000; 2104 bcnt /= (u_int64_t)dtv.tv_usec; 2105 cnt = bcnt; 2106 2107 /* make it Hz */ 2108 cnt *= 4; 2109 cnt /= 3; 2110 2111 SCA_DPRINTF(SCA_DEBUG_CLOCK, 2112 ("sca: unadjusted base %lu Hz\n", (u_long)cnt)); 2113 2114 /* 2115 * round to the nearest 200 -- this allows for +-3 ticks error 2116 */ 2117 sc->sc_baseclock = ((cnt + 100) / 200) * 200; 2118 } 2119 2120 /* 2121 * print the information about the clock on the ports 2122 */ 2123 void 2124 sca_print_clock_info(struct sca_softc *sc) 2125 { 2126 struct sca_port *scp; 2127 u_int32_t mhz, div; 2128 int i; 2129 2130 printf("%s: base clock %d Hz\n", sc->sc_parent->dv_xname, 2131 sc->sc_baseclock); 2132 2133 /* print the information about the port clock selection */ 2134 for (i = 0; i < sc->sc_numports; i++) { 2135 scp = &sc->sc_ports[i]; 2136 mhz = sc->sc_baseclock / (scp->sp_tmc ? scp->sp_tmc : 256); 2137 div = scp->sp_rxs & SCA_RXS_DIV_MASK; 2138 2139 printf("%s: rx clock: ", scp->sp_if.if_xname); 2140 switch (scp->sp_rxs & SCA_RXS_CLK_MASK) { 2141 case SCA_RXS_CLK_LINE: 2142 printf("line"); 2143 break; 2144 case SCA_RXS_CLK_LINE_SN: 2145 printf("line with noise suppression"); 2146 break; 2147 case SCA_RXS_CLK_INTERNAL: 2148 printf("internal %d Hz", (mhz >> div)); 2149 break; 2150 case SCA_RXS_CLK_ADPLL_OUT: 2151 printf("adpll using internal %d Hz", (mhz >> div)); 2152 break; 2153 case SCA_RXS_CLK_ADPLL_IN: 2154 printf("adpll using line clock"); 2155 break; 2156 } 2157 printf(" tx clock: "); 2158 div = scp->sp_txs & SCA_TXS_DIV_MASK; 2159 switch (scp->sp_txs & SCA_TXS_CLK_MASK) { 2160 case SCA_TXS_CLK_LINE: 2161 printf("line\n"); 2162 break; 2163 case SCA_TXS_CLK_INTERNAL: 2164 printf("internal %d Hz\n", (mhz >> div)); 2165 break; 2166 case SCA_TXS_CLK_RXCLK: 2167 printf("rxclock\n"); 2168 break; 2169 } 2170 if (scp->sp_eclock) 2171 printf("%s: outputting line clock\n", 2172 scp->sp_if.if_xname); 2173 } 2174 } 2175
Cache object: d880accf1746bf1e35d85a7e053a97f2
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