Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/hd64570.h
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1 /* 2 * Copyright (c) 1995 John Hay. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. All advertising materials mentioning features or use of this software 13 * must display the following acknowledgement: 14 * This product includes software developed by [your name] 15 * and [any other names deserving credit ] 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY [your name] AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 #ifndef _HD64570_H_ 35 #define _HD64570_H_ 36 37 typedef struct msci_channel 38 { 39 union 40 { 41 unsigned short us_trb; /* rw */ 42 struct 43 { 44 unsigned char uc_trbl; 45 unsigned char uc_trbh; 46 }uc_trb; 47 }u_trb; 48 unsigned char st0; /* ro */ 49 unsigned char st1; /* rw */ 50 unsigned char st2; /* rw */ 51 unsigned char st3; /* ro */ 52 unsigned char fst; /* rw */ 53 unsigned char unused0; 54 unsigned char ie0; /* rw */ 55 unsigned char ie1; /* rw */ 56 unsigned char ie2; /* rw */ 57 unsigned char fie; /* rw */ 58 unsigned char cmd; /* wo */ 59 unsigned char unused1; 60 unsigned char md0; /* rw */ 61 unsigned char md1; /* rw */ 62 unsigned char md2; /* rw */ 63 unsigned char ctl; /* rw */ 64 unsigned char sa0; /* rw */ 65 unsigned char sa1; /* rw */ 66 unsigned char idl; /* rw */ 67 unsigned char tmc; /* rw */ 68 unsigned char rxs; /* rw */ 69 unsigned char txs; /* rw */ 70 unsigned char trc0; /* rw */ 71 unsigned char trc1; /* rw */ 72 unsigned char rrc; /* rw */ 73 unsigned char unused2; 74 unsigned char cst0; /* rw */ 75 unsigned char cst1; /* rw */ 76 unsigned char unused3[2]; 77 }msci_channel; 78 79 #define trb u_trb.us_trb 80 #define trbl u_trb.uc_trb.uc_trbl 81 #define trbh u_trb.uc_trb.uc_trbh 82 83 typedef struct timer_channel 84 { 85 unsigned short tcnt; /* rw */ 86 unsigned short tconr; /* wo */ 87 unsigned char tcsr; /* rw */ 88 unsigned char tepr; /* rw */ 89 unsigned char unused[2]; 90 }timer_channel; 91 92 typedef struct dmac_channel 93 { 94 unsigned short dar; /* rw */ 95 unsigned char darb; /* rw */ 96 unsigned char unused0; 97 unsigned short sar; /* rw On odd numbered dmacs (tx) only */ 98 unsigned char sarb; /* rw */ 99 #define cpb sarb 100 unsigned char unused1; 101 unsigned short cda; /* rw */ 102 unsigned short eda; /* rw */ 103 unsigned short bfl; /* rw On even numbered dmacs (rx) only */ 104 unsigned short bcr; /* rw */ 105 unsigned char dsr; /* rw */ 106 unsigned char dmr; /* rw */ 107 unsigned char unused2; 108 unsigned char fct; /* rw */ 109 unsigned char dir; /* rw */ 110 unsigned char dcr; /* rw */ 111 unsigned char unused3[10]; 112 }dmac_channel; 113 114 /* x is the channel number. rx channels are even numbered and tx, odd. */ 115 #define DMAC_RXCH(x) ((x*2) + 0) 116 #define DMAC_TXCH(x) ((x*2) + 1) 117 118 typedef struct sca_regs 119 { 120 unsigned char lpr; /* rw */ 121 unsigned char unused0; /* -- */ 122 /* Wait system */ 123 unsigned char pabr0; /* rw */ 124 unsigned char pabr1; /* rw */ 125 unsigned char wcrl; /* rw */ 126 unsigned char wcrm; /* rw */ 127 unsigned char wcrh; /* rw */ 128 unsigned char unused1; 129 /* DMAC */ 130 unsigned char pcr; /* rw */ 131 unsigned char dmer; /* rw */ 132 unsigned char unused2[6]; 133 /* Interrupt */ 134 unsigned char isr0; /* ro */ 135 unsigned char isr1; /* ro */ 136 unsigned char isr2; /* ro */ 137 unsigned char unused3; 138 unsigned char ier0; /* rw */ 139 unsigned char ier1; /* rw */ 140 unsigned char ier2; /* rw */ 141 unsigned char unused4; 142 unsigned char itcr; /* rw */ 143 unsigned char unused5; 144 unsigned char ivr; /* rw */ 145 unsigned char unused6; 146 unsigned char imvr; /* rw */ 147 unsigned char unused7[3]; 148 /* MSCI Channel 0 */ 149 msci_channel msci[2]; 150 timer_channel timer[4]; 151 dmac_channel dmac[4]; 152 }sca_regs; 153 154 #define SCA_CMD_TXRESET 0x01 155 #define SCA_CMD_TXENABLE 0x02 156 #define SCA_CMD_TXDISABLE 0x03 157 #define SCA_CMD_TXCRCINIT 0x04 158 #define SCA_CMD_TXCRCEXCL 0x05 159 #define SCA_CMS_TXEOM 0x06 160 #define SCA_CMD_TXABORT 0x07 161 #define SCA_CMD_MPON 0x08 162 #define SCA_CMD_TXBCLEAR 0x09 163 164 #define SCA_CMD_RXRESET 0x11 165 #define SCA_CMD_RXENABLE 0x12 166 #define SCA_CMD_RXDISABLE 0x13 167 #define SCA_CMD_RXCRCINIT 0x14 168 #define SCA_CMD_RXMSGREJ 0x15 169 #define SCA_CMD_MPSEARCH 0x16 170 #define SCA_CMD_RXCRCEXCL 0x17 171 #define SCA_CMD_RXCRCCALC 0x18 172 173 #define SCA_CMD_NOP 0x00 174 #define SCA_CMD_RESET 0x21 175 #define SCA_CMD_SEARCH 0x31 176 177 #define SCA_MD0_CRC_1 0x01 178 #define SCA_MD0_CRC_CCITT 0x02 179 #define SCA_MD0_CRC_ENABLE 0x04 180 #define SCA_MD0_AUTO_ENABLE 0x10 181 #define SCA_MD0_MODE_ASYNC 0x00 182 #define SCA_MD0_MODE_BYTESYNC1 0x20 183 #define SCA_MD0_MODE_BISYNC 0x40 184 #define SCA_MD0_MODE_BYTESYNC2 0x60 185 #define SCA_MD0_MODE_HDLC 0x80 186 187 #define SCA_MD1_NOADDRCHK 0x00 188 #define SCA_MD1_SNGLADDR1 0x40 189 #define SCA_MD1_SNGLADDR2 0x80 190 #define SCA_MD1_DUALADDR 0xC0 191 192 #define SCA_MD2_DUPLEX 0x00 193 #define SCA_MD2_ECHO 0x01 194 #define SCA_MD2_LOOPBACK 0x03 195 #define SCA_MD2_ADPLLx8 0x00 196 #define SCA_MD2_ADPLLx16 0x08 197 #define SCA_MD2_ADPLLx32 0x10 198 #define SCA_MD2_NRZ 0x00 199 #define SCA_MD2_NRZI 0x20 200 #define SCA_MD2_MANCHESTER 0x80 201 #define SCA_MD2_FM0 0xC0 202 #define SCA_MD2_FM1 0xA0 203 204 #define SCA_CTL_RTS 0x01 205 #define SCA_CTL_IDLPAT 0x10 206 #define SCA_CTL_UDRNC 0x20 207 208 #define SCA_RXS_DIV_MASK 0x0F 209 #define SCA_RXS_DIV1 0x00 210 #define SCA_RXS_DIV2 0x01 211 #define SCA_RXS_DIV4 0x02 212 #define SCA_RXS_DIV8 0x03 213 #define SCA_RXS_DIV16 0x04 214 #define SCA_RXS_DIV32 0x05 215 #define SCA_RXS_DIV64 0x06 216 #define SCA_RXS_DIV128 0x07 217 #define SCA_RXS_DIV256 0x08 218 #define SCA_RXS_DIV512 0x09 219 #define SCA_RXS_CLK_RXC0 0x00 220 #define SCA_RXS_CLK_RXC1 0x20 221 #define SCA_RXS_CLK_INT 0x40 222 #define SCA_RXS_CLK_ADPLL_OUT 0x60 223 #define SCA_RXS_CLK_ADPLL_IN 0x70 224 225 #define SCA_TXS_DIV_MASK 0x0F 226 #define SCA_TXS_DIV1 0x00 227 #define SCA_TXS_DIV2 0x01 228 #define SCA_TXS_DIV4 0x02 229 #define SCA_TXS_DIV8 0x03 230 #define SCA_TXS_DIV16 0x04 231 #define SCA_TXS_DIV32 0x05 232 #define SCA_TXS_DIV64 0x06 233 #define SCA_TXS_DIV128 0x07 234 #define SCA_TXS_DIV256 0x08 235 #define SCA_TXS_DIV512 0x09 236 #define SCA_TXS_CLK_TXC 0x00 237 #define SCA_TXS_CLK_INT 0x40 238 #define SCA_TXS_CLK_RX 0x60 239 240 #define SCA_ST0_RXRDY 0x01 241 #define SCA_ST0_TXRDY 0x02 242 #define SCA_ST0_RXINT 0x40 243 #define SCA_ST0_TXINT 0x80 244 245 #define SCA_ST1_IDLST 0x01 246 #define SCA_ST1_ABTST 0x02 247 #define SCA_ST1_DCDCHG 0x04 248 #define SCA_ST1_CTSCHG 0x08 249 #define SCA_ST1_FLAG 0x10 250 #define SCA_ST1_TXIDL 0x40 251 #define SCA_ST1_UDRN 0x80 252 253 /* ST2 and FST look the same */ 254 #define SCA_FST_CRCERR 0x04 255 #define SCA_FST_OVRN 0x08 256 #define SCA_FST_RESFRM 0x10 257 #define SCA_FST_ABRT 0x20 258 #define SCA_FST_SHRT 0x40 259 #define SCA_FST_EOM 0x80 260 261 #define SCA_ST3_RXENA 0x01 262 #define SCA_ST3_TXENA 0x02 263 #define SCA_ST3_DCD 0x04 264 #define SCA_ST3_CTS 0x08 265 #define SCA_ST3_ADPLLSRCH 0x10 266 #define SCA_ST3_TXDATA 0x20 267 268 #define SCA_FIE_EOMFE 0x80 269 270 #define SCA_IE0_RXRDY 0x01 271 #define SCA_IE0_TXRDY 0x02 272 #define SCA_IE0_RXINT 0x40 273 #define SCA_IE0_TXINT 0x80 274 275 #define SCA_IE1_IDLDE 0x01 276 #define SCA_IE1_ABTDE 0x02 277 #define SCA_IE1_DCD 0x04 278 #define SCA_IE1_CTS 0x08 279 #define SCA_IE1_FLAG 0x10 280 #define SCA_IE1_IDL 0x40 281 #define SCA_IE1_UDRN 0x80 282 283 #define SCA_IE2_CRCERR 0x04 284 #define SCA_IE2_OVRN 0x08 285 #define SCA_IE2_RESFRM 0x10 286 #define SCA_IE2_ABRT 0x20 287 #define SCA_IE2_SHRT 0x40 288 #define SCA_IE2_EOM 0x80 289 290 /* This is for RRC, TRC0 and TRC1. */ 291 #define SCA_RCR_MASK 0x1F 292 293 #define SCA_IE1_ 294 295 #define SCA_IV_CHAN0 0x00 296 #define SCA_IV_CHAN1 0x20 297 298 #define SCA_IV_RXRDY 0x04 299 #define SCA_IV_TXRDY 0x06 300 #define SCA_IV_RXINT 0x08 301 #define SCA_IV_TXINT 0x0A 302 303 #define SCA_IV_DMACH0 0x00 304 #define SCA_IV_DMACH1 0x08 305 #define SCA_IV_DMACH2 0x20 306 #define SCA_IV_DMACH3 0x28 307 308 #define SCA_IV_DMIA 0x14 309 #define SCA_IV_DMIB 0x16 310 311 #define SCA_IV_TIMER0 0x1C 312 #define SCA_IV_TIMER1 0x1E 313 #define SCA_IV_TIMER2 0x3C 314 #define SCA_IV_TIMER3 0x3E 315 316 /* 317 * DMA registers 318 */ 319 #define SCA_DSR_EOT 0x80 320 #define SCA_DSR_EOM 0x40 321 #define SCA_DSR_BOF 0x20 322 #define SCA_DSR_COF 0x10 323 #define SCA_DSR_DE 0x02 324 #define SCA_DSR_DWE 0x01 325 326 #define SCA_DMR_TMOD 0x10 327 #define SCA_DMR_NF 0x04 328 #define SCA_DMR_CNTE 0x02 329 330 #define SCA_DMER_EN 0x80 331 332 #define SCA_DCR_ABRT 0x01 333 #define SCA_DCR_FCCLR 0x02 /* Clear frame end intr counter */ 334 335 #define SCA_DIR_EOT 0x80 336 #define SCA_DIR_EOM 0x40 337 #define SCA_DIR_BOF 0x20 338 #define SCA_DIR_COF 0x10 339 340 #define SCA_PCR_BRC 0x10 341 #define SCA_PCR_CCC 0x08 342 #define SCA_PCR_PR2 0x04 343 #define SCA_PCR_PR1 0x02 344 #define SCA_PCR_PR0 0x01 345 346 typedef struct sca_descriptor 347 { 348 unsigned short cp; 349 unsigned short bp; 350 unsigned char bpb; 351 unsigned char unused0; 352 unsigned short len; 353 unsigned char stat; 354 unsigned char unused1; 355 }sca_descriptor; 356 357 #define SCA_DESC_EOT 0x01 358 #define SCA_DESC_CRC 0x04 359 #define SCA_DESC_OVRN 0x08 360 #define SCA_DESC_RESD 0x10 361 #define SCA_DESC_ABORT 0x20 362 #define SCA_DESC_SHRTFRM 0x40 363 #define SCA_DESC_EOM 0x80 364 #define SCA_DESC_ERRORS 0x7C 365 366 /* 367 *************************************************************************** 368 ** END 369 *************************************************************************** 370 **/ 371 #endif /* _HD64570_H_ */ 372
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