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sys/dev/ic/hme.c
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1 /* $NetBSD: hme.c,v 1.55 2006/11/24 19:46:59 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * HME Ethernet module driver. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: hme.c,v 1.55 2006/11/24 19:46:59 christos Exp $"); 45 46 /* #define HMEDEBUG */ 47 48 #include "opt_inet.h" 49 #include "bpfilter.h" 50 #include "rnd.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/mbuf.h> 56 #include <sys/syslog.h> 57 #include <sys/socket.h> 58 #include <sys/device.h> 59 #include <sys/malloc.h> 60 #include <sys/ioctl.h> 61 #include <sys/errno.h> 62 #if NRND > 0 63 #include <sys/rnd.h> 64 #endif 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_ether.h> 69 #include <net/if_media.h> 70 71 #ifdef INET 72 #include <netinet/in.h> 73 #include <netinet/if_inarp.h> 74 #include <netinet/in_systm.h> 75 #include <netinet/in_var.h> 76 #include <netinet/ip.h> 77 #include <netinet/tcp.h> 78 #include <netinet/udp.h> 79 #endif 80 81 82 #if NBPFILTER > 0 83 #include <net/bpf.h> 84 #include <net/bpfdesc.h> 85 #endif 86 87 #include <dev/mii/mii.h> 88 #include <dev/mii/miivar.h> 89 90 #include <machine/bus.h> 91 92 #include <dev/ic/hmereg.h> 93 #include <dev/ic/hmevar.h> 94 95 void hme_start(struct ifnet *); 96 void hme_stop(struct hme_softc *); 97 int hme_ioctl(struct ifnet *, u_long, caddr_t); 98 void hme_tick(void *); 99 void hme_watchdog(struct ifnet *); 100 void hme_shutdown(void *); 101 void hme_init(struct hme_softc *); 102 void hme_meminit(struct hme_softc *); 103 void hme_mifinit(struct hme_softc *); 104 void hme_reset(struct hme_softc *); 105 void hme_setladrf(struct hme_softc *); 106 107 /* MII methods & callbacks */ 108 static int hme_mii_readreg(struct device *, int, int); 109 static void hme_mii_writereg(struct device *, int, int, int); 110 static void hme_mii_statchg(struct device *); 111 112 int hme_mediachange(struct ifnet *); 113 void hme_mediastatus(struct ifnet *, struct ifmediareq *); 114 115 struct mbuf *hme_get(struct hme_softc *, int, uint32_t); 116 int hme_put(struct hme_softc *, int, struct mbuf *); 117 void hme_read(struct hme_softc *, int, uint32_t); 118 int hme_eint(struct hme_softc *, u_int); 119 int hme_rint(struct hme_softc *); 120 int hme_tint(struct hme_softc *); 121 122 static int ether_cmp(u_char *, u_char *); 123 124 /* Default buffer copy routines */ 125 void hme_copytobuf_contig(struct hme_softc *, void *, int, int); 126 void hme_copyfrombuf_contig(struct hme_softc *, void *, int, int); 127 void hme_zerobuf_contig(struct hme_softc *, int, int); 128 129 130 void 131 hme_config(sc) 132 struct hme_softc *sc; 133 { 134 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 135 struct mii_data *mii = &sc->sc_mii; 136 struct mii_softc *child; 137 bus_dma_tag_t dmatag = sc->sc_dmatag; 138 bus_dma_segment_t seg; 139 bus_size_t size; 140 int rseg, error; 141 142 /* 143 * HME common initialization. 144 * 145 * hme_softc fields that must be initialized by the front-end: 146 * 147 * the bus tag: 148 * sc_bustag 149 * 150 * the DMA bus tag: 151 * sc_dmatag 152 * 153 * the bus handles: 154 * sc_seb (Shared Ethernet Block registers) 155 * sc_erx (Receiver Unit registers) 156 * sc_etx (Transmitter Unit registers) 157 * sc_mac (MAC registers) 158 * sc_mif (Management Interface registers) 159 * 160 * the maximum bus burst size: 161 * sc_burst 162 * 163 * (notyet:DMA capable memory for the ring descriptors & packet buffers: 164 * rb_membase, rb_dmabase) 165 * 166 * the local Ethernet address: 167 * sc_enaddr 168 * 169 */ 170 171 /* Make sure the chip is stopped. */ 172 hme_stop(sc); 173 174 175 /* 176 * Allocate descriptors and buffers 177 * XXX - do all this differently.. and more configurably, 178 * eg. use things as `dma_load_mbuf()' on transmit, 179 * and a pool of `EXTMEM' mbufs (with buffers DMA-mapped 180 * all the time) on the receiver side. 181 * 182 * Note: receive buffers must be 64-byte aligned. 183 * Also, apparently, the buffers must extend to a DMA burst 184 * boundary beyond the maximum packet size. 185 */ 186 #define _HME_NDESC 128 187 #define _HME_BUFSZ 1600 188 189 /* Note: the # of descriptors must be a multiple of 16 */ 190 sc->sc_rb.rb_ntbuf = _HME_NDESC; 191 sc->sc_rb.rb_nrbuf = _HME_NDESC; 192 193 /* 194 * Allocate DMA capable memory 195 * Buffer descriptors must be aligned on a 2048 byte boundary; 196 * take this into account when calculating the size. Note that 197 * the maximum number of descriptors (256) occupies 2048 bytes, 198 * so we allocate that much regardless of _HME_NDESC. 199 */ 200 size = 2048 + /* TX descriptors */ 201 2048 + /* RX descriptors */ 202 sc->sc_rb.rb_ntbuf * _HME_BUFSZ + /* TX buffers */ 203 sc->sc_rb.rb_nrbuf * _HME_BUFSZ; /* RX buffers */ 204 205 /* Allocate DMA buffer */ 206 if ((error = bus_dmamem_alloc(dmatag, size, 207 2048, 0, 208 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 209 printf("%s: DMA buffer alloc error %d\n", 210 sc->sc_dev.dv_xname, error); 211 return; 212 } 213 214 /* Map DMA memory in CPU addressable space */ 215 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size, 216 &sc->sc_rb.rb_membase, 217 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 218 printf("%s: DMA buffer map error %d\n", 219 sc->sc_dev.dv_xname, error); 220 bus_dmamap_unload(dmatag, sc->sc_dmamap); 221 bus_dmamem_free(dmatag, &seg, rseg); 222 return; 223 } 224 225 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 226 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 227 printf("%s: DMA map create error %d\n", 228 sc->sc_dev.dv_xname, error); 229 return; 230 } 231 232 /* Load the buffer */ 233 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 234 sc->sc_rb.rb_membase, size, NULL, 235 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 236 printf("%s: DMA buffer map load error %d\n", 237 sc->sc_dev.dv_xname, error); 238 bus_dmamem_free(dmatag, &seg, rseg); 239 return; 240 } 241 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 242 243 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 244 ether_sprintf(sc->sc_enaddr)); 245 246 /* Initialize ifnet structure. */ 247 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 248 ifp->if_softc = sc; 249 ifp->if_start = hme_start; 250 ifp->if_ioctl = hme_ioctl; 251 ifp->if_watchdog = hme_watchdog; 252 ifp->if_flags = 253 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 254 sc->sc_if_flags = ifp->if_flags; 255 ifp->if_capabilities |= 256 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 257 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 258 IFQ_SET_READY(&ifp->if_snd); 259 260 /* Initialize ifmedia structures and MII info */ 261 mii->mii_ifp = ifp; 262 mii->mii_readreg = hme_mii_readreg; 263 mii->mii_writereg = hme_mii_writereg; 264 mii->mii_statchg = hme_mii_statchg; 265 266 ifmedia_init(&mii->mii_media, 0, hme_mediachange, hme_mediastatus); 267 268 hme_mifinit(sc); 269 270 mii_attach(&sc->sc_dev, mii, 0xffffffff, 271 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 272 273 child = LIST_FIRST(&mii->mii_phys); 274 if (child == NULL) { 275 /* No PHY attached */ 276 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 277 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 278 } else { 279 /* 280 * Walk along the list of attached MII devices and 281 * establish an `MII instance' to `phy number' 282 * mapping. We'll use this mapping in media change 283 * requests to determine which phy to use to program 284 * the MIF configuration register. 285 */ 286 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 287 /* 288 * Note: we support just two PHYs: the built-in 289 * internal device and an external on the MII 290 * connector. 291 */ 292 if (child->mii_phy > 1 || child->mii_inst > 1) { 293 printf("%s: cannot accommodate MII device %s" 294 " at phy %d, instance %d\n", 295 sc->sc_dev.dv_xname, 296 child->mii_dev.dv_xname, 297 child->mii_phy, child->mii_inst); 298 continue; 299 } 300 301 sc->sc_phys[child->mii_inst] = child->mii_phy; 302 } 303 304 /* 305 * XXX - we can really do the following ONLY if the 306 * phy indeed has the auto negotiation capability!! 307 */ 308 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 309 } 310 311 /* claim 802.1q capability */ 312 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 313 314 /* Attach the interface. */ 315 if_attach(ifp); 316 ether_ifattach(ifp, sc->sc_enaddr); 317 318 sc->sc_sh = shutdownhook_establish(hme_shutdown, sc); 319 if (sc->sc_sh == NULL) 320 panic("hme_config: can't establish shutdownhook"); 321 322 #if NRND > 0 323 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 324 RND_TYPE_NET, 0); 325 #endif 326 327 callout_init(&sc->sc_tick_ch); 328 } 329 330 void 331 hme_tick(arg) 332 void *arg; 333 { 334 struct hme_softc *sc = arg; 335 int s; 336 337 s = splnet(); 338 mii_tick(&sc->sc_mii); 339 splx(s); 340 341 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 342 } 343 344 void 345 hme_reset(sc) 346 struct hme_softc *sc; 347 { 348 int s; 349 350 s = splnet(); 351 hme_init(sc); 352 splx(s); 353 } 354 355 void 356 hme_stop(sc) 357 struct hme_softc *sc; 358 { 359 bus_space_tag_t t = sc->sc_bustag; 360 bus_space_handle_t seb = sc->sc_seb; 361 int n; 362 363 callout_stop(&sc->sc_tick_ch); 364 mii_down(&sc->sc_mii); 365 366 /* Mask all interrupts */ 367 bus_space_write_4(t, seb, HME_SEBI_IMASK, 0xffffffff); 368 369 /* Reset transmitter and receiver */ 370 bus_space_write_4(t, seb, HME_SEBI_RESET, 371 (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)); 372 373 for (n = 0; n < 20; n++) { 374 u_int32_t v = bus_space_read_4(t, seb, HME_SEBI_RESET); 375 if ((v & (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)) == 0) 376 return; 377 DELAY(20); 378 } 379 380 printf("%s: hme_stop: reset failed\n", sc->sc_dev.dv_xname); 381 } 382 383 void 384 hme_meminit(sc) 385 struct hme_softc *sc; 386 { 387 bus_addr_t txbufdma, rxbufdma; 388 bus_addr_t dma; 389 caddr_t p; 390 unsigned int ntbuf, nrbuf, i; 391 struct hme_ring *hr = &sc->sc_rb; 392 393 p = hr->rb_membase; 394 dma = hr->rb_dmabase; 395 396 ntbuf = hr->rb_ntbuf; 397 nrbuf = hr->rb_nrbuf; 398 399 /* 400 * Allocate transmit descriptors 401 */ 402 hr->rb_txd = p; 403 hr->rb_txddma = dma; 404 p += ntbuf * HME_XD_SIZE; 405 dma += ntbuf * HME_XD_SIZE; 406 /* We have reserved descriptor space until the next 2048 byte boundary.*/ 407 dma = (bus_addr_t)roundup((u_long)dma, 2048); 408 p = (caddr_t)roundup((u_long)p, 2048); 409 410 /* 411 * Allocate receive descriptors 412 */ 413 hr->rb_rxd = p; 414 hr->rb_rxddma = dma; 415 p += nrbuf * HME_XD_SIZE; 416 dma += nrbuf * HME_XD_SIZE; 417 /* Again move forward to the next 2048 byte boundary.*/ 418 dma = (bus_addr_t)roundup((u_long)dma, 2048); 419 p = (caddr_t)roundup((u_long)p, 2048); 420 421 422 /* 423 * Allocate transmit buffers 424 */ 425 hr->rb_txbuf = p; 426 txbufdma = dma; 427 p += ntbuf * _HME_BUFSZ; 428 dma += ntbuf * _HME_BUFSZ; 429 430 /* 431 * Allocate receive buffers 432 */ 433 hr->rb_rxbuf = p; 434 rxbufdma = dma; 435 p += nrbuf * _HME_BUFSZ; 436 dma += nrbuf * _HME_BUFSZ; 437 438 /* 439 * Initialize transmit buffer descriptors 440 */ 441 for (i = 0; i < ntbuf; i++) { 442 HME_XD_SETADDR(sc->sc_pci, hr->rb_txd, i, txbufdma + i * _HME_BUFSZ); 443 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_txd, i, 0); 444 } 445 446 /* 447 * Initialize receive buffer descriptors 448 */ 449 for (i = 0; i < nrbuf; i++) { 450 HME_XD_SETADDR(sc->sc_pci, hr->rb_rxd, i, rxbufdma + i * _HME_BUFSZ); 451 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_rxd, i, 452 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 453 } 454 455 hr->rb_tdhead = hr->rb_tdtail = 0; 456 hr->rb_td_nbusy = 0; 457 hr->rb_rdtail = 0; 458 } 459 460 /* 461 * Initialization of interface; set up initialization block 462 * and transmit/receive descriptor rings. 463 */ 464 void 465 hme_init(sc) 466 struct hme_softc *sc; 467 { 468 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 469 bus_space_tag_t t = sc->sc_bustag; 470 bus_space_handle_t seb = sc->sc_seb; 471 bus_space_handle_t etx = sc->sc_etx; 472 bus_space_handle_t erx = sc->sc_erx; 473 bus_space_handle_t mac = sc->sc_mac; 474 u_int8_t *ea; 475 u_int32_t v; 476 477 /* 478 * Initialization sequence. The numbered steps below correspond 479 * to the sequence outlined in section 6.3.5.1 in the Ethernet 480 * Channel Engine manual (part of the PCIO manual). 481 * See also the STP2002-STQ document from Sun Microsystems. 482 */ 483 484 /* step 1 & 2. Reset the Ethernet Channel */ 485 hme_stop(sc); 486 487 /* Re-initialize the MIF */ 488 hme_mifinit(sc); 489 490 /* Call MI reset function if any */ 491 if (sc->sc_hwreset) 492 (*sc->sc_hwreset)(sc); 493 494 #if 0 495 /* Mask all MIF interrupts, just in case */ 496 bus_space_write_4(t, mif, HME_MIFI_IMASK, 0xffff); 497 #endif 498 499 /* step 3. Setup data structures in host memory */ 500 hme_meminit(sc); 501 502 /* step 4. TX MAC registers & counters */ 503 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 504 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 505 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 506 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 507 bus_space_write_4(t, mac, HME_MACI_TXSIZE, 508 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 509 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN); 510 sc->sc_ec_capenable = sc->sc_ethercom.ec_capenable; 511 512 /* Load station MAC address */ 513 ea = sc->sc_enaddr; 514 bus_space_write_4(t, mac, HME_MACI_MACADDR0, (ea[0] << 8) | ea[1]); 515 bus_space_write_4(t, mac, HME_MACI_MACADDR1, (ea[2] << 8) | ea[3]); 516 bus_space_write_4(t, mac, HME_MACI_MACADDR2, (ea[4] << 8) | ea[5]); 517 518 /* 519 * Init seed for backoff 520 * (source suggested by manual: low 10 bits of MAC address) 521 */ 522 v = ((ea[4] << 8) | ea[5]) & 0x3fff; 523 bus_space_write_4(t, mac, HME_MACI_RANDSEED, v); 524 525 526 /* Note: Accepting power-on default for other MAC registers here.. */ 527 528 529 /* step 5. RX MAC registers & counters */ 530 hme_setladrf(sc); 531 532 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 533 bus_space_write_4(t, etx, HME_ETXI_RING, sc->sc_rb.rb_txddma); 534 bus_space_write_4(t, etx, HME_ETXI_RSIZE, sc->sc_rb.rb_ntbuf); 535 536 bus_space_write_4(t, erx, HME_ERXI_RING, sc->sc_rb.rb_rxddma); 537 bus_space_write_4(t, mac, HME_MACI_RXSIZE, 538 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 539 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN); 540 541 /* step 8. Global Configuration & Interrupt Mask */ 542 bus_space_write_4(t, seb, HME_SEBI_IMASK, 543 ~( 544 /*HME_SEB_STAT_GOTFRAME | HME_SEB_STAT_SENTFRAME |*/ 545 HME_SEB_STAT_HOSTTOTX | 546 HME_SEB_STAT_RXTOHOST | 547 HME_SEB_STAT_TXALL | 548 HME_SEB_STAT_TXPERR | 549 HME_SEB_STAT_RCNTEXP | 550 /*HME_SEB_STAT_MIFIRQ |*/ 551 HME_SEB_STAT_ALL_ERRORS )); 552 553 switch (sc->sc_burst) { 554 default: 555 v = 0; 556 break; 557 case 16: 558 v = HME_SEB_CFG_BURST16; 559 break; 560 case 32: 561 v = HME_SEB_CFG_BURST32; 562 break; 563 case 64: 564 v = HME_SEB_CFG_BURST64; 565 break; 566 } 567 bus_space_write_4(t, seb, HME_SEBI_CFG, v); 568 569 /* step 9. ETX Configuration: use mostly default values */ 570 571 /* Enable DMA */ 572 v = bus_space_read_4(t, etx, HME_ETXI_CFG); 573 v |= HME_ETX_CFG_DMAENABLE; 574 bus_space_write_4(t, etx, HME_ETXI_CFG, v); 575 576 /* Transmit Descriptor ring size: in increments of 16 */ 577 bus_space_write_4(t, etx, HME_ETXI_RSIZE, _HME_NDESC / 16 - 1); 578 579 580 /* step 10. ERX Configuration */ 581 v = bus_space_read_4(t, erx, HME_ERXI_CFG); 582 583 /* Encode Receive Descriptor ring size: four possible values */ 584 switch (_HME_NDESC /*XXX*/) { 585 case 32: 586 v |= HME_ERX_CFG_RINGSIZE32; 587 break; 588 case 64: 589 v |= HME_ERX_CFG_RINGSIZE64; 590 break; 591 case 128: 592 v |= HME_ERX_CFG_RINGSIZE128; 593 break; 594 case 256: 595 v |= HME_ERX_CFG_RINGSIZE256; 596 break; 597 default: 598 printf("hme: invalid Receive Descriptor ring size\n"); 599 break; 600 } 601 602 /* Enable DMA */ 603 v |= HME_ERX_CFG_DMAENABLE; 604 605 /* set h/w rx checksum start offset (# of half-words) */ 606 #ifdef INET 607 v |= (((ETHER_HDR_LEN + sizeof(struct ip) + 608 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 609 ETHER_VLAN_ENCAP_LEN : 0)) / 2) << HME_ERX_CFG_CSUMSHIFT) & 610 HME_ERX_CFG_CSUMSTART; 611 #endif 612 bus_space_write_4(t, erx, HME_ERXI_CFG, v); 613 614 /* step 11. XIF Configuration */ 615 v = bus_space_read_4(t, mac, HME_MACI_XIF); 616 v |= HME_MAC_XIF_OE; 617 bus_space_write_4(t, mac, HME_MACI_XIF, v); 618 619 /* step 12. RX_MAC Configuration Register */ 620 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 621 v |= HME_MAC_RXCFG_ENABLE | HME_MAC_RXCFG_PSTRIP; 622 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 623 624 /* step 13. TX_MAC Configuration Register */ 625 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 626 v |= (HME_MAC_TXCFG_ENABLE | HME_MAC_TXCFG_DGIVEUP); 627 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 628 629 /* step 14. Issue Transmit Pending command */ 630 631 /* Call MI initialization function if any */ 632 if (sc->sc_hwinit) 633 (*sc->sc_hwinit)(sc); 634 635 /* Set the current media. */ 636 mii_mediachg(&sc->sc_mii); 637 638 /* Start the one second timer. */ 639 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 640 641 ifp->if_flags |= IFF_RUNNING; 642 ifp->if_flags &= ~IFF_OACTIVE; 643 sc->sc_if_flags = ifp->if_flags; 644 ifp->if_timer = 0; 645 hme_start(ifp); 646 } 647 648 /* 649 * Compare two Ether/802 addresses for equality, inlined and unrolled for 650 * speed. 651 */ 652 static inline int 653 ether_cmp(a, b) 654 u_char *a, *b; 655 { 656 657 if (a[5] != b[5] || a[4] != b[4] || a[3] != b[3] || 658 a[2] != b[2] || a[1] != b[1] || a[0] != b[0]) 659 return (0); 660 return (1); 661 } 662 663 664 /* 665 * Routine to copy from mbuf chain to transmit buffer in 666 * network buffer memory. 667 * Returns the amount of data copied. 668 */ 669 int 670 hme_put(sc, ri, m) 671 struct hme_softc *sc; 672 int ri; /* Ring index */ 673 struct mbuf *m; 674 { 675 struct mbuf *n; 676 int len, tlen = 0; 677 caddr_t bp; 678 679 bp = sc->sc_rb.rb_txbuf + (ri % sc->sc_rb.rb_ntbuf) * _HME_BUFSZ; 680 for (; m; m = n) { 681 len = m->m_len; 682 if (len == 0) { 683 MFREE(m, n); 684 continue; 685 } 686 memcpy(bp, mtod(m, caddr_t), len); 687 bp += len; 688 tlen += len; 689 MFREE(m, n); 690 } 691 return (tlen); 692 } 693 694 /* 695 * Pull data off an interface. 696 * Len is length of data, with local net header stripped. 697 * We copy the data into mbufs. When full cluster sized units are present 698 * we copy into clusters. 699 */ 700 struct mbuf * 701 hme_get(sc, ri, flags) 702 struct hme_softc *sc; 703 int ri; 704 u_int32_t flags; 705 { 706 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 707 struct mbuf *m, *m0, *newm; 708 caddr_t bp; 709 int len, totlen; 710 711 totlen = HME_XD_DECODE_RSIZE(flags); 712 MGETHDR(m0, M_DONTWAIT, MT_DATA); 713 if (m0 == 0) 714 return (0); 715 m0->m_pkthdr.rcvif = ifp; 716 m0->m_pkthdr.len = totlen; 717 len = MHLEN; 718 m = m0; 719 720 bp = sc->sc_rb.rb_rxbuf + (ri % sc->sc_rb.rb_nrbuf) * _HME_BUFSZ; 721 722 while (totlen > 0) { 723 if (totlen >= MINCLSIZE) { 724 MCLGET(m, M_DONTWAIT); 725 if ((m->m_flags & M_EXT) == 0) 726 goto bad; 727 len = MCLBYTES; 728 } 729 730 if (m == m0) { 731 caddr_t newdata = (caddr_t) 732 ALIGN(m->m_data + sizeof(struct ether_header)) - 733 sizeof(struct ether_header); 734 len -= newdata - m->m_data; 735 m->m_data = newdata; 736 } 737 738 m->m_len = len = min(totlen, len); 739 memcpy(mtod(m, caddr_t), bp, len); 740 bp += len; 741 742 totlen -= len; 743 if (totlen > 0) { 744 MGET(newm, M_DONTWAIT, MT_DATA); 745 if (newm == 0) 746 goto bad; 747 len = MLEN; 748 m = m->m_next = newm; 749 } 750 } 751 752 #ifdef INET 753 /* hardware checksum */ 754 if (ifp->if_csum_flags_rx & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 755 struct ether_header *eh; 756 struct ip *ip; 757 struct udphdr *uh; 758 uint16_t *opts; 759 int32_t hlen, pktlen; 760 uint32_t temp; 761 762 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 763 pktlen = m0->m_pkthdr.len - ETHER_HDR_LEN - 764 ETHER_VLAN_ENCAP_LEN; 765 eh = (struct ether_header *) mtod(m0, caddr_t) + 766 ETHER_VLAN_ENCAP_LEN; 767 } else { 768 pktlen = m0->m_pkthdr.len - ETHER_HDR_LEN; 769 eh = mtod(m0, struct ether_header *); 770 } 771 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 772 goto swcsum; 773 ip = (struct ip *) ((caddr_t) eh + ETHER_HDR_LEN); 774 775 /* IPv4 only */ 776 if (ip->ip_v != IPVERSION) 777 goto swcsum; 778 779 hlen = ip->ip_hl << 2; 780 if (hlen < sizeof(struct ip)) 781 goto swcsum; 782 783 /* 784 * bail if too short, has random trailing garbage, truncated, 785 * fragment, or has ethernet pad. 786 */ 787 if ((ntohs(ip->ip_len) < hlen) || (ntohs(ip->ip_len) != pktlen) 788 || (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 789 goto swcsum; 790 791 switch (ip->ip_p) { 792 case IPPROTO_TCP: 793 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 794 goto swcsum; 795 if (pktlen < (hlen + sizeof(struct tcphdr))) 796 goto swcsum; 797 m0->m_pkthdr.csum_flags = M_CSUM_TCPv4; 798 break; 799 case IPPROTO_UDP: 800 if (! (ifp->if_csum_flags_rx & M_CSUM_UDPv4)) 801 goto swcsum; 802 if (pktlen < (hlen + sizeof(struct udphdr))) 803 goto swcsum; 804 uh = (struct udphdr *)((caddr_t)ip + hlen); 805 /* no checksum */ 806 if (uh->uh_sum == 0) 807 goto swcsum; 808 m0->m_pkthdr.csum_flags = M_CSUM_UDPv4; 809 break; 810 default: 811 goto swcsum; 812 } 813 814 /* w/ M_CSUM_NO_PSEUDOHDR, the uncomplemented sum is expected */ 815 m0->m_pkthdr.csum_data = (~flags) & HME_XD_RXCKSUM; 816 817 /* if the pkt had ip options, we have to deduct them */ 818 if (hlen > sizeof(struct ip)) { 819 uint32_t optsum; 820 821 optsum = 0; 822 temp = hlen - sizeof(struct ip); 823 opts = (uint16_t *) ((caddr_t) ip + sizeof(struct ip)); 824 825 while (temp > 1) { 826 optsum += ntohs(*opts++); 827 temp -= 2; 828 } 829 while (optsum >> 16) 830 optsum = (optsum >> 16) + (optsum & 0xffff); 831 832 /* Deduct the ip opts sum from the hwsum (rfc 1624). */ 833 m0->m_pkthdr.csum_data = ~((~m0->m_pkthdr.csum_data) - 834 ~optsum); 835 836 while (m0->m_pkthdr.csum_data >> 16) 837 m0->m_pkthdr.csum_data = 838 (m0->m_pkthdr.csum_data >> 16) + 839 (m0->m_pkthdr.csum_data & 0xffff); 840 } 841 842 m0->m_pkthdr.csum_flags |= M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 843 } 844 swcsum: 845 m0->m_pkthdr.csum_flags = 0; 846 #endif 847 848 return (m0); 849 850 bad: 851 m_freem(m0); 852 return (0); 853 } 854 855 /* 856 * Pass a packet to the higher levels. 857 */ 858 void 859 hme_read(sc, ix, flags) 860 struct hme_softc *sc; 861 int ix; 862 u_int32_t flags; 863 { 864 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 865 struct mbuf *m; 866 int len; 867 868 len = HME_XD_DECODE_RSIZE(flags); 869 if (len <= sizeof(struct ether_header) || 870 len > ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 871 ETHER_VLAN_ENCAP_LEN + ETHERMTU + sizeof(struct ether_header) : 872 ETHERMTU + sizeof(struct ether_header))) { 873 #ifdef HMEDEBUG 874 printf("%s: invalid packet size %d; dropping\n", 875 sc->sc_dev.dv_xname, len); 876 #endif 877 ifp->if_ierrors++; 878 return; 879 } 880 881 /* Pull packet off interface. */ 882 m = hme_get(sc, ix, flags); 883 if (m == 0) { 884 ifp->if_ierrors++; 885 return; 886 } 887 888 ifp->if_ipackets++; 889 890 #if NBPFILTER > 0 891 /* 892 * Check if there's a BPF listener on this interface. 893 * If so, hand off the raw packet to BPF. 894 */ 895 if (ifp->if_bpf) 896 bpf_mtap(ifp->if_bpf, m); 897 #endif 898 899 /* Pass the packet up. */ 900 (*ifp->if_input)(ifp, m); 901 } 902 903 void 904 hme_start(ifp) 905 struct ifnet *ifp; 906 { 907 struct hme_softc *sc = (struct hme_softc *)ifp->if_softc; 908 caddr_t txd = sc->sc_rb.rb_txd; 909 struct mbuf *m; 910 unsigned int txflags; 911 unsigned int ri, len; 912 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 913 914 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 915 return; 916 917 ri = sc->sc_rb.rb_tdhead; 918 919 for (;;) { 920 IFQ_DEQUEUE(&ifp->if_snd, m); 921 if (m == 0) 922 break; 923 924 #if NBPFILTER > 0 925 /* 926 * If BPF is listening on this interface, let it see the 927 * packet before we commit it to the wire. 928 */ 929 if (ifp->if_bpf) 930 bpf_mtap(ifp->if_bpf, m); 931 #endif 932 933 #ifdef INET 934 /* collect bits for h/w csum, before hme_put frees the mbuf */ 935 if (ifp->if_csum_flags_tx & (M_CSUM_TCPv4 | M_CSUM_UDPv4) && 936 m->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 937 struct ether_header *eh; 938 uint16_t offset, start; 939 940 eh = mtod(m, struct ether_header *); 941 switch (ntohs(eh->ether_type)) { 942 case ETHERTYPE_IP: 943 start = ETHER_HDR_LEN; 944 break; 945 case ETHERTYPE_VLAN: 946 start = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 947 break; 948 default: 949 /* unsupported, drop it */ 950 m_free(m); 951 continue; 952 } 953 start += M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 954 offset = M_CSUM_DATA_IPv4_OFFSET(m->m_pkthdr.csum_data) 955 + start; 956 txflags = HME_XD_TXCKSUM | 957 (offset << HME_XD_TXCSSTUFFSHIFT) | 958 (start << HME_XD_TXCSSTARTSHIFT); 959 } else 960 #endif 961 txflags = 0; 962 963 /* 964 * Copy the mbuf chain into the transmit buffer. 965 */ 966 len = hme_put(sc, ri, m); 967 968 /* 969 * Initialize transmit registers and start transmission 970 */ 971 HME_XD_SETFLAGS(sc->sc_pci, txd, ri, 972 HME_XD_OWN | HME_XD_SOP | HME_XD_EOP | 973 HME_XD_ENCODE_TSIZE(len) | txflags); 974 975 /*if (sc->sc_rb.rb_td_nbusy <= 0)*/ 976 bus_space_write_4(sc->sc_bustag, sc->sc_etx, HME_ETXI_PENDING, 977 HME_ETX_TP_DMAWAKEUP); 978 979 if (++ri == ntbuf) 980 ri = 0; 981 982 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 983 ifp->if_flags |= IFF_OACTIVE; 984 break; 985 } 986 } 987 988 sc->sc_rb.rb_tdhead = ri; 989 } 990 991 /* 992 * Transmit interrupt. 993 */ 994 int 995 hme_tint(sc) 996 struct hme_softc *sc; 997 { 998 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 999 bus_space_tag_t t = sc->sc_bustag; 1000 bus_space_handle_t mac = sc->sc_mac; 1001 unsigned int ri, txflags; 1002 1003 /* 1004 * Unload collision counters 1005 */ 1006 ifp->if_collisions += 1007 bus_space_read_4(t, mac, HME_MACI_NCCNT) + 1008 bus_space_read_4(t, mac, HME_MACI_FCCNT) + 1009 bus_space_read_4(t, mac, HME_MACI_EXCNT) + 1010 bus_space_read_4(t, mac, HME_MACI_LTCNT); 1011 1012 /* 1013 * then clear the hardware counters. 1014 */ 1015 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 1016 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 1017 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 1018 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 1019 1020 /* Fetch current position in the transmit ring */ 1021 ri = sc->sc_rb.rb_tdtail; 1022 1023 for (;;) { 1024 if (sc->sc_rb.rb_td_nbusy <= 0) 1025 break; 1026 1027 txflags = HME_XD_GETFLAGS(sc->sc_pci, sc->sc_rb.rb_txd, ri); 1028 1029 if (txflags & HME_XD_OWN) 1030 break; 1031 1032 ifp->if_flags &= ~IFF_OACTIVE; 1033 ifp->if_opackets++; 1034 1035 if (++ri == sc->sc_rb.rb_ntbuf) 1036 ri = 0; 1037 1038 --sc->sc_rb.rb_td_nbusy; 1039 } 1040 1041 /* Update ring */ 1042 sc->sc_rb.rb_tdtail = ri; 1043 1044 hme_start(ifp); 1045 1046 if (sc->sc_rb.rb_td_nbusy == 0) 1047 ifp->if_timer = 0; 1048 1049 return (1); 1050 } 1051 1052 /* 1053 * Receive interrupt. 1054 */ 1055 int 1056 hme_rint(sc) 1057 struct hme_softc *sc; 1058 { 1059 caddr_t xdr = sc->sc_rb.rb_rxd; 1060 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 1061 unsigned int ri; 1062 u_int32_t flags; 1063 1064 ri = sc->sc_rb.rb_rdtail; 1065 1066 /* 1067 * Process all buffers with valid data. 1068 */ 1069 for (;;) { 1070 flags = HME_XD_GETFLAGS(sc->sc_pci, xdr, ri); 1071 if (flags & HME_XD_OWN) 1072 break; 1073 1074 if (flags & HME_XD_OFL) { 1075 printf("%s: buffer overflow, ri=%d; flags=0x%x\n", 1076 sc->sc_dev.dv_xname, ri, flags); 1077 } else 1078 hme_read(sc, ri, flags); 1079 1080 /* This buffer can be used by the hardware again */ 1081 HME_XD_SETFLAGS(sc->sc_pci, xdr, ri, 1082 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 1083 1084 if (++ri == nrbuf) 1085 ri = 0; 1086 } 1087 1088 sc->sc_rb.rb_rdtail = ri; 1089 1090 return (1); 1091 } 1092 1093 int 1094 hme_eint(sc, status) 1095 struct hme_softc *sc; 1096 u_int status; 1097 { 1098 char bits[128]; 1099 1100 if ((status & HME_SEB_STAT_MIFIRQ) != 0) { 1101 bus_space_tag_t t = sc->sc_bustag; 1102 bus_space_handle_t mif = sc->sc_mif; 1103 u_int32_t cf, st, sm; 1104 cf = bus_space_read_4(t, mif, HME_MIFI_CFG); 1105 st = bus_space_read_4(t, mif, HME_MIFI_STAT); 1106 sm = bus_space_read_4(t, mif, HME_MIFI_SM); 1107 printf("%s: XXXlink status changed: cfg=%x, stat %x, sm %x\n", 1108 sc->sc_dev.dv_xname, cf, st, sm); 1109 return (1); 1110 } 1111 1112 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 1113 bitmask_snprintf(status, HME_SEB_STAT_BITS, bits,sizeof(bits))); 1114 return (1); 1115 } 1116 1117 int 1118 hme_intr(v) 1119 void *v; 1120 { 1121 struct hme_softc *sc = (struct hme_softc *)v; 1122 bus_space_tag_t t = sc->sc_bustag; 1123 bus_space_handle_t seb = sc->sc_seb; 1124 u_int32_t status; 1125 int r = 0; 1126 1127 status = bus_space_read_4(t, seb, HME_SEBI_STAT); 1128 1129 if ((status & HME_SEB_STAT_ALL_ERRORS) != 0) 1130 r |= hme_eint(sc, status); 1131 1132 if ((status & (HME_SEB_STAT_TXALL | HME_SEB_STAT_HOSTTOTX)) != 0) 1133 r |= hme_tint(sc); 1134 1135 if ((status & HME_SEB_STAT_RXTOHOST) != 0) 1136 r |= hme_rint(sc); 1137 1138 #if NRND > 0 1139 rnd_add_uint32(&sc->rnd_source, status); 1140 #endif 1141 1142 return (r); 1143 } 1144 1145 1146 void 1147 hme_watchdog(ifp) 1148 struct ifnet *ifp; 1149 { 1150 struct hme_softc *sc = ifp->if_softc; 1151 1152 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1153 ++ifp->if_oerrors; 1154 1155 hme_reset(sc); 1156 } 1157 1158 /* 1159 * Initialize the MII Management Interface 1160 */ 1161 void 1162 hme_mifinit(sc) 1163 struct hme_softc *sc; 1164 { 1165 bus_space_tag_t t = sc->sc_bustag; 1166 bus_space_handle_t mif = sc->sc_mif; 1167 bus_space_handle_t mac = sc->sc_mac; 1168 int instance, phy; 1169 u_int32_t v; 1170 1171 if (sc->sc_media.ifm_cur != NULL) { 1172 instance = IFM_INST(sc->sc_media.ifm_cur->ifm_media); 1173 phy = sc->sc_phys[instance]; 1174 } else 1175 /* No media set yet, pick phy arbitrarily.. */ 1176 phy = HME_PHYAD_EXTERNAL; 1177 1178 /* Configure the MIF in frame mode, no poll, current phy select */ 1179 v = 0; 1180 if (phy == HME_PHYAD_EXTERNAL) 1181 v |= HME_MIF_CFG_PHY; 1182 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1183 1184 /* If an external transceiver is selected, enable its MII drivers */ 1185 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1186 v &= ~HME_MAC_XIF_MIIENABLE; 1187 if (phy == HME_PHYAD_EXTERNAL) 1188 v |= HME_MAC_XIF_MIIENABLE; 1189 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1190 } 1191 1192 /* 1193 * MII interface 1194 */ 1195 static int 1196 hme_mii_readreg(self, phy, reg) 1197 struct device *self; 1198 int phy, reg; 1199 { 1200 struct hme_softc *sc = (void *)self; 1201 bus_space_tag_t t = sc->sc_bustag; 1202 bus_space_handle_t mif = sc->sc_mif; 1203 bus_space_handle_t mac = sc->sc_mac; 1204 u_int32_t v, xif_cfg, mifi_cfg; 1205 int n; 1206 1207 /* We can at most have two PHYs */ 1208 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1209 return (0); 1210 1211 /* Select the desired PHY in the MIF configuration register */ 1212 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1213 v &= ~HME_MIF_CFG_PHY; 1214 if (phy == HME_PHYAD_EXTERNAL) 1215 v |= HME_MIF_CFG_PHY; 1216 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1217 1218 /* Enable MII drivers on external transceiver */ 1219 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1220 if (phy == HME_PHYAD_EXTERNAL) 1221 v |= HME_MAC_XIF_MIIENABLE; 1222 else 1223 v &= ~HME_MAC_XIF_MIIENABLE; 1224 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1225 1226 #if 0 1227 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1228 /* 1229 * Check whether a transceiver is connected by testing 1230 * the MIF configuration register's MDI_X bits. Note that 1231 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1232 */ 1233 mif_mdi_bit = 1 << (8 + (1 - phy)); 1234 delay(100); 1235 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1236 if ((v & mif_mdi_bit) == 0) 1237 return (0); 1238 #endif 1239 1240 /* Construct the frame command */ 1241 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1242 HME_MIF_FO_TAMSB | 1243 (MII_COMMAND_READ << HME_MIF_FO_OPC_SHIFT) | 1244 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1245 (reg << HME_MIF_FO_REGAD_SHIFT); 1246 1247 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1248 for (n = 0; n < 100; n++) { 1249 DELAY(1); 1250 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1251 if (v & HME_MIF_FO_TALSB) { 1252 v &= HME_MIF_FO_DATA; 1253 goto out; 1254 } 1255 } 1256 1257 v = 0; 1258 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1259 1260 out: 1261 /* Restore MIFI_CFG register */ 1262 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1263 /* Restore XIF register */ 1264 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1265 return (v); 1266 } 1267 1268 static void 1269 hme_mii_writereg(self, phy, reg, val) 1270 struct device *self; 1271 int phy, reg, val; 1272 { 1273 struct hme_softc *sc = (void *)self; 1274 bus_space_tag_t t = sc->sc_bustag; 1275 bus_space_handle_t mif = sc->sc_mif; 1276 bus_space_handle_t mac = sc->sc_mac; 1277 u_int32_t v, xif_cfg, mifi_cfg; 1278 int n; 1279 1280 /* We can at most have two PHYs */ 1281 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1282 return; 1283 1284 /* Select the desired PHY in the MIF configuration register */ 1285 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1286 v &= ~HME_MIF_CFG_PHY; 1287 if (phy == HME_PHYAD_EXTERNAL) 1288 v |= HME_MIF_CFG_PHY; 1289 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1290 1291 /* Enable MII drivers on external transceiver */ 1292 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1293 if (phy == HME_PHYAD_EXTERNAL) 1294 v |= HME_MAC_XIF_MIIENABLE; 1295 else 1296 v &= ~HME_MAC_XIF_MIIENABLE; 1297 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1298 1299 #if 0 1300 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1301 /* 1302 * Check whether a transceiver is connected by testing 1303 * the MIF configuration register's MDI_X bits. Note that 1304 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1305 */ 1306 mif_mdi_bit = 1 << (8 + (1 - phy)); 1307 delay(100); 1308 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1309 if ((v & mif_mdi_bit) == 0) 1310 return; 1311 #endif 1312 1313 /* Construct the frame command */ 1314 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1315 HME_MIF_FO_TAMSB | 1316 (MII_COMMAND_WRITE << HME_MIF_FO_OPC_SHIFT) | 1317 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1318 (reg << HME_MIF_FO_REGAD_SHIFT) | 1319 (val & HME_MIF_FO_DATA); 1320 1321 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1322 for (n = 0; n < 100; n++) { 1323 DELAY(1); 1324 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1325 if (v & HME_MIF_FO_TALSB) 1326 goto out; 1327 } 1328 1329 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1330 out: 1331 /* Restore MIFI_CFG register */ 1332 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1333 /* Restore XIF register */ 1334 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1335 } 1336 1337 static void 1338 hme_mii_statchg(dev) 1339 struct device *dev; 1340 { 1341 struct hme_softc *sc = (void *)dev; 1342 bus_space_tag_t t = sc->sc_bustag; 1343 bus_space_handle_t mac = sc->sc_mac; 1344 u_int32_t v; 1345 1346 #ifdef HMEDEBUG 1347 if (sc->sc_debug) 1348 printf("hme_mii_statchg: status change\n"); 1349 #endif 1350 1351 /* Set the MAC Full Duplex bit appropriately */ 1352 /* Apparently the hme chip is SIMPLEX if working in full duplex mode, 1353 but not otherwise. */ 1354 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 1355 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1356 v |= HME_MAC_TXCFG_FULLDPLX; 1357 sc->sc_ethercom.ec_if.if_flags |= IFF_SIMPLEX; 1358 } else { 1359 v &= ~HME_MAC_TXCFG_FULLDPLX; 1360 sc->sc_ethercom.ec_if.if_flags &= ~IFF_SIMPLEX; 1361 } 1362 sc->sc_if_flags = sc->sc_ethercom.ec_if.if_flags; 1363 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 1364 } 1365 1366 int 1367 hme_mediachange(ifp) 1368 struct ifnet *ifp; 1369 { 1370 struct hme_softc *sc = ifp->if_softc; 1371 bus_space_tag_t t = sc->sc_bustag; 1372 bus_space_handle_t mif = sc->sc_mif; 1373 bus_space_handle_t mac = sc->sc_mac; 1374 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1375 int phy = sc->sc_phys[instance]; 1376 u_int32_t v; 1377 1378 #ifdef HMEDEBUG 1379 if (sc->sc_debug) 1380 printf("hme_mediachange: phy = %d\n", phy); 1381 #endif 1382 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 1383 return (EINVAL); 1384 1385 /* Select the current PHY in the MIF configuration register */ 1386 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1387 v &= ~HME_MIF_CFG_PHY; 1388 if (phy == HME_PHYAD_EXTERNAL) 1389 v |= HME_MIF_CFG_PHY; 1390 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1391 1392 /* If an external transceiver is selected, enable its MII drivers */ 1393 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1394 v &= ~HME_MAC_XIF_MIIENABLE; 1395 if (phy == HME_PHYAD_EXTERNAL) 1396 v |= HME_MAC_XIF_MIIENABLE; 1397 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1398 1399 return (mii_mediachg(&sc->sc_mii)); 1400 } 1401 1402 void 1403 hme_mediastatus(ifp, ifmr) 1404 struct ifnet *ifp; 1405 struct ifmediareq *ifmr; 1406 { 1407 struct hme_softc *sc = ifp->if_softc; 1408 1409 if ((ifp->if_flags & IFF_UP) == 0) 1410 return; 1411 1412 mii_pollstat(&sc->sc_mii); 1413 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1414 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1415 } 1416 1417 /* 1418 * Process an ioctl request. 1419 */ 1420 int 1421 hme_ioctl(ifp, cmd, data) 1422 struct ifnet *ifp; 1423 u_long cmd; 1424 caddr_t data; 1425 { 1426 struct hme_softc *sc = ifp->if_softc; 1427 struct ifaddr *ifa = (struct ifaddr *)data; 1428 struct ifreq *ifr = (struct ifreq *)data; 1429 int s, error = 0; 1430 1431 s = splnet(); 1432 1433 switch (cmd) { 1434 1435 case SIOCSIFADDR: 1436 switch (ifa->ifa_addr->sa_family) { 1437 #ifdef INET 1438 case AF_INET: 1439 if (ifp->if_flags & IFF_UP) 1440 hme_setladrf(sc); 1441 else { 1442 ifp->if_flags |= IFF_UP; 1443 hme_init(sc); 1444 } 1445 arp_ifinit(ifp, ifa); 1446 break; 1447 #endif 1448 default: 1449 ifp->if_flags |= IFF_UP; 1450 hme_init(sc); 1451 break; 1452 } 1453 break; 1454 1455 case SIOCSIFFLAGS: 1456 #ifdef HMEDEBUG 1457 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0; 1458 #endif 1459 1460 if ((ifp->if_flags & IFF_UP) == 0 && 1461 (ifp->if_flags & IFF_RUNNING) != 0) { 1462 /* 1463 * If interface is marked down and it is running, then 1464 * stop it. 1465 */ 1466 hme_stop(sc); 1467 ifp->if_flags &= ~IFF_RUNNING; 1468 } else if ((ifp->if_flags & IFF_UP) != 0 && 1469 (ifp->if_flags & IFF_RUNNING) == 0) { 1470 /* 1471 * If interface is marked up and it is stopped, then 1472 * start it. 1473 */ 1474 hme_init(sc); 1475 } else if ((ifp->if_flags & IFF_UP) != 0) { 1476 /* 1477 * If setting debug or promiscuous mode, do not reset 1478 * the chip; for everything else, call hme_init() 1479 * which will trigger a reset. 1480 */ 1481 #define RESETIGN (IFF_CANTCHANGE | IFF_DEBUG) 1482 if (ifp->if_flags != sc->sc_if_flags) { 1483 if ((ifp->if_flags & (~RESETIGN)) 1484 == (sc->sc_if_flags & (~RESETIGN))) 1485 hme_setladrf(sc); 1486 else 1487 hme_init(sc); 1488 } 1489 #undef RESETIGN 1490 } 1491 1492 if (sc->sc_ec_capenable != sc->sc_ethercom.ec_capenable) 1493 hme_init(sc); 1494 1495 break; 1496 1497 case SIOCADDMULTI: 1498 case SIOCDELMULTI: 1499 error = (cmd == SIOCADDMULTI) ? 1500 ether_addmulti(ifr, &sc->sc_ethercom) : 1501 ether_delmulti(ifr, &sc->sc_ethercom); 1502 1503 if (error == ENETRESET) { 1504 /* 1505 * Multicast list has changed; set the hardware filter 1506 * accordingly. 1507 */ 1508 if (ifp->if_flags & IFF_RUNNING) 1509 hme_setladrf(sc); 1510 error = 0; 1511 } 1512 break; 1513 1514 case SIOCGIFMEDIA: 1515 case SIOCSIFMEDIA: 1516 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1517 break; 1518 1519 default: 1520 error = EINVAL; 1521 break; 1522 } 1523 1524 sc->sc_if_flags = ifp->if_flags; 1525 splx(s); 1526 return (error); 1527 } 1528 1529 void 1530 hme_shutdown(arg) 1531 void *arg; 1532 { 1533 1534 hme_stop((struct hme_softc *)arg); 1535 } 1536 1537 /* 1538 * Set up the logical address filter. 1539 */ 1540 void 1541 hme_setladrf(sc) 1542 struct hme_softc *sc; 1543 { 1544 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1545 struct ether_multi *enm; 1546 struct ether_multistep step; 1547 struct ethercom *ec = &sc->sc_ethercom; 1548 bus_space_tag_t t = sc->sc_bustag; 1549 bus_space_handle_t mac = sc->sc_mac; 1550 u_char *cp; 1551 u_int32_t crc; 1552 u_int32_t hash[4]; 1553 u_int32_t v; 1554 int len; 1555 1556 /* Clear hash table */ 1557 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1558 1559 /* Get current RX configuration */ 1560 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 1561 1562 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1563 /* Turn on promiscuous mode; turn off the hash filter */ 1564 v |= HME_MAC_RXCFG_PMISC; 1565 v &= ~HME_MAC_RXCFG_HENABLE; 1566 ifp->if_flags |= IFF_ALLMULTI; 1567 goto chipit; 1568 } 1569 1570 /* Turn off promiscuous mode; turn on the hash filter */ 1571 v &= ~HME_MAC_RXCFG_PMISC; 1572 v |= HME_MAC_RXCFG_HENABLE; 1573 1574 /* 1575 * Set up multicast address filter by passing all multicast addresses 1576 * through a crc generator, and then using the high order 6 bits as an 1577 * index into the 64 bit logical address filter. The high order bit 1578 * selects the word, while the rest of the bits select the bit within 1579 * the word. 1580 */ 1581 1582 ETHER_FIRST_MULTI(step, ec, enm); 1583 while (enm != NULL) { 1584 if (ether_cmp(enm->enm_addrlo, enm->enm_addrhi)) { 1585 /* 1586 * We must listen to a range of multicast addresses. 1587 * For now, just accept all multicasts, rather than 1588 * trying to set only those filter bits needed to match 1589 * the range. (At this time, the only use of address 1590 * ranges is for IP multicast routing, for which the 1591 * range is big enough to require all bits set.) 1592 */ 1593 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1594 ifp->if_flags |= IFF_ALLMULTI; 1595 goto chipit; 1596 } 1597 1598 cp = enm->enm_addrlo; 1599 crc = 0xffffffff; 1600 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1601 int octet = *cp++; 1602 int i; 1603 1604 #define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */ 1605 for (i = 0; i < 8; i++) { 1606 if ((crc & 1) ^ (octet & 1)) { 1607 crc >>= 1; 1608 crc ^= MC_POLY_LE; 1609 } else { 1610 crc >>= 1; 1611 } 1612 octet >>= 1; 1613 } 1614 } 1615 /* Just want the 6 most significant bits. */ 1616 crc >>= 26; 1617 1618 /* Set the corresponding bit in the filter. */ 1619 hash[crc >> 4] |= 1 << (crc & 0xf); 1620 1621 ETHER_NEXT_MULTI(step, enm); 1622 } 1623 1624 ifp->if_flags &= ~IFF_ALLMULTI; 1625 1626 chipit: 1627 /* Now load the hash table into the chip */ 1628 bus_space_write_4(t, mac, HME_MACI_HASHTAB0, hash[0]); 1629 bus_space_write_4(t, mac, HME_MACI_HASHTAB1, hash[1]); 1630 bus_space_write_4(t, mac, HME_MACI_HASHTAB2, hash[2]); 1631 bus_space_write_4(t, mac, HME_MACI_HASHTAB3, hash[3]); 1632 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 1633 } 1634 1635 /* 1636 * Routines for accessing the transmit and receive buffers. 1637 * The various CPU and adapter configurations supported by this 1638 * driver require three different access methods for buffers 1639 * and descriptors: 1640 * (1) contig (contiguous data; no padding), 1641 * (2) gap2 (two bytes of data followed by two bytes of padding), 1642 * (3) gap16 (16 bytes of data followed by 16 bytes of padding). 1643 */ 1644 1645 #if 0 1646 /* 1647 * contig: contiguous data with no padding. 1648 * 1649 * Buffers may have any alignment. 1650 */ 1651 1652 void 1653 hme_copytobuf_contig(sc, from, ri, len) 1654 struct hme_softc *sc; 1655 void *from; 1656 int ri, len; 1657 { 1658 volatile caddr_t buf = sc->sc_rb.rb_txbuf + (ri * _HME_BUFSZ); 1659 1660 /* 1661 * Just call memcpy() to do the work. 1662 */ 1663 memcpy(buf, from, len); 1664 } 1665 1666 void 1667 hme_copyfrombuf_contig(sc, to, boff, len) 1668 struct hme_softc *sc; 1669 void *to; 1670 int boff, len; 1671 { 1672 volatile caddr_t buf = sc->sc_rb.rb_rxbuf + (ri * _HME_BUFSZ); 1673 1674 /* 1675 * Just call memcpy() to do the work. 1676 */ 1677 memcpy(to, buf, len); 1678 } 1679 #endif
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