FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/hme.c
1 /* $NetBSD: hme.c,v 1.66.10.4 2009/11/13 20:57:27 sborrill Exp $ */
2
3 /*-
4 * Copyright (c) 1999 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Paul Kranenburg.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * HME Ethernet module driver.
34 */
35
36 #include <sys/cdefs.h>
37 __KERNEL_RCSID(0, "$NetBSD: hme.c,v 1.66.10.4 2009/11/13 20:57:27 sborrill Exp $");
38
39 /* #define HMEDEBUG */
40
41 #include "opt_inet.h"
42 #include "bpfilter.h"
43 #include "rnd.h"
44
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/kernel.h>
48 #include <sys/mbuf.h>
49 #include <sys/syslog.h>
50 #include <sys/socket.h>
51 #include <sys/device.h>
52 #include <sys/malloc.h>
53 #include <sys/ioctl.h>
54 #include <sys/errno.h>
55 #if NRND > 0
56 #include <sys/rnd.h>
57 #endif
58
59 #include <net/if.h>
60 #include <net/if_dl.h>
61 #include <net/if_ether.h>
62 #include <net/if_media.h>
63
64 #ifdef INET
65 #include <netinet/in.h>
66 #include <netinet/if_inarp.h>
67 #include <netinet/in_systm.h>
68 #include <netinet/in_var.h>
69 #include <netinet/ip.h>
70 #include <netinet/tcp.h>
71 #include <netinet/udp.h>
72 #endif
73
74
75 #if NBPFILTER > 0
76 #include <net/bpf.h>
77 #include <net/bpfdesc.h>
78 #endif
79
80 #include <dev/mii/mii.h>
81 #include <dev/mii/miivar.h>
82
83 #include <sys/bus.h>
84
85 #include <dev/ic/hmereg.h>
86 #include <dev/ic/hmevar.h>
87
88 void hme_start(struct ifnet *);
89 void hme_stop(struct hme_softc *,bool);
90 int hme_ioctl(struct ifnet *, u_long, void *);
91 void hme_tick(void *);
92 void hme_watchdog(struct ifnet *);
93 void hme_shutdown(void *);
94 int hme_init(struct ifnet *);
95 void hme_meminit(struct hme_softc *);
96 void hme_mifinit(struct hme_softc *);
97 void hme_reset(struct hme_softc *);
98 void hme_setladrf(struct hme_softc *);
99
100 /* MII methods & callbacks */
101 static int hme_mii_readreg(struct device *, int, int);
102 static void hme_mii_writereg(struct device *, int, int, int);
103 static void hme_mii_statchg(struct device *);
104
105 int hme_mediachange(struct ifnet *);
106
107 struct mbuf *hme_get(struct hme_softc *, int, uint32_t);
108 int hme_put(struct hme_softc *, int, struct mbuf *);
109 void hme_read(struct hme_softc *, int, uint32_t);
110 int hme_eint(struct hme_softc *, u_int);
111 int hme_rint(struct hme_softc *);
112 int hme_tint(struct hme_softc *);
113
114 /* Default buffer copy routines */
115 void hme_copytobuf_contig(struct hme_softc *, void *, int, int);
116 void hme_copyfrombuf_contig(struct hme_softc *, void *, int, int);
117 void hme_zerobuf_contig(struct hme_softc *, int, int);
118
119
120 void
121 hme_config(sc)
122 struct hme_softc *sc;
123 {
124 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
125 struct mii_data *mii = &sc->sc_mii;
126 struct mii_softc *child;
127 bus_dma_tag_t dmatag = sc->sc_dmatag;
128 bus_dma_segment_t seg;
129 bus_size_t size;
130 int rseg, error;
131
132 /*
133 * HME common initialization.
134 *
135 * hme_softc fields that must be initialized by the front-end:
136 *
137 * the bus tag:
138 * sc_bustag
139 *
140 * the DMA bus tag:
141 * sc_dmatag
142 *
143 * the bus handles:
144 * sc_seb (Shared Ethernet Block registers)
145 * sc_erx (Receiver Unit registers)
146 * sc_etx (Transmitter Unit registers)
147 * sc_mac (MAC registers)
148 * sc_mif (Management Interface registers)
149 *
150 * the maximum bus burst size:
151 * sc_burst
152 *
153 * (notyet:DMA capable memory for the ring descriptors & packet buffers:
154 * rb_membase, rb_dmabase)
155 *
156 * the local Ethernet address:
157 * sc_enaddr
158 *
159 */
160
161 /* Make sure the chip is stopped. */
162 hme_stop(sc, true);
163
164
165 /*
166 * Allocate descriptors and buffers
167 * XXX - do all this differently.. and more configurably,
168 * eg. use things as `dma_load_mbuf()' on transmit,
169 * and a pool of `EXTMEM' mbufs (with buffers DMA-mapped
170 * all the time) on the receiver side.
171 *
172 * Note: receive buffers must be 64-byte aligned.
173 * Also, apparently, the buffers must extend to a DMA burst
174 * boundary beyond the maximum packet size.
175 */
176 #define _HME_NDESC 128
177 #define _HME_BUFSZ 1600
178
179 /* Note: the # of descriptors must be a multiple of 16 */
180 sc->sc_rb.rb_ntbuf = _HME_NDESC;
181 sc->sc_rb.rb_nrbuf = _HME_NDESC;
182
183 /*
184 * Allocate DMA capable memory
185 * Buffer descriptors must be aligned on a 2048 byte boundary;
186 * take this into account when calculating the size. Note that
187 * the maximum number of descriptors (256) occupies 2048 bytes,
188 * so we allocate that much regardless of _HME_NDESC.
189 */
190 size = 2048 + /* TX descriptors */
191 2048 + /* RX descriptors */
192 sc->sc_rb.rb_ntbuf * _HME_BUFSZ + /* TX buffers */
193 sc->sc_rb.rb_nrbuf * _HME_BUFSZ; /* RX buffers */
194
195 /* Allocate DMA buffer */
196 if ((error = bus_dmamem_alloc(dmatag, size,
197 2048, 0,
198 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
199 aprint_error_dev(&sc->sc_dev, "DMA buffer alloc error %d\n",
200 error);
201 return;
202 }
203
204 /* Map DMA memory in CPU addressable space */
205 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size,
206 &sc->sc_rb.rb_membase,
207 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
208 aprint_error_dev(&sc->sc_dev, "DMA buffer map error %d\n",
209 error);
210 bus_dmamap_unload(dmatag, sc->sc_dmamap);
211 bus_dmamem_free(dmatag, &seg, rseg);
212 return;
213 }
214
215 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0,
216 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) {
217 aprint_error_dev(&sc->sc_dev, "DMA map create error %d\n",
218 error);
219 return;
220 }
221
222 /* Load the buffer */
223 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap,
224 sc->sc_rb.rb_membase, size, NULL,
225 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
226 aprint_error_dev(&sc->sc_dev, "DMA buffer map load error %d\n",
227 error);
228 bus_dmamem_free(dmatag, &seg, rseg);
229 return;
230 }
231 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr;
232
233 printf("%s: Ethernet address %s\n", device_xname(&sc->sc_dev),
234 ether_sprintf(sc->sc_enaddr));
235
236 /* Initialize ifnet structure. */
237 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ);
238 ifp->if_softc = sc;
239 ifp->if_start = hme_start;
240 ifp->if_ioctl = hme_ioctl;
241 ifp->if_init = hme_init;
242 ifp->if_watchdog = hme_watchdog;
243 ifp->if_flags =
244 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST;
245 sc->sc_if_flags = ifp->if_flags;
246 ifp->if_capabilities |=
247 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
248 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx;
249 IFQ_SET_READY(&ifp->if_snd);
250
251 /* Initialize ifmedia structures and MII info */
252 mii->mii_ifp = ifp;
253 mii->mii_readreg = hme_mii_readreg;
254 mii->mii_writereg = hme_mii_writereg;
255 mii->mii_statchg = hme_mii_statchg;
256
257 sc->sc_ethercom.ec_mii = mii;
258 ifmedia_init(&mii->mii_media, 0, hme_mediachange, ether_mediastatus);
259
260 hme_mifinit(sc);
261
262 mii_attach(&sc->sc_dev, mii, 0xffffffff,
263 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG);
264
265 child = LIST_FIRST(&mii->mii_phys);
266 if (child == NULL) {
267 /* No PHY attached */
268 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
269 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL);
270 } else {
271 /*
272 * Walk along the list of attached MII devices and
273 * establish an `MII instance' to `phy number'
274 * mapping. We'll use this mapping in media change
275 * requests to determine which phy to use to program
276 * the MIF configuration register.
277 */
278 for (; child != NULL; child = LIST_NEXT(child, mii_list)) {
279 /*
280 * Note: we support just two PHYs: the built-in
281 * internal device and an external on the MII
282 * connector.
283 */
284 if (child->mii_phy > 1 || child->mii_inst > 1) {
285 aprint_error_dev(&sc->sc_dev, "cannot accommodate MII device %s"
286 " at phy %d, instance %d\n",
287 device_xname(child->mii_dev),
288 child->mii_phy, child->mii_inst);
289 continue;
290 }
291
292 sc->sc_phys[child->mii_inst] = child->mii_phy;
293 }
294
295 /*
296 * XXX - we can really do the following ONLY if the
297 * phy indeed has the auto negotiation capability!!
298 */
299 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
300 }
301
302 /* claim 802.1q capability */
303 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU;
304
305 /* Attach the interface. */
306 if_attach(ifp);
307 ether_ifattach(ifp, sc->sc_enaddr);
308
309 sc->sc_sh = shutdownhook_establish(hme_shutdown, sc);
310 if (sc->sc_sh == NULL)
311 panic("hme_config: can't establish shutdownhook");
312
313 #if NRND > 0
314 rnd_attach_source(&sc->rnd_source, device_xname(&sc->sc_dev),
315 RND_TYPE_NET, 0);
316 #endif
317
318 callout_init(&sc->sc_tick_ch, 0);
319 }
320
321 void
322 hme_tick(arg)
323 void *arg;
324 {
325 struct hme_softc *sc = arg;
326 int s;
327
328 s = splnet();
329 mii_tick(&sc->sc_mii);
330 splx(s);
331
332 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc);
333 }
334
335 void
336 hme_reset(sc)
337 struct hme_softc *sc;
338 {
339 int s;
340
341 s = splnet();
342 (void)hme_init(&sc->sc_ethercom.ec_if);
343 splx(s);
344 }
345
346 void
347 hme_stop(struct hme_softc *sc, bool chip_only)
348 {
349 bus_space_tag_t t = sc->sc_bustag;
350 bus_space_handle_t seb = sc->sc_seb;
351 int n;
352
353 if (!chip_only) {
354 callout_stop(&sc->sc_tick_ch);
355 mii_down(&sc->sc_mii);
356 }
357
358 /* Mask all interrupts */
359 bus_space_write_4(t, seb, HME_SEBI_IMASK, 0xffffffff);
360
361 /* Reset transmitter and receiver */
362 bus_space_write_4(t, seb, HME_SEBI_RESET,
363 (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX));
364
365 for (n = 0; n < 20; n++) {
366 u_int32_t v = bus_space_read_4(t, seb, HME_SEBI_RESET);
367 if ((v & (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)) == 0)
368 return;
369 DELAY(20);
370 }
371
372 printf("%s: hme_stop: reset failed\n", device_xname(&sc->sc_dev));
373 }
374
375 void
376 hme_meminit(sc)
377 struct hme_softc *sc;
378 {
379 bus_addr_t txbufdma, rxbufdma;
380 bus_addr_t dma;
381 char *p;
382 unsigned int ntbuf, nrbuf, i;
383 struct hme_ring *hr = &sc->sc_rb;
384
385 p = hr->rb_membase;
386 dma = hr->rb_dmabase;
387
388 ntbuf = hr->rb_ntbuf;
389 nrbuf = hr->rb_nrbuf;
390
391 /*
392 * Allocate transmit descriptors
393 */
394 hr->rb_txd = p;
395 hr->rb_txddma = dma;
396 p += ntbuf * HME_XD_SIZE;
397 dma += ntbuf * HME_XD_SIZE;
398 /* We have reserved descriptor space until the next 2048 byte boundary.*/
399 dma = (bus_addr_t)roundup((u_long)dma, 2048);
400 p = (void *)roundup((u_long)p, 2048);
401
402 /*
403 * Allocate receive descriptors
404 */
405 hr->rb_rxd = p;
406 hr->rb_rxddma = dma;
407 p += nrbuf * HME_XD_SIZE;
408 dma += nrbuf * HME_XD_SIZE;
409 /* Again move forward to the next 2048 byte boundary.*/
410 dma = (bus_addr_t)roundup((u_long)dma, 2048);
411 p = (void *)roundup((u_long)p, 2048);
412
413
414 /*
415 * Allocate transmit buffers
416 */
417 hr->rb_txbuf = p;
418 txbufdma = dma;
419 p += ntbuf * _HME_BUFSZ;
420 dma += ntbuf * _HME_BUFSZ;
421
422 /*
423 * Allocate receive buffers
424 */
425 hr->rb_rxbuf = p;
426 rxbufdma = dma;
427 p += nrbuf * _HME_BUFSZ;
428 dma += nrbuf * _HME_BUFSZ;
429
430 /*
431 * Initialize transmit buffer descriptors
432 */
433 for (i = 0; i < ntbuf; i++) {
434 HME_XD_SETADDR(sc->sc_pci, hr->rb_txd, i, txbufdma + i * _HME_BUFSZ);
435 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_txd, i, 0);
436 }
437
438 /*
439 * Initialize receive buffer descriptors
440 */
441 for (i = 0; i < nrbuf; i++) {
442 HME_XD_SETADDR(sc->sc_pci, hr->rb_rxd, i, rxbufdma + i * _HME_BUFSZ);
443 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_rxd, i,
444 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ));
445 }
446
447 hr->rb_tdhead = hr->rb_tdtail = 0;
448 hr->rb_td_nbusy = 0;
449 hr->rb_rdtail = 0;
450 }
451
452 /*
453 * Initialization of interface; set up initialization block
454 * and transmit/receive descriptor rings.
455 */
456 int
457 hme_init(ifp)
458 struct ifnet *ifp;
459 {
460 struct hme_softc *sc = (struct hme_softc *)ifp->if_softc;
461 bus_space_tag_t t = sc->sc_bustag;
462 bus_space_handle_t seb = sc->sc_seb;
463 bus_space_handle_t etx = sc->sc_etx;
464 bus_space_handle_t erx = sc->sc_erx;
465 bus_space_handle_t mac = sc->sc_mac;
466 u_int8_t *ea;
467 u_int32_t v;
468 int rc;
469
470 /*
471 * Initialization sequence. The numbered steps below correspond
472 * to the sequence outlined in section 6.3.5.1 in the Ethernet
473 * Channel Engine manual (part of the PCIO manual).
474 * See also the STP2002-STQ document from Sun Microsystems.
475 */
476
477 /* step 1 & 2. Reset the Ethernet Channel */
478 hme_stop(sc, false);
479
480 /* Re-initialize the MIF */
481 hme_mifinit(sc);
482
483 /* Call MI reset function if any */
484 if (sc->sc_hwreset)
485 (*sc->sc_hwreset)(sc);
486
487 #if 0
488 /* Mask all MIF interrupts, just in case */
489 bus_space_write_4(t, mif, HME_MIFI_IMASK, 0xffff);
490 #endif
491
492 /* step 3. Setup data structures in host memory */
493 hme_meminit(sc);
494
495 /* step 4. TX MAC registers & counters */
496 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0);
497 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0);
498 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0);
499 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0);
500 bus_space_write_4(t, mac, HME_MACI_TXSIZE,
501 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ?
502 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN);
503 sc->sc_ec_capenable = sc->sc_ethercom.ec_capenable;
504
505 /* Load station MAC address */
506 ea = sc->sc_enaddr;
507 bus_space_write_4(t, mac, HME_MACI_MACADDR0, (ea[0] << 8) | ea[1]);
508 bus_space_write_4(t, mac, HME_MACI_MACADDR1, (ea[2] << 8) | ea[3]);
509 bus_space_write_4(t, mac, HME_MACI_MACADDR2, (ea[4] << 8) | ea[5]);
510
511 /*
512 * Init seed for backoff
513 * (source suggested by manual: low 10 bits of MAC address)
514 */
515 v = ((ea[4] << 8) | ea[5]) & 0x3fff;
516 bus_space_write_4(t, mac, HME_MACI_RANDSEED, v);
517
518
519 /* Note: Accepting power-on default for other MAC registers here.. */
520
521
522 /* step 5. RX MAC registers & counters */
523 hme_setladrf(sc);
524
525 /* step 6 & 7. Program Descriptor Ring Base Addresses */
526 bus_space_write_4(t, etx, HME_ETXI_RING, sc->sc_rb.rb_txddma);
527 bus_space_write_4(t, etx, HME_ETXI_RSIZE, sc->sc_rb.rb_ntbuf);
528
529 bus_space_write_4(t, erx, HME_ERXI_RING, sc->sc_rb.rb_rxddma);
530 bus_space_write_4(t, mac, HME_MACI_RXSIZE,
531 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ?
532 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN);
533
534 /* step 8. Global Configuration & Interrupt Mask */
535 bus_space_write_4(t, seb, HME_SEBI_IMASK,
536 ~(
537 /*HME_SEB_STAT_GOTFRAME | HME_SEB_STAT_SENTFRAME |*/
538 HME_SEB_STAT_HOSTTOTX |
539 HME_SEB_STAT_RXTOHOST |
540 HME_SEB_STAT_TXALL |
541 HME_SEB_STAT_TXPERR |
542 HME_SEB_STAT_RCNTEXP |
543 /*HME_SEB_STAT_MIFIRQ |*/
544 HME_SEB_STAT_ALL_ERRORS ));
545
546 switch (sc->sc_burst) {
547 default:
548 v = 0;
549 break;
550 case 16:
551 v = HME_SEB_CFG_BURST16;
552 break;
553 case 32:
554 v = HME_SEB_CFG_BURST32;
555 break;
556 case 64:
557 v = HME_SEB_CFG_BURST64;
558 break;
559 }
560 bus_space_write_4(t, seb, HME_SEBI_CFG, v);
561
562 /* step 9. ETX Configuration: use mostly default values */
563
564 /* Enable DMA */
565 v = bus_space_read_4(t, etx, HME_ETXI_CFG);
566 v |= HME_ETX_CFG_DMAENABLE;
567 bus_space_write_4(t, etx, HME_ETXI_CFG, v);
568
569 /* Transmit Descriptor ring size: in increments of 16 */
570 bus_space_write_4(t, etx, HME_ETXI_RSIZE, _HME_NDESC / 16 - 1);
571
572
573 /* step 10. ERX Configuration */
574 v = bus_space_read_4(t, erx, HME_ERXI_CFG);
575
576 /* Encode Receive Descriptor ring size: four possible values */
577 switch (_HME_NDESC /*XXX*/) {
578 case 32:
579 v |= HME_ERX_CFG_RINGSIZE32;
580 break;
581 case 64:
582 v |= HME_ERX_CFG_RINGSIZE64;
583 break;
584 case 128:
585 v |= HME_ERX_CFG_RINGSIZE128;
586 break;
587 case 256:
588 v |= HME_ERX_CFG_RINGSIZE256;
589 break;
590 default:
591 printf("hme: invalid Receive Descriptor ring size\n");
592 break;
593 }
594
595 /* Enable DMA */
596 v |= HME_ERX_CFG_DMAENABLE;
597
598 /* set h/w rx checksum start offset (# of half-words) */
599 #ifdef INET
600 v |= (((ETHER_HDR_LEN + sizeof(struct ip) +
601 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ?
602 ETHER_VLAN_ENCAP_LEN : 0)) / 2) << HME_ERX_CFG_CSUMSHIFT) &
603 HME_ERX_CFG_CSUMSTART;
604 #endif
605 bus_space_write_4(t, erx, HME_ERXI_CFG, v);
606
607 /* step 11. XIF Configuration */
608 v = bus_space_read_4(t, mac, HME_MACI_XIF);
609 v |= HME_MAC_XIF_OE;
610 bus_space_write_4(t, mac, HME_MACI_XIF, v);
611
612 /* step 12. RX_MAC Configuration Register */
613 v = bus_space_read_4(t, mac, HME_MACI_RXCFG);
614 v |= HME_MAC_RXCFG_ENABLE | HME_MAC_RXCFG_PSTRIP;
615 bus_space_write_4(t, mac, HME_MACI_RXCFG, v);
616
617 /* step 13. TX_MAC Configuration Register */
618 v = bus_space_read_4(t, mac, HME_MACI_TXCFG);
619 v |= (HME_MAC_TXCFG_ENABLE | HME_MAC_TXCFG_DGIVEUP);
620 bus_space_write_4(t, mac, HME_MACI_TXCFG, v);
621
622 /* step 14. Issue Transmit Pending command */
623
624 /* Call MI initialization function if any */
625 if (sc->sc_hwinit)
626 (*sc->sc_hwinit)(sc);
627
628 /* Set the current media. */
629 if ((rc = hme_mediachange(ifp)) != 0)
630 return rc;
631
632 /* Start the one second timer. */
633 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc);
634
635 ifp->if_flags |= IFF_RUNNING;
636 ifp->if_flags &= ~IFF_OACTIVE;
637 sc->sc_if_flags = ifp->if_flags;
638 ifp->if_timer = 0;
639 hme_start(ifp);
640 return 0;
641 }
642
643 /*
644 * Routine to copy from mbuf chain to transmit buffer in
645 * network buffer memory.
646 * Returns the amount of data copied.
647 */
648 int
649 hme_put(sc, ri, m)
650 struct hme_softc *sc;
651 int ri; /* Ring index */
652 struct mbuf *m;
653 {
654 struct mbuf *n;
655 int len, tlen = 0;
656 char *bp;
657
658 bp = (char *)sc->sc_rb.rb_txbuf + (ri % sc->sc_rb.rb_ntbuf) * _HME_BUFSZ;
659 for (; m; m = n) {
660 len = m->m_len;
661 if (len == 0) {
662 MFREE(m, n);
663 continue;
664 }
665 memcpy(bp, mtod(m, void *), len);
666 bp += len;
667 tlen += len;
668 MFREE(m, n);
669 }
670 return (tlen);
671 }
672
673 /*
674 * Pull data off an interface.
675 * Len is length of data, with local net header stripped.
676 * We copy the data into mbufs. When full cluster sized units are present
677 * we copy into clusters.
678 */
679 struct mbuf *
680 hme_get(sc, ri, flags)
681 struct hme_softc *sc;
682 int ri;
683 u_int32_t flags;
684 {
685 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
686 struct mbuf *m, *m0, *newm;
687 char *bp;
688 int len, totlen;
689
690 totlen = HME_XD_DECODE_RSIZE(flags);
691 MGETHDR(m0, M_DONTWAIT, MT_DATA);
692 if (m0 == 0)
693 return (0);
694 m0->m_pkthdr.rcvif = ifp;
695 m0->m_pkthdr.len = totlen;
696 len = MHLEN;
697 m = m0;
698
699 bp = (char *)sc->sc_rb.rb_rxbuf + (ri % sc->sc_rb.rb_nrbuf) * _HME_BUFSZ;
700
701 while (totlen > 0) {
702 if (totlen >= MINCLSIZE) {
703 MCLGET(m, M_DONTWAIT);
704 if ((m->m_flags & M_EXT) == 0)
705 goto bad;
706 len = MCLBYTES;
707 }
708
709 if (m == m0) {
710 char *newdata = (char *)
711 ALIGN(m->m_data + sizeof(struct ether_header)) -
712 sizeof(struct ether_header);
713 len -= newdata - m->m_data;
714 m->m_data = newdata;
715 }
716
717 m->m_len = len = min(totlen, len);
718 memcpy(mtod(m, void *), bp, len);
719 bp += len;
720
721 totlen -= len;
722 if (totlen > 0) {
723 MGET(newm, M_DONTWAIT, MT_DATA);
724 if (newm == 0)
725 goto bad;
726 len = MLEN;
727 m = m->m_next = newm;
728 }
729 }
730
731 #ifdef INET
732 /* hardware checksum */
733 if (ifp->if_csum_flags_rx & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) {
734 struct ether_header *eh;
735 struct ip *ip;
736 struct udphdr *uh;
737 uint16_t *opts;
738 int32_t hlen, pktlen;
739 uint32_t temp;
740
741 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) {
742 pktlen = m0->m_pkthdr.len - ETHER_HDR_LEN -
743 ETHER_VLAN_ENCAP_LEN;
744 eh = (struct ether_header *) mtod(m0, void *) +
745 ETHER_VLAN_ENCAP_LEN;
746 } else {
747 pktlen = m0->m_pkthdr.len - ETHER_HDR_LEN;
748 eh = mtod(m0, struct ether_header *);
749 }
750 if (ntohs(eh->ether_type) != ETHERTYPE_IP)
751 goto swcsum;
752 ip = (struct ip *) ((char *)eh + ETHER_HDR_LEN);
753
754 /* IPv4 only */
755 if (ip->ip_v != IPVERSION)
756 goto swcsum;
757
758 hlen = ip->ip_hl << 2;
759 if (hlen < sizeof(struct ip))
760 goto swcsum;
761
762 /*
763 * bail if too short, has random trailing garbage, truncated,
764 * fragment, or has ethernet pad.
765 */
766 if ((ntohs(ip->ip_len) < hlen) || (ntohs(ip->ip_len) != pktlen)
767 || (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK)))
768 goto swcsum;
769
770 switch (ip->ip_p) {
771 case IPPROTO_TCP:
772 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4))
773 goto swcsum;
774 if (pktlen < (hlen + sizeof(struct tcphdr)))
775 goto swcsum;
776 m0->m_pkthdr.csum_flags = M_CSUM_TCPv4;
777 break;
778 case IPPROTO_UDP:
779 if (! (ifp->if_csum_flags_rx & M_CSUM_UDPv4))
780 goto swcsum;
781 if (pktlen < (hlen + sizeof(struct udphdr)))
782 goto swcsum;
783 uh = (struct udphdr *)((char *)ip + hlen);
784 /* no checksum */
785 if (uh->uh_sum == 0)
786 goto swcsum;
787 m0->m_pkthdr.csum_flags = M_CSUM_UDPv4;
788 break;
789 default:
790 goto swcsum;
791 }
792
793 /* w/ M_CSUM_NO_PSEUDOHDR, the uncomplemented sum is expected */
794 m0->m_pkthdr.csum_data = (~flags) & HME_XD_RXCKSUM;
795
796 /* if the pkt had ip options, we have to deduct them */
797 if (hlen > sizeof(struct ip)) {
798 uint32_t optsum;
799
800 optsum = 0;
801 temp = hlen - sizeof(struct ip);
802 opts = (uint16_t *)((char *)ip + sizeof(struct ip));
803
804 while (temp > 1) {
805 optsum += ntohs(*opts++);
806 temp -= 2;
807 }
808 while (optsum >> 16)
809 optsum = (optsum >> 16) + (optsum & 0xffff);
810
811 /* Deduct the ip opts sum from the hwsum. */
812 m0->m_pkthdr.csum_data += (uint16_t)~optsum;
813
814 while (m0->m_pkthdr.csum_data >> 16)
815 m0->m_pkthdr.csum_data =
816 (m0->m_pkthdr.csum_data >> 16) +
817 (m0->m_pkthdr.csum_data & 0xffff);
818 }
819
820 m0->m_pkthdr.csum_flags |= M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR;
821 } else
822 swcsum:
823 m0->m_pkthdr.csum_flags = 0;
824 #endif
825
826 return (m0);
827
828 bad:
829 m_freem(m0);
830 return (0);
831 }
832
833 /*
834 * Pass a packet to the higher levels.
835 */
836 void
837 hme_read(sc, ix, flags)
838 struct hme_softc *sc;
839 int ix;
840 u_int32_t flags;
841 {
842 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
843 struct mbuf *m;
844 int len;
845
846 len = HME_XD_DECODE_RSIZE(flags);
847 if (len <= sizeof(struct ether_header) ||
848 len > ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ?
849 ETHER_VLAN_ENCAP_LEN + ETHERMTU + sizeof(struct ether_header) :
850 ETHERMTU + sizeof(struct ether_header))) {
851 #ifdef HMEDEBUG
852 printf("%s: invalid packet size %d; dropping\n",
853 device_xname(&sc->sc_dev), len);
854 #endif
855 ifp->if_ierrors++;
856 return;
857 }
858
859 /* Pull packet off interface. */
860 m = hme_get(sc, ix, flags);
861 if (m == 0) {
862 ifp->if_ierrors++;
863 return;
864 }
865
866 ifp->if_ipackets++;
867
868 #if NBPFILTER > 0
869 /*
870 * Check if there's a BPF listener on this interface.
871 * If so, hand off the raw packet to BPF.
872 */
873 if (ifp->if_bpf)
874 bpf_mtap(ifp->if_bpf, m);
875 #endif
876
877 /* Pass the packet up. */
878 (*ifp->if_input)(ifp, m);
879 }
880
881 void
882 hme_start(ifp)
883 struct ifnet *ifp;
884 {
885 struct hme_softc *sc = (struct hme_softc *)ifp->if_softc;
886 void *txd = sc->sc_rb.rb_txd;
887 struct mbuf *m;
888 unsigned int txflags;
889 unsigned int ri, len;
890 unsigned int ntbuf = sc->sc_rb.rb_ntbuf;
891
892 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
893 return;
894
895 ri = sc->sc_rb.rb_tdhead;
896
897 for (;;) {
898 IFQ_DEQUEUE(&ifp->if_snd, m);
899 if (m == 0)
900 break;
901
902 #if NBPFILTER > 0
903 /*
904 * If BPF is listening on this interface, let it see the
905 * packet before we commit it to the wire.
906 */
907 if (ifp->if_bpf)
908 bpf_mtap(ifp->if_bpf, m);
909 #endif
910
911 #ifdef INET
912 /* collect bits for h/w csum, before hme_put frees the mbuf */
913 if (ifp->if_csum_flags_tx & (M_CSUM_TCPv4 | M_CSUM_UDPv4) &&
914 m->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) {
915 struct ether_header *eh;
916 uint16_t offset, start;
917
918 eh = mtod(m, struct ether_header *);
919 switch (ntohs(eh->ether_type)) {
920 case ETHERTYPE_IP:
921 start = ETHER_HDR_LEN;
922 break;
923 case ETHERTYPE_VLAN:
924 start = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
925 break;
926 default:
927 /* unsupported, drop it */
928 m_free(m);
929 continue;
930 }
931 start += M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data);
932 offset = M_CSUM_DATA_IPv4_OFFSET(m->m_pkthdr.csum_data)
933 + start;
934 txflags = HME_XD_TXCKSUM |
935 (offset << HME_XD_TXCSSTUFFSHIFT) |
936 (start << HME_XD_TXCSSTARTSHIFT);
937 } else
938 #endif
939 txflags = 0;
940
941 /*
942 * Copy the mbuf chain into the transmit buffer.
943 */
944 len = hme_put(sc, ri, m);
945
946 /*
947 * Initialize transmit registers and start transmission
948 */
949 HME_XD_SETFLAGS(sc->sc_pci, txd, ri,
950 HME_XD_OWN | HME_XD_SOP | HME_XD_EOP |
951 HME_XD_ENCODE_TSIZE(len) | txflags);
952
953 /*if (sc->sc_rb.rb_td_nbusy <= 0)*/
954 bus_space_write_4(sc->sc_bustag, sc->sc_etx, HME_ETXI_PENDING,
955 HME_ETX_TP_DMAWAKEUP);
956
957 if (++ri == ntbuf)
958 ri = 0;
959
960 if (++sc->sc_rb.rb_td_nbusy == ntbuf) {
961 ifp->if_flags |= IFF_OACTIVE;
962 break;
963 }
964 }
965
966 sc->sc_rb.rb_tdhead = ri;
967 }
968
969 /*
970 * Transmit interrupt.
971 */
972 int
973 hme_tint(sc)
974 struct hme_softc *sc;
975 {
976 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
977 bus_space_tag_t t = sc->sc_bustag;
978 bus_space_handle_t mac = sc->sc_mac;
979 unsigned int ri, txflags;
980
981 /*
982 * Unload collision counters
983 */
984 ifp->if_collisions +=
985 bus_space_read_4(t, mac, HME_MACI_NCCNT) +
986 bus_space_read_4(t, mac, HME_MACI_FCCNT) +
987 bus_space_read_4(t, mac, HME_MACI_EXCNT) +
988 bus_space_read_4(t, mac, HME_MACI_LTCNT);
989
990 /*
991 * then clear the hardware counters.
992 */
993 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0);
994 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0);
995 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0);
996 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0);
997
998 /* Fetch current position in the transmit ring */
999 ri = sc->sc_rb.rb_tdtail;
1000
1001 for (;;) {
1002 if (sc->sc_rb.rb_td_nbusy <= 0)
1003 break;
1004
1005 txflags = HME_XD_GETFLAGS(sc->sc_pci, sc->sc_rb.rb_txd, ri);
1006
1007 if (txflags & HME_XD_OWN)
1008 break;
1009
1010 ifp->if_flags &= ~IFF_OACTIVE;
1011 ifp->if_opackets++;
1012
1013 if (++ri == sc->sc_rb.rb_ntbuf)
1014 ri = 0;
1015
1016 --sc->sc_rb.rb_td_nbusy;
1017 }
1018
1019 /* Update ring */
1020 sc->sc_rb.rb_tdtail = ri;
1021
1022 hme_start(ifp);
1023
1024 if (sc->sc_rb.rb_td_nbusy == 0)
1025 ifp->if_timer = 0;
1026
1027 return (1);
1028 }
1029
1030 /*
1031 * Receive interrupt.
1032 */
1033 int
1034 hme_rint(sc)
1035 struct hme_softc *sc;
1036 {
1037 void *xdr = sc->sc_rb.rb_rxd;
1038 unsigned int nrbuf = sc->sc_rb.rb_nrbuf;
1039 unsigned int ri;
1040 u_int32_t flags;
1041
1042 ri = sc->sc_rb.rb_rdtail;
1043
1044 /*
1045 * Process all buffers with valid data.
1046 */
1047 for (;;) {
1048 flags = HME_XD_GETFLAGS(sc->sc_pci, xdr, ri);
1049 if (flags & HME_XD_OWN)
1050 break;
1051
1052 if (flags & HME_XD_OFL) {
1053 printf("%s: buffer overflow, ri=%d; flags=0x%x\n",
1054 device_xname(&sc->sc_dev), ri, flags);
1055 } else
1056 hme_read(sc, ri, flags);
1057
1058 /* This buffer can be used by the hardware again */
1059 HME_XD_SETFLAGS(sc->sc_pci, xdr, ri,
1060 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ));
1061
1062 if (++ri == nrbuf)
1063 ri = 0;
1064 }
1065
1066 sc->sc_rb.rb_rdtail = ri;
1067
1068 return (1);
1069 }
1070
1071 int
1072 hme_eint(sc, status)
1073 struct hme_softc *sc;
1074 u_int status;
1075 {
1076 char bits[128];
1077
1078 if ((status & HME_SEB_STAT_MIFIRQ) != 0) {
1079 bus_space_tag_t t = sc->sc_bustag;
1080 bus_space_handle_t mif = sc->sc_mif;
1081 u_int32_t cf, st, sm;
1082 cf = bus_space_read_4(t, mif, HME_MIFI_CFG);
1083 st = bus_space_read_4(t, mif, HME_MIFI_STAT);
1084 sm = bus_space_read_4(t, mif, HME_MIFI_SM);
1085 printf("%s: XXXlink status changed: cfg=%x, stat %x, sm %x\n",
1086 device_xname(&sc->sc_dev), cf, st, sm);
1087 return (1);
1088 }
1089
1090 printf("%s: status=%s\n", device_xname(&sc->sc_dev),
1091 bitmask_snprintf(status, HME_SEB_STAT_BITS, bits,sizeof(bits)));
1092 return (1);
1093 }
1094
1095 int
1096 hme_intr(v)
1097 void *v;
1098 {
1099 struct hme_softc *sc = (struct hme_softc *)v;
1100 bus_space_tag_t t = sc->sc_bustag;
1101 bus_space_handle_t seb = sc->sc_seb;
1102 u_int32_t status;
1103 int r = 0;
1104
1105 status = bus_space_read_4(t, seb, HME_SEBI_STAT);
1106
1107 if ((status & HME_SEB_STAT_ALL_ERRORS) != 0)
1108 r |= hme_eint(sc, status);
1109
1110 if ((status & (HME_SEB_STAT_TXALL | HME_SEB_STAT_HOSTTOTX)) != 0)
1111 r |= hme_tint(sc);
1112
1113 if ((status & HME_SEB_STAT_RXTOHOST) != 0)
1114 r |= hme_rint(sc);
1115
1116 #if NRND > 0
1117 rnd_add_uint32(&sc->rnd_source, status);
1118 #endif
1119
1120 return (r);
1121 }
1122
1123
1124 void
1125 hme_watchdog(ifp)
1126 struct ifnet *ifp;
1127 {
1128 struct hme_softc *sc = ifp->if_softc;
1129
1130 log(LOG_ERR, "%s: device timeout\n", device_xname(&sc->sc_dev));
1131 ++ifp->if_oerrors;
1132
1133 hme_reset(sc);
1134 }
1135
1136 /*
1137 * Initialize the MII Management Interface
1138 */
1139 void
1140 hme_mifinit(sc)
1141 struct hme_softc *sc;
1142 {
1143 bus_space_tag_t t = sc->sc_bustag;
1144 bus_space_handle_t mif = sc->sc_mif;
1145 bus_space_handle_t mac = sc->sc_mac;
1146 int instance, phy;
1147 u_int32_t v;
1148
1149 if (sc->sc_mii.mii_media.ifm_cur != NULL) {
1150 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media);
1151 phy = sc->sc_phys[instance];
1152 } else
1153 /* No media set yet, pick phy arbitrarily.. */
1154 phy = HME_PHYAD_EXTERNAL;
1155
1156 /* Configure the MIF in frame mode, no poll, current phy select */
1157 v = 0;
1158 if (phy == HME_PHYAD_EXTERNAL)
1159 v |= HME_MIF_CFG_PHY;
1160 bus_space_write_4(t, mif, HME_MIFI_CFG, v);
1161
1162 /* If an external transceiver is selected, enable its MII drivers */
1163 v = bus_space_read_4(t, mac, HME_MACI_XIF);
1164 v &= ~HME_MAC_XIF_MIIENABLE;
1165 if (phy == HME_PHYAD_EXTERNAL)
1166 v |= HME_MAC_XIF_MIIENABLE;
1167 bus_space_write_4(t, mac, HME_MACI_XIF, v);
1168 }
1169
1170 /*
1171 * MII interface
1172 */
1173 static int
1174 hme_mii_readreg(self, phy, reg)
1175 struct device *self;
1176 int phy, reg;
1177 {
1178 struct hme_softc *sc = (void *)self;
1179 bus_space_tag_t t = sc->sc_bustag;
1180 bus_space_handle_t mif = sc->sc_mif;
1181 bus_space_handle_t mac = sc->sc_mac;
1182 u_int32_t v, xif_cfg, mifi_cfg;
1183 int n;
1184
1185 /* We can at most have two PHYs */
1186 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL)
1187 return (0);
1188
1189 /* Select the desired PHY in the MIF configuration register */
1190 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG);
1191 v &= ~HME_MIF_CFG_PHY;
1192 if (phy == HME_PHYAD_EXTERNAL)
1193 v |= HME_MIF_CFG_PHY;
1194 bus_space_write_4(t, mif, HME_MIFI_CFG, v);
1195
1196 /* Enable MII drivers on external transceiver */
1197 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF);
1198 if (phy == HME_PHYAD_EXTERNAL)
1199 v |= HME_MAC_XIF_MIIENABLE;
1200 else
1201 v &= ~HME_MAC_XIF_MIIENABLE;
1202 bus_space_write_4(t, mac, HME_MACI_XIF, v);
1203
1204 #if 0
1205 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */
1206 /*
1207 * Check whether a transceiver is connected by testing
1208 * the MIF configuration register's MDI_X bits. Note that
1209 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h
1210 */
1211 mif_mdi_bit = 1 << (8 + (1 - phy));
1212 delay(100);
1213 v = bus_space_read_4(t, mif, HME_MIFI_CFG);
1214 if ((v & mif_mdi_bit) == 0)
1215 return (0);
1216 #endif
1217
1218 /* Construct the frame command */
1219 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) |
1220 HME_MIF_FO_TAMSB |
1221 (MII_COMMAND_READ << HME_MIF_FO_OPC_SHIFT) |
1222 (phy << HME_MIF_FO_PHYAD_SHIFT) |
1223 (reg << HME_MIF_FO_REGAD_SHIFT);
1224
1225 bus_space_write_4(t, mif, HME_MIFI_FO, v);
1226 for (n = 0; n < 100; n++) {
1227 DELAY(1);
1228 v = bus_space_read_4(t, mif, HME_MIFI_FO);
1229 if (v & HME_MIF_FO_TALSB) {
1230 v &= HME_MIF_FO_DATA;
1231 goto out;
1232 }
1233 }
1234
1235 v = 0;
1236 printf("%s: mii_read timeout\n", device_xname(&sc->sc_dev));
1237
1238 out:
1239 /* Restore MIFI_CFG register */
1240 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg);
1241 /* Restore XIF register */
1242 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg);
1243 return (v);
1244 }
1245
1246 static void
1247 hme_mii_writereg(self, phy, reg, val)
1248 struct device *self;
1249 int phy, reg, val;
1250 {
1251 struct hme_softc *sc = (void *)self;
1252 bus_space_tag_t t = sc->sc_bustag;
1253 bus_space_handle_t mif = sc->sc_mif;
1254 bus_space_handle_t mac = sc->sc_mac;
1255 u_int32_t v, xif_cfg, mifi_cfg;
1256 int n;
1257
1258 /* We can at most have two PHYs */
1259 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL)
1260 return;
1261
1262 /* Select the desired PHY in the MIF configuration register */
1263 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG);
1264 v &= ~HME_MIF_CFG_PHY;
1265 if (phy == HME_PHYAD_EXTERNAL)
1266 v |= HME_MIF_CFG_PHY;
1267 bus_space_write_4(t, mif, HME_MIFI_CFG, v);
1268
1269 /* Enable MII drivers on external transceiver */
1270 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF);
1271 if (phy == HME_PHYAD_EXTERNAL)
1272 v |= HME_MAC_XIF_MIIENABLE;
1273 else
1274 v &= ~HME_MAC_XIF_MIIENABLE;
1275 bus_space_write_4(t, mac, HME_MACI_XIF, v);
1276
1277 #if 0
1278 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */
1279 /*
1280 * Check whether a transceiver is connected by testing
1281 * the MIF configuration register's MDI_X bits. Note that
1282 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h
1283 */
1284 mif_mdi_bit = 1 << (8 + (1 - phy));
1285 delay(100);
1286 v = bus_space_read_4(t, mif, HME_MIFI_CFG);
1287 if ((v & mif_mdi_bit) == 0)
1288 return;
1289 #endif
1290
1291 /* Construct the frame command */
1292 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) |
1293 HME_MIF_FO_TAMSB |
1294 (MII_COMMAND_WRITE << HME_MIF_FO_OPC_SHIFT) |
1295 (phy << HME_MIF_FO_PHYAD_SHIFT) |
1296 (reg << HME_MIF_FO_REGAD_SHIFT) |
1297 (val & HME_MIF_FO_DATA);
1298
1299 bus_space_write_4(t, mif, HME_MIFI_FO, v);
1300 for (n = 0; n < 100; n++) {
1301 DELAY(1);
1302 v = bus_space_read_4(t, mif, HME_MIFI_FO);
1303 if (v & HME_MIF_FO_TALSB)
1304 goto out;
1305 }
1306
1307 printf("%s: mii_write timeout\n", device_xname(&sc->sc_dev));
1308 out:
1309 /* Restore MIFI_CFG register */
1310 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg);
1311 /* Restore XIF register */
1312 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg);
1313 }
1314
1315 static void
1316 hme_mii_statchg(dev)
1317 struct device *dev;
1318 {
1319 struct hme_softc *sc = (void *)dev;
1320 bus_space_tag_t t = sc->sc_bustag;
1321 bus_space_handle_t mac = sc->sc_mac;
1322 u_int32_t v;
1323
1324 #ifdef HMEDEBUG
1325 if (sc->sc_debug)
1326 printf("hme_mii_statchg: status change\n");
1327 #endif
1328
1329 /* Set the MAC Full Duplex bit appropriately */
1330 /* Apparently the hme chip is SIMPLEX if working in full duplex mode,
1331 but not otherwise. */
1332 v = bus_space_read_4(t, mac, HME_MACI_TXCFG);
1333 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) {
1334 v |= HME_MAC_TXCFG_FULLDPLX;
1335 sc->sc_ethercom.ec_if.if_flags |= IFF_SIMPLEX;
1336 } else {
1337 v &= ~HME_MAC_TXCFG_FULLDPLX;
1338 sc->sc_ethercom.ec_if.if_flags &= ~IFF_SIMPLEX;
1339 }
1340 sc->sc_if_flags = sc->sc_ethercom.ec_if.if_flags;
1341 bus_space_write_4(t, mac, HME_MACI_TXCFG, v);
1342 }
1343
1344 int
1345 hme_mediachange(ifp)
1346 struct ifnet *ifp;
1347 {
1348 struct hme_softc *sc = ifp->if_softc;
1349 bus_space_tag_t t = sc->sc_bustag;
1350 bus_space_handle_t mif = sc->sc_mif;
1351 bus_space_handle_t mac = sc->sc_mac;
1352 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media);
1353 int phy = sc->sc_phys[instance];
1354 int rc;
1355 u_int32_t v;
1356
1357 #ifdef HMEDEBUG
1358 if (sc->sc_debug)
1359 printf("hme_mediachange: phy = %d\n", phy);
1360 #endif
1361
1362 /* Select the current PHY in the MIF configuration register */
1363 v = bus_space_read_4(t, mif, HME_MIFI_CFG);
1364 v &= ~HME_MIF_CFG_PHY;
1365 if (phy == HME_PHYAD_EXTERNAL)
1366 v |= HME_MIF_CFG_PHY;
1367 bus_space_write_4(t, mif, HME_MIFI_CFG, v);
1368
1369 /* If an external transceiver is selected, enable its MII drivers */
1370 v = bus_space_read_4(t, mac, HME_MACI_XIF);
1371 v &= ~HME_MAC_XIF_MIIENABLE;
1372 if (phy == HME_PHYAD_EXTERNAL)
1373 v |= HME_MAC_XIF_MIIENABLE;
1374 bus_space_write_4(t, mac, HME_MACI_XIF, v);
1375
1376 if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO)
1377 return 0;
1378 return rc;
1379 }
1380
1381 /*
1382 * Process an ioctl request.
1383 */
1384 int
1385 hme_ioctl(ifp, cmd, data)
1386 struct ifnet *ifp;
1387 u_long cmd;
1388 void *data;
1389 {
1390 struct hme_softc *sc = ifp->if_softc;
1391 struct ifaddr *ifa = (struct ifaddr *)data;
1392 int s, error = 0;
1393
1394 s = splnet();
1395
1396 switch (cmd) {
1397
1398 case SIOCSIFADDR:
1399 switch (ifa->ifa_addr->sa_family) {
1400 #ifdef INET
1401 case AF_INET:
1402 if (ifp->if_flags & IFF_UP)
1403 hme_setladrf(sc);
1404 else {
1405 ifp->if_flags |= IFF_UP;
1406 error = hme_init(ifp);
1407 }
1408 arp_ifinit(ifp, ifa);
1409 break;
1410 #endif
1411 default:
1412 ifp->if_flags |= IFF_UP;
1413 error = hme_init(ifp);
1414 break;
1415 }
1416 break;
1417
1418 case SIOCSIFFLAGS:
1419 #ifdef HMEDEBUG
1420 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0;
1421 #endif
1422
1423 if ((ifp->if_flags & IFF_UP) == 0 &&
1424 (ifp->if_flags & IFF_RUNNING) != 0) {
1425 /*
1426 * If interface is marked down and it is running, then
1427 * stop it.
1428 */
1429 hme_stop(sc, false);
1430 ifp->if_flags &= ~IFF_RUNNING;
1431 } else if ((ifp->if_flags & IFF_UP) != 0 &&
1432 (ifp->if_flags & IFF_RUNNING) == 0) {
1433 /*
1434 * If interface is marked up and it is stopped, then
1435 * start it.
1436 */
1437 error = hme_init(ifp);
1438 } else if ((ifp->if_flags & IFF_UP) != 0) {
1439 /*
1440 * If setting debug or promiscuous mode, do not reset
1441 * the chip; for everything else, call hme_init()
1442 * which will trigger a reset.
1443 */
1444 #define RESETIGN (IFF_CANTCHANGE | IFF_DEBUG)
1445 if (ifp->if_flags != sc->sc_if_flags) {
1446 if ((ifp->if_flags & (~RESETIGN))
1447 == (sc->sc_if_flags & (~RESETIGN)))
1448 hme_setladrf(sc);
1449 else
1450 error = hme_init(ifp);
1451 }
1452 #undef RESETIGN
1453 }
1454
1455 if (sc->sc_ec_capenable != sc->sc_ethercom.ec_capenable)
1456 error = hme_init(ifp);
1457
1458 break;
1459
1460 default:
1461 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET)
1462 break;
1463
1464 error = 0;
1465
1466 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI)
1467 ;
1468 else if (ifp->if_flags & IFF_RUNNING) {
1469 /*
1470 * Multicast list has changed; set the hardware filter
1471 * accordingly.
1472 */
1473 hme_setladrf(sc);
1474 }
1475 break;
1476 }
1477
1478 sc->sc_if_flags = ifp->if_flags;
1479 splx(s);
1480 return (error);
1481 }
1482
1483 void
1484 hme_shutdown(arg)
1485 void *arg;
1486 {
1487
1488 hme_stop((struct hme_softc *)arg, false);
1489 }
1490
1491 /*
1492 * Set up the logical address filter.
1493 */
1494 void
1495 hme_setladrf(sc)
1496 struct hme_softc *sc;
1497 {
1498 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1499 struct ether_multi *enm;
1500 struct ether_multistep step;
1501 struct ethercom *ec = &sc->sc_ethercom;
1502 bus_space_tag_t t = sc->sc_bustag;
1503 bus_space_handle_t mac = sc->sc_mac;
1504 u_char *cp;
1505 u_int32_t crc;
1506 u_int32_t hash[4];
1507 u_int32_t v;
1508 int len;
1509
1510 /* Clear hash table */
1511 hash[3] = hash[2] = hash[1] = hash[0] = 0;
1512
1513 /* Get current RX configuration */
1514 v = bus_space_read_4(t, mac, HME_MACI_RXCFG);
1515
1516 if ((ifp->if_flags & IFF_PROMISC) != 0) {
1517 /* Turn on promiscuous mode; turn off the hash filter */
1518 v |= HME_MAC_RXCFG_PMISC;
1519 v &= ~HME_MAC_RXCFG_HENABLE;
1520 ifp->if_flags |= IFF_ALLMULTI;
1521 goto chipit;
1522 }
1523
1524 /* Turn off promiscuous mode; turn on the hash filter */
1525 v &= ~HME_MAC_RXCFG_PMISC;
1526 v |= HME_MAC_RXCFG_HENABLE;
1527
1528 /*
1529 * Set up multicast address filter by passing all multicast addresses
1530 * through a crc generator, and then using the high order 6 bits as an
1531 * index into the 64 bit logical address filter. The high order bit
1532 * selects the word, while the rest of the bits select the bit within
1533 * the word.
1534 */
1535
1536 ETHER_FIRST_MULTI(step, ec, enm);
1537 while (enm != NULL) {
1538 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
1539 /*
1540 * We must listen to a range of multicast addresses.
1541 * For now, just accept all multicasts, rather than
1542 * trying to set only those filter bits needed to match
1543 * the range. (At this time, the only use of address
1544 * ranges is for IP multicast routing, for which the
1545 * range is big enough to require all bits set.)
1546 */
1547 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff;
1548 ifp->if_flags |= IFF_ALLMULTI;
1549 goto chipit;
1550 }
1551
1552 cp = enm->enm_addrlo;
1553 crc = 0xffffffff;
1554 for (len = sizeof(enm->enm_addrlo); --len >= 0;) {
1555 int octet = *cp++;
1556 int i;
1557
1558 #define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */
1559 for (i = 0; i < 8; i++) {
1560 if ((crc & 1) ^ (octet & 1)) {
1561 crc >>= 1;
1562 crc ^= MC_POLY_LE;
1563 } else {
1564 crc >>= 1;
1565 }
1566 octet >>= 1;
1567 }
1568 }
1569 /* Just want the 6 most significant bits. */
1570 crc >>= 26;
1571
1572 /* Set the corresponding bit in the filter. */
1573 hash[crc >> 4] |= 1 << (crc & 0xf);
1574
1575 ETHER_NEXT_MULTI(step, enm);
1576 }
1577
1578 ifp->if_flags &= ~IFF_ALLMULTI;
1579
1580 chipit:
1581 /* Now load the hash table into the chip */
1582 bus_space_write_4(t, mac, HME_MACI_HASHTAB0, hash[0]);
1583 bus_space_write_4(t, mac, HME_MACI_HASHTAB1, hash[1]);
1584 bus_space_write_4(t, mac, HME_MACI_HASHTAB2, hash[2]);
1585 bus_space_write_4(t, mac, HME_MACI_HASHTAB3, hash[3]);
1586 bus_space_write_4(t, mac, HME_MACI_RXCFG, v);
1587 }
1588
1589 /*
1590 * Routines for accessing the transmit and receive buffers.
1591 * The various CPU and adapter configurations supported by this
1592 * driver require three different access methods for buffers
1593 * and descriptors:
1594 * (1) contig (contiguous data; no padding),
1595 * (2) gap2 (two bytes of data followed by two bytes of padding),
1596 * (3) gap16 (16 bytes of data followed by 16 bytes of padding).
1597 */
1598
1599 #if 0
1600 /*
1601 * contig: contiguous data with no padding.
1602 *
1603 * Buffers may have any alignment.
1604 */
1605
1606 void
1607 hme_copytobuf_contig(sc, from, ri, len)
1608 struct hme_softc *sc;
1609 void *from;
1610 int ri, len;
1611 {
1612 volatile void *buf = sc->sc_rb.rb_txbuf + (ri * _HME_BUFSZ);
1613
1614 /*
1615 * Just call memcpy() to do the work.
1616 */
1617 memcpy(buf, from, len);
1618 }
1619
1620 void
1621 hme_copyfrombuf_contig(sc, to, boff, len)
1622 struct hme_softc *sc;
1623 void *to;
1624 int boff, len;
1625 {
1626 volatile void *buf = sc->sc_rb.rb_rxbuf + (ri * _HME_BUFSZ);
1627
1628 /*
1629 * Just call memcpy() to do the work.
1630 */
1631 memcpy(to, buf, len);
1632 }
1633 #endif
Cache object: 390959cb3e06c9d4bdf1e91a527fc078
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