The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/hscx.h

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    1 /*
    2  *   Copyright (c) 1996, 1998 Gary Jennejohn. All rights reserved.
    3  *
    4  *   Redistribution and use in source and binary forms, with or without
    5  *   modification, are permitted provided that the following conditions
    6  *   are met:
    7  *
    8  *   1. Redistributions of source code must retain the above copyright
    9  *      notice, this list of conditions and the following disclaimer.
   10  *   2. Redistributions in binary form must reproduce the above copyright
   11  *      notice, this list of conditions and the following disclaimer in the
   12  *      documentation and/or other materials provided with the distribution.
   13  *   3. Neither the name of the author nor the names of any co-contributors
   14  *      may be used to endorse or promote products derived from this software
   15  *      without specific prior written permission.
   16  *   4. Altered versions must be plainly marked as such, and must not be
   17  *      misrepresented as being the original software and/or documentation.
   18  *
   19  *   THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   20  *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   21  *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   22  *   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   23  *   FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   24  *   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   25  *   OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   26  *   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   27  *   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   28  *   OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   29  *   SUCH DAMAGE.
   30  *
   31  *---------------------------------------------------------------------------
   32  *
   33  *      $Id: hscx.h,v 1.3 2005/12/11 12:21:26 christos Exp $
   34  *
   35  *      last edit-date: [Sun Feb 14 10:26:56 1999]
   36  *
   37  *      -hm     added AVM config register defs
   38  *      -hm     split up for rewrite of Siemens chipset driver
   39  *
   40  *---------------------------------------------------------------------------
   41  */
   42 
   43 #ifndef I4B_HSCX_H_
   44 #define I4B_HSCX_H_
   45 
   46 enum HSCX_VERSIONS {
   47         HSCX_VA1,       /* 82525 A1  */
   48         HSCX_UNKN1,     /* unknown 1 */
   49         HSCX_VA2,       /* 82525 A2  */
   50         HSCX_UNKN3,     /* unknown 3 */
   51         HSCX_VA3,       /* 82525 A3  */
   52         HSCX_V21,       /* 82525 2.1 */
   53         HSCX_UNKN       /* unknown version */
   54 };
   55 
   56 #define HSCX_CH_A       0       /* channel A */
   57 #define HSCX_CH_B       1       /* channel B */
   58 
   59 #define HSCX_FIFO_LEN   32      /* 32 bytes FIFO on chip */
   60 
   61 /*
   62  * definitions of registers and bits for the HSCX ISDN chip.
   63  */
   64 
   65 typedef struct hscx_reg {
   66 
   67         /* 32 byte deep FIFO always first */
   68 
   69         unsigned char hscx_fifo [HSCX_FIFO_LEN];
   70 
   71         /* most registers can be read/written, but have different names */
   72         /* so define a union with read/write names to make that clear */
   73 
   74         union {
   75                 struct {
   76                         unsigned char hscx_ista;
   77                         unsigned char hscx_star;
   78                         unsigned char hscx_mode;
   79                         unsigned char hscx_timr;
   80                         unsigned char hscx_exir;
   81                         unsigned char hscx_rbcl;
   82                         unsigned char dummy_26;
   83                         unsigned char hscx_rsta;
   84                         unsigned char hscx_ral1;
   85                         unsigned char hscx_rhcr;
   86                         unsigned char dummy_2a;
   87                         unsigned char dummy_2b;
   88                         unsigned char hscx_ccr2;
   89                         unsigned char hscx_rbch;
   90                         unsigned char hscx_vstr;
   91                         unsigned char hscx_ccr;
   92                         unsigned char dummy_30;
   93                         unsigned char dummy_31;
   94                         unsigned char dummy_32;
   95                         unsigned char dummy_33;
   96                 } hscx_r;
   97                 struct {
   98                         unsigned char hscx_mask;
   99                         unsigned char hscx_cmdr;
  100                         unsigned char hscx_mode;
  101                         unsigned char hscx_timr;
  102                         unsigned char hscx_xad1;
  103                         unsigned char hscx_xad2;
  104                         unsigned char hscx_rah1;
  105                         unsigned char hscx_rah2;
  106                         unsigned char hscx_ral1;
  107                         unsigned char hscx_ral2;
  108                         unsigned char hscx_xbcl;
  109                         unsigned char hscx_bgr;
  110                         unsigned char hscx_ccr2;
  111                         unsigned char hscx_xbch;
  112                         unsigned char hscx_rlcr;
  113                         unsigned char hscx_ccr1;
  114                         unsigned char hscx_tsax;
  115                         unsigned char hscx_tsar;
  116                         unsigned char hscx_xccr;
  117                         unsigned char hscx_rccr;
  118                 } hscx_w;
  119         } hscx_rw;
  120 } hscx_reg_t;
  121 
  122 #define REG_OFFSET(type, field) (int)(&(((type *)0)->field))
  123 
  124 /* HSCX read registers */
  125 
  126 #define h_ista hscx_rw.hscx_r.hscx_ista
  127 #define H_ISTA REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_ista)
  128 #define h_star hscx_rw.hscx_r.hscx_star
  129 #define H_STAR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_star)
  130 #define h_mode hscx_rw.hscx_r.hscx_mode
  131 #define H_MODE REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_mode)
  132 #define h_timr hscx_rw.hscx_r.hscx_timr
  133 #define H_TIMR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_timr)
  134 #define h_exir hscx_rw.hscx_r.hscx_exir
  135 #define H_EXIR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_exir)
  136 #define h_rbcl hscx_rw.hscx_r.hscx_rbcl
  137 #define H_RBCL REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_rbcl)
  138 #define h_rsta hscx_rw.hscx_r.hscx_rsta
  139 #define H_RSTA REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_rsta)
  140 #define h_ral1 hscx_rw.hscx_r.hscx_ral1
  141 #define H_RAL1 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_ral1)
  142 #define h_rhcr hscx_rw.hscx_r.hscx_rhcr
  143 #define H_RHCR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_rhcr)
  144 #define h_ccr2 hscx_rw.hscx_r.hscx_ccr2
  145 #define H_CCR2 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_ccr2)
  146 #define h_rbch hscx_rw.hscx_r.hscx_rbch
  147 #define H_RBCH REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_rbch)
  148 #define h_vstr hscx_rw.hscx_r.hscx_vstr
  149 #define H_VSTR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_vstr)
  150 #define h_ccr hscx_rw.hscx_r.hscx_ccr
  151 #define H_CCR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_ccr)
  152 
  153 /* HSCX write registers - for hscx_mode, hscx_timr, hscx_ral1, hscx_ccr2 */
  154 /* see read registers */
  155 
  156 #define h_mask hscx_rw.hscx_w.hscx_mask
  157 #define H_MASK REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_mask)
  158 #define h_cmdr hscx_rw.hscx_w.hscx_cmdr
  159 #define H_CMDR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_cmdr)
  160 #define h_xad1 hscx_rw.hscx_w.hscx_xad1
  161 #define H_XAD1 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_xad1)
  162 #define h_xad2 hscx_rw.hscx_w.hscx_xad2
  163 #define H_XAD2 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_xad2)
  164 #define h_rah1 hscx_rw.hscx_w.hscx_rah1
  165 #define H_RAH1 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_rah1)
  166 #define h_rah2 hscx_rw.hscx_w.hscx_rah2
  167 #define H_RAH2 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_rah2)
  168 #define h_ral2 hscx_rw.hscx_w.hscx_ral2
  169 #define H_RAL2 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_ral2)
  170 #define h_xbcl hscx_rw.hscx_w.hscx_xbcl
  171 #define H_XBCL REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_xbcl)
  172 #define h_bgr hscx_rw.hscx_w.hscx_bgr
  173 #define H_BGR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_bgr)
  174 #define h_xbch hscx_rw.hscx_w.hscx_xbch
  175 #define H_XBCH REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_xbch)
  176 #define h_rlcr hscx_rw.hscx_w.hscx_rlcr
  177 #define H_RLCR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_rlcr)
  178 #define h_ccr1 hscx_rw.hscx_w.hscx_ccr1
  179 #define H_CCR1 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_ccr1)
  180 #define h_tsax hscx_rw.hscx_w.hscx_tsax
  181 #define H_TSAX REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_tsax)
  182 #define h_tsar hscx_rw.hscx_w.hscx_tsar
  183 #define H_TSAR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_tsar)
  184 #define h_xccr hscx_rw.hscx_w.hscx_xccr
  185 #define H_XCCR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_xccr)
  186 #define h_rccr hscx_rw.hscx_w.hscx_rccr
  187 #define H_RCCR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_rccr)
  188 
  189 #define HSCX_ISTA_RME  0x80
  190 #define HSCX_ISTA_RPF  0x40
  191 #define HSCX_ISTA_RSC  0x20
  192 #define HSCX_ISTA_XPR  0x10
  193 #define HSCX_ISTA_TIN  0x08
  194 #define HSCX_ISTA_ICA  0x04
  195 #define HSCX_ISTA_EXA  0x02
  196 #define HSCX_ISTA_EXB  0x01
  197 
  198 #define HSCX_MASK_RME  0x80
  199 #define HSCX_MASK_RPF  0x40
  200 #define HSCX_MASK_RSC  0x20
  201 #define HSCX_MASK_XPR  0x10
  202 #define HSCX_MASK_TIN  0x08
  203 #define HSCX_MASK_ICA  0x04
  204 #define HSCX_MASK_EXA  0x02
  205 #define HSCX_MASK_EXB  0x01
  206 
  207 #define HSCX_EXIR_XMR  0x80
  208 #define HSCX_EXIR_XDU  0x40
  209 #define HSCX_EXIR_PCE  0x20
  210 #define HSCX_EXIR_RFO  0x10
  211 #define HSCX_EXIR_CSC  0x08
  212 #define HSCX_EXIR_RFS  0x04
  213 
  214 /* the other bits are always 0 */
  215 
  216 #define HSCX_STAR_XDOV 0x80
  217 #define HSCX_STAR_XFW  0x40
  218 #define HSCX_STAR_XRNR 0x20
  219 #define HSCX_STAR_RRNR 0x10
  220 #define HSCX_STAR_RLI  0x08
  221 #define HSCX_STAR_CEC  0x04
  222 #define HSCX_STAR_CTS  0x02
  223 #define HSCX_STAR_WFA  0x01
  224 
  225 #define HSCX_CMDR_RMC  0x80
  226 #define HSCX_CMDR_RHR  0x40
  227 /* also known as XREP in transparent mode */
  228 #define HSCX_CMDR_RNR  0x20
  229 #define HSCX_CMDR_STI  0x10
  230 #define HSCX_CMDR_XTF  0x08
  231 #define HSCX_CMDR_XIF  0x04
  232 #define HSCX_CMDR_XME  0x02
  233 #define HSCX_CMDR_XRES 0x01
  234 
  235 #define HSCX_MODE_MDS1 0x80
  236 #define HSCX_MODE_MDS0 0x40
  237 #define HSCX_MODE_ADM  0x20
  238 #define HSCX_MODE_TMD  0x10
  239 #define HSCX_MODE_RAC  0x08
  240 #define HSCX_MODE_RTS  0x04
  241 #define HSCX_MODE_TRS  0x02
  242 #define HSCX_MODE_TLP  0x01
  243 
  244 #define HSCX_RSTA_VFR  0x80
  245 #define HSCX_RSTA_RDO  0x40
  246 #define HSCX_RSTA_CRC  0x20
  247 #define HSCX_RSTA_RAB  0x10
  248 #define HSCX_RSTA_HA1  0x08
  249 #define HSCX_RSTA_HA0  0x04
  250 #define HSCX_RSTA_CR   0x02
  251 #define HSCX_RSTA_LA   0x01
  252 
  253 #define HSCX_RSTA_MASK 0xf0     /* the interesting ones */
  254 
  255 /* only used in DMA mode */
  256 #define HSCX_XBCH_DMA  0x80
  257 #define HSCX_XBCH_NRM  0x40
  258 #define HSCX_XBCH_CAS  0x20
  259 #define HSCX_XBCH_XC   0x10
  260 /* the rest are bits 11 thru 8 of the byte count */
  261 
  262 #define HSCX_RBCH_DMA  0x80
  263 #define HSCX_RBCH_NRM  0x40
  264 #define HSCX_RBCH_CAS  0x20
  265 #define HSCX_RBCH_OV   0x10
  266 /* the rest are bits 11 thru 8 of the byte count */
  267 
  268 #define HSCX_VSTR_CD   0x80
  269 /* bits 6 thru 4 are 0 */
  270 /* bits 3 thru 0 are the version number */
  271 
  272 #define HSCX_RLCR_RC   0x80
  273 /* the rest of the bits are used to set the received length */
  274 
  275 #define HSCX_CCR1_PU   0x80
  276 /* bits 6 and 5 are SC1 SC0 */
  277 #define HSCX_CCR1_ODS  0x10
  278 #define HSCX_CCR1_ITF  0x08
  279 #define HSCX_CCR1_CM2  0x04
  280 #define HSCX_CCR1_CM1  0x02
  281 #define HSCX_CCR1_CM0  0x01
  282 
  283 /* for clock mode 5 */
  284 #define HSCX_CCR2_SOC2 0x80
  285 #define HSCX_CCR2_SOC1 0x40
  286 #define HSCX_CCR2_XCS0 0x20
  287 #define HSCX_CCR2_RCS0 0x10
  288 #define HSCX_CCR2_TIO  0x08
  289 #define HSCX_CCR2_CIE  0x04
  290 #define HSCX_CCR2_RIE  0x02
  291 #define HSCX_CCR2_DIV  0x01
  292 
  293 /* bits 7 thru 2 are TSNX */
  294 #define HSCX_TSAX_XCS2 0x02
  295 #define HSCX_TSAX_XCS1 0x01
  296 
  297 /* bits 7 thru 2 are TSNR */
  298 #define HSCX_TSAR_RCS2 0x02
  299 #define HSCX_TSAR_RCS1 0x01
  300 
  301 #endif /* I4B_HSCX_H_ */

Cache object: a2b9ad9894d1e44c2934aa1914e08d4d


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