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sys/dev/ic/i82365.c
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1 /* $NetBSD: i82365.c,v 1.77 2003/12/28 01:21:37 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Christian E. Hopps. All rights reserved. 5 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Marc Horowitz. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: i82365.c,v 1.77 2003/12/28 01:21:37 christos Exp $"); 35 36 #define PCICDEBUG 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 #include <sys/extent.h> 42 #include <sys/kernel.h> 43 #include <sys/malloc.h> 44 #include <sys/kthread.h> 45 46 #include <machine/bus.h> 47 #include <machine/intr.h> 48 49 #include <dev/pcmcia/pcmciareg.h> 50 #include <dev/pcmcia/pcmciavar.h> 51 52 #include <dev/ic/i82365reg.h> 53 #include <dev/ic/i82365var.h> 54 55 #include "locators.h" 56 57 #ifdef PCICDEBUG 58 int pcic_debug = 0; 59 #define DPRINTF(arg) if (pcic_debug) printf arg; 60 #else 61 #define DPRINTF(arg) 62 #endif 63 64 /* 65 * Individual drivers will allocate their own memory and io regions. Memory 66 * regions must be a multiple of 4k, aligned on a 4k boundary. 67 */ 68 69 #define PCIC_MEM_ALIGN PCIC_MEM_PAGESIZE 70 71 void pcic_attach_socket __P((struct pcic_handle *)); 72 void pcic_attach_socket_finish __P((struct pcic_handle *)); 73 74 int pcic_submatch __P((struct device *, struct cfdata *, void *)); 75 int pcic_print __P((void *arg, const char *pnp)); 76 int pcic_intr_socket __P((struct pcic_handle *)); 77 void pcic_poll_intr __P((void *)); 78 79 void pcic_attach_card __P((struct pcic_handle *)); 80 void pcic_detach_card __P((struct pcic_handle *, int)); 81 void pcic_deactivate_card __P((struct pcic_handle *)); 82 83 void pcic_chip_do_mem_map __P((struct pcic_handle *, int)); 84 void pcic_chip_do_io_map __P((struct pcic_handle *, int)); 85 86 void pcic_create_event_thread __P((void *)); 87 void pcic_event_thread __P((void *)); 88 89 void pcic_queue_event __P((struct pcic_handle *, int)); 90 void pcic_power __P((int, void *)); 91 92 static void pcic_wait_ready __P((struct pcic_handle *)); 93 static void pcic_delay __P((struct pcic_handle *, int, const char *)); 94 95 static u_int8_t st_pcic_read __P((struct pcic_handle *, int)); 96 static void st_pcic_write __P((struct pcic_handle *, int, u_int8_t)); 97 98 int 99 pcic_ident_ok(ident) 100 int ident; 101 { 102 /* this is very empirical and heuristic */ 103 104 if ((ident == 0) || (ident == 0xff) || (ident & PCIC_IDENT_ZERO)) 105 return (0); 106 107 if ((ident & PCIC_IDENT_REV_MASK) == 0) 108 return (0); 109 110 if ((ident & PCIC_IDENT_IFTYPE_MASK) != PCIC_IDENT_IFTYPE_MEM_AND_IO) { 111 #ifdef DIAGNOSTIC 112 printf("pcic: does not support memory and I/O cards, " 113 "ignored (ident=%0x)\n", ident); 114 #endif 115 return (0); 116 } 117 118 return (1); 119 } 120 121 int 122 pcic_vendor(h) 123 struct pcic_handle *h; 124 { 125 int reg; 126 int vendor; 127 128 reg = pcic_read(h, PCIC_IDENT); 129 130 if ((reg & PCIC_IDENT_REV_MASK) == 0) 131 return (PCIC_VENDOR_NONE); 132 133 switch (reg) { 134 case 0x00: 135 case 0xff: 136 return (PCIC_VENDOR_NONE); 137 case PCIC_IDENT_ID_INTEL0: 138 vendor = PCIC_VENDOR_I82365SLR0; 139 break; 140 case PCIC_IDENT_ID_INTEL1: 141 vendor = PCIC_VENDOR_I82365SLR1; 142 break; 143 case PCIC_IDENT_ID_INTEL2: 144 vendor = PCIC_VENDOR_I82365SL_DF; 145 break; 146 case PCIC_IDENT_ID_IBM1: 147 case PCIC_IDENT_ID_IBM2: 148 vendor = PCIC_VENDOR_IBM; 149 break; 150 case PCIC_IDENT_ID_IBM3: 151 vendor = PCIC_VENDOR_IBM_KING; 152 break; 153 default: 154 vendor = PCIC_VENDOR_UNKNOWN; 155 break; 156 } 157 158 if (vendor == PCIC_VENDOR_I82365SLR0 || 159 vendor == PCIC_VENDOR_I82365SLR1) { 160 /* 161 * Check for Cirrus PD67xx. 162 * the chip_id of the cirrus toggles between 11 and 00 after a 163 * write. weird. 164 */ 165 pcic_write(h, PCIC_CIRRUS_CHIP_INFO, 0); 166 reg = pcic_read(h, -1); 167 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 168 PCIC_CIRRUS_CHIP_INFO_CHIP_ID) { 169 reg = pcic_read(h, -1); 170 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0) 171 return (PCIC_VENDOR_CIRRUS_PD67XX); 172 } 173 174 /* 175 * check for Ricoh RF5C[23]96 176 */ 177 reg = pcic_read(h, PCIC_RICOH_REG_CHIP_ID); 178 switch (reg) { 179 case PCIC_RICOH_CHIP_ID_5C296: 180 return (PCIC_VENDOR_RICOH_5C296); 181 case PCIC_RICOH_CHIP_ID_5C396: 182 return (PCIC_VENDOR_RICOH_5C396); 183 } 184 } 185 186 return (vendor); 187 } 188 189 char * 190 pcic_vendor_to_string(vendor) 191 int vendor; 192 { 193 switch (vendor) { 194 case PCIC_VENDOR_I82365SLR0: 195 return ("Intel 82365SL Revision 0"); 196 case PCIC_VENDOR_I82365SLR1: 197 return ("Intel 82365SL Revision 1"); 198 case PCIC_VENDOR_CIRRUS_PD67XX: 199 return ("Cirrus PD6710/2X"); 200 case PCIC_VENDOR_I82365SL_DF: 201 return ("Intel 82365SL-DF"); 202 case PCIC_VENDOR_RICOH_5C296: 203 return ("Ricoh RF5C296"); 204 case PCIC_VENDOR_RICOH_5C396: 205 return ("Ricoh RF5C396"); 206 case PCIC_VENDOR_IBM: 207 return ("IBM PCIC"); 208 case PCIC_VENDOR_IBM_KING: 209 return ("IBM KING"); 210 } 211 212 return ("Unknown controller"); 213 } 214 215 void 216 pcic_attach(sc) 217 struct pcic_softc *sc; 218 { 219 int i, reg, chip, socket; 220 struct pcic_handle *h; 221 222 DPRINTF(("pcic ident regs:")); 223 224 lockinit(&sc->sc_pcic_lock, PWAIT, "pciclk", 0, 0); 225 226 /* find and configure for the available sockets */ 227 for (i = 0; i < PCIC_NSLOTS; i++) { 228 h = &sc->handle[i]; 229 chip = i / 2; 230 socket = i % 2; 231 232 h->ph_parent = (struct device *)sc; 233 h->chip = chip; 234 h->sock = chip * PCIC_CHIP_OFFSET + socket * PCIC_SOCKET_OFFSET; 235 h->laststate = PCIC_LASTSTATE_EMPTY; 236 /* initialize pcic_read and pcic_write functions */ 237 h->ph_read = st_pcic_read; 238 h->ph_write = st_pcic_write; 239 h->ph_bus_t = sc->iot; 240 h->ph_bus_h = sc->ioh; 241 h->flags = 0; 242 243 /* need to read vendor -- for cirrus to report no xtra chip */ 244 if (socket == 0) 245 h->vendor = (h+1)->vendor = pcic_vendor(h); 246 247 switch (h->vendor) { 248 case PCIC_VENDOR_NONE: 249 /* no chip */ 250 continue; 251 case PCIC_VENDOR_CIRRUS_PD67XX: 252 reg = pcic_read(h, PCIC_CIRRUS_CHIP_INFO); 253 if (socket == 0 || 254 (reg & PCIC_CIRRUS_CHIP_INFO_SLOTS)) 255 h->flags = PCIC_FLAG_SOCKETP; 256 break; 257 default: 258 /* 259 * During the socket probe, read the ident register 260 * twice. I don't understand why, but sometimes the 261 * clone chips in hpcmips boxes read all-0s the first 262 * time. -- mycroft 263 */ 264 reg = pcic_read(h, PCIC_IDENT); 265 DPRINTF(("socket %d ident reg 0x%02x\n", i, reg)); 266 reg = pcic_read(h, PCIC_IDENT); 267 DPRINTF(("socket %d ident reg 0x%02x\n", i, reg)); 268 if (pcic_ident_ok(reg)) 269 h->flags = PCIC_FLAG_SOCKETP; 270 break; 271 } 272 } 273 274 for (i = 0; i < PCIC_NSLOTS; i++) { 275 h = &sc->handle[i]; 276 277 if (h->flags & PCIC_FLAG_SOCKETP) { 278 SIMPLEQ_INIT(&h->events); 279 280 /* disable interrupts and leave socket in reset */ 281 pcic_write(h, PCIC_CSC_INTR, 0); 282 pcic_write(h, PCIC_INTR, 0); 283 (void) pcic_read(h, PCIC_CSC); 284 } 285 } 286 287 /* print detected info */ 288 for (i = 0; i < PCIC_NSLOTS; i += 2) { 289 h = &sc->handle[i]; 290 chip = i / 2; 291 292 if (h->vendor == PCIC_VENDOR_NONE) 293 continue; 294 295 aprint_normal("%s: controller %d (%s) has ", sc->dev.dv_xname, 296 chip, pcic_vendor_to_string(sc->handle[i].vendor)); 297 298 if ((h->flags & PCIC_FLAG_SOCKETP) && 299 ((h+1)->flags & PCIC_FLAG_SOCKETP)) 300 aprint_normal("sockets A and B\n"); 301 else if (h->flags & PCIC_FLAG_SOCKETP) 302 aprint_normal("socket A only\n"); 303 else if ((h+1)->flags & PCIC_FLAG_SOCKETP) 304 aprint_normal("socket B only\n"); 305 else 306 aprint_normal("no sockets\n"); 307 } 308 } 309 310 /* 311 * attach the sockets before we know what interrupts we have 312 */ 313 void 314 pcic_attach_sockets(sc) 315 struct pcic_softc *sc; 316 { 317 int i; 318 319 for (i = 0; i < PCIC_NSLOTS; i++) 320 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 321 pcic_attach_socket(&sc->handle[i]); 322 } 323 324 void 325 pcic_power(why, arg) 326 int why; 327 void *arg; 328 { 329 struct pcic_handle *h = (struct pcic_handle *)arg; 330 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 331 int reg; 332 333 DPRINTF(("%s: power: why %d\n", h->ph_parent->dv_xname, why)); 334 335 if (h->flags & PCIC_FLAG_SOCKETP) { 336 if ((why == PWR_RESUME) && 337 (pcic_read(h, PCIC_CSC_INTR) == 0)) { 338 #ifdef PCICDEBUG 339 char bitbuf[64]; 340 #endif 341 reg = PCIC_CSC_INTR_CD_ENABLE; 342 if (sc->irq != -1) 343 reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT; 344 pcic_write(h, PCIC_CSC_INTR, reg); 345 DPRINTF(("%s: CSC_INTR was zero; reset to %s\n", 346 sc->dev.dv_xname, 347 bitmask_snprintf(pcic_read(h, PCIC_CSC_INTR), 348 PCIC_CSC_INTR_FORMAT, 349 bitbuf, sizeof(bitbuf)))); 350 } 351 352 /* 353 * check for card insertion or removal during suspend period. 354 * XXX: the code can't cope with card swap (remove then insert). 355 * how can we detect such situation? 356 */ 357 if (why == PWR_RESUME) 358 (void)pcic_intr_socket(h); 359 } 360 } 361 362 363 /* 364 * attach a socket -- we don't know about irqs yet 365 */ 366 void 367 pcic_attach_socket(h) 368 struct pcic_handle *h; 369 { 370 struct pcmciabus_attach_args paa; 371 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 372 373 /* initialize the rest of the handle */ 374 375 h->shutdown = 0; 376 h->memalloc = 0; 377 h->ioalloc = 0; 378 h->ih_irq = 0; 379 380 /* now, config one pcmcia device per socket */ 381 382 paa.paa_busname = "pcmcia"; 383 paa.pct = (pcmcia_chipset_tag_t) sc->pct; 384 paa.pch = (pcmcia_chipset_handle_t) h; 385 paa.iobase = sc->iobase; 386 paa.iosize = sc->iosize; 387 388 h->pcmcia = config_found_sm(&sc->dev, &paa, pcic_print, pcic_submatch); 389 if (h->pcmcia == NULL) { 390 h->flags &= ~PCIC_FLAG_SOCKETP; 391 return; 392 } 393 394 /* 395 * queue creation of a kernel thread to handle insert/removal events. 396 */ 397 #ifdef DIAGNOSTIC 398 if (h->event_thread != NULL) 399 panic("pcic_attach_socket: event thread"); 400 #endif 401 config_pending_incr(); 402 kthread_create(pcic_create_event_thread, h); 403 } 404 405 /* 406 * now finish attaching the sockets, we are ready to allocate 407 * interrupts 408 */ 409 void 410 pcic_attach_sockets_finish(sc) 411 struct pcic_softc *sc; 412 { 413 int i; 414 415 for (i = 0; i < PCIC_NSLOTS; i++) 416 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 417 pcic_attach_socket_finish(&sc->handle[i]); 418 } 419 420 /* 421 * finishing attaching the socket. Interrupts may now be on 422 * if so expects the pcic interrupt to be blocked 423 */ 424 void 425 pcic_attach_socket_finish(h) 426 struct pcic_handle *h; 427 { 428 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 429 int reg, intr; 430 431 DPRINTF(("%s: attach finish socket %ld\n", h->ph_parent->dv_xname, 432 (long) (h - &sc->handle[0]))); 433 434 /* 435 * Set up a powerhook to ensure it continues to interrupt on 436 * card detect even after suspend. 437 * (this works around a bug seen in suspend-to-disk on the 438 * Sony VAIO Z505; on resume, the CSC_INTR state is not preserved). 439 */ 440 powerhook_establish(pcic_power, h); 441 442 /* enable interrupts on card detect, poll for them if no irq avail */ 443 reg = PCIC_CSC_INTR_CD_ENABLE; 444 if (sc->irq == -1) { 445 if (sc->poll_established == 0) { 446 callout_init(&sc->poll_ch); 447 callout_reset(&sc->poll_ch, hz / 2, pcic_poll_intr, sc); 448 sc->poll_established = 1; 449 } 450 } else 451 reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT; 452 pcic_write(h, PCIC_CSC_INTR, reg); 453 454 /* steer above mgmt interrupt to configured place */ 455 intr = pcic_read(h, PCIC_INTR); 456 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE); 457 if (sc->irq == 0) 458 intr |= PCIC_INTR_ENABLE; 459 pcic_write(h, PCIC_INTR, intr); 460 461 /* power down the socket */ 462 pcic_write(h, PCIC_PWRCTL, 0); 463 464 /* zero out the address windows */ 465 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 466 467 /* clear possible card detect interrupt */ 468 pcic_read(h, PCIC_CSC); 469 470 DPRINTF(("%s: attach finish vendor 0x%02x\n", h->ph_parent->dv_xname, 471 h->vendor)); 472 473 /* unsleep the cirrus controller */ 474 if (h->vendor == PCIC_VENDOR_CIRRUS_PD67XX) { 475 reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2); 476 if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) { 477 DPRINTF(("%s: socket %02x was suspended\n", 478 h->ph_parent->dv_xname, h->sock)); 479 reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND; 480 pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg); 481 } 482 } 483 484 /* if there's a card there, then attach it. */ 485 reg = pcic_read(h, PCIC_IF_STATUS); 486 if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) == 487 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 488 pcic_queue_event(h, PCIC_EVENT_INSERTION); 489 h->laststate = PCIC_LASTSTATE_PRESENT; 490 } else { 491 h->laststate = PCIC_LASTSTATE_EMPTY; 492 } 493 } 494 495 void 496 pcic_create_event_thread(arg) 497 void *arg; 498 { 499 struct pcic_handle *h = arg; 500 const char *cs; 501 502 switch (h->sock) { 503 case C0SA: 504 cs = "0,0"; 505 break; 506 case C0SB: 507 cs = "0,1"; 508 break; 509 case C1SA: 510 cs = "1,0"; 511 break; 512 case C1SB: 513 cs = "1,1"; 514 break; 515 default: 516 panic("pcic_create_event_thread: unknown pcic socket"); 517 } 518 519 if (kthread_create1(pcic_event_thread, h, &h->event_thread, 520 "%s,%s", h->ph_parent->dv_xname, cs)) { 521 printf("%s: unable to create event thread for sock 0x%02x\n", 522 h->ph_parent->dv_xname, h->sock); 523 panic("pcic_create_event_thread"); 524 } 525 } 526 527 void 528 pcic_event_thread(arg) 529 void *arg; 530 { 531 struct pcic_handle *h = arg; 532 struct pcic_event *pe; 533 int s, first = 1; 534 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 535 536 while (h->shutdown == 0) { 537 /* 538 * Serialize event processing on the PCIC. We may 539 * sleep while we hold this lock. 540 */ 541 (void) lockmgr(&sc->sc_pcic_lock, LK_EXCLUSIVE, NULL); 542 543 s = splhigh(); 544 if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) { 545 splx(s); 546 if (first) { 547 first = 0; 548 config_pending_decr(); 549 } 550 /* 551 * No events to process; release the PCIC lock. 552 */ 553 (void) lockmgr(&sc->sc_pcic_lock, LK_RELEASE, NULL); 554 (void) tsleep(&h->events, PWAIT, "pcicev", 0); 555 continue; 556 } else { 557 splx(s); 558 /* sleep .25s to be enqueued chatterling interrupts */ 559 (void) tsleep((caddr_t)pcic_event_thread, PWAIT, 560 "pcicss", hz/4); 561 } 562 s = splhigh(); 563 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 564 splx(s); 565 566 switch (pe->pe_type) { 567 case PCIC_EVENT_INSERTION: 568 s = splhigh(); 569 while (1) { 570 struct pcic_event *pe1, *pe2; 571 572 if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL) 573 break; 574 if (pe1->pe_type != PCIC_EVENT_REMOVAL) 575 break; 576 if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL) 577 break; 578 if (pe2->pe_type == PCIC_EVENT_INSERTION) { 579 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 580 free(pe1, M_TEMP); 581 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 582 free(pe2, M_TEMP); 583 } 584 } 585 splx(s); 586 587 DPRINTF(("%s: insertion event\n", 588 h->ph_parent->dv_xname)); 589 pcic_attach_card(h); 590 break; 591 592 case PCIC_EVENT_REMOVAL: 593 s = splhigh(); 594 while (1) { 595 struct pcic_event *pe1, *pe2; 596 597 if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL) 598 break; 599 if (pe1->pe_type != PCIC_EVENT_INSERTION) 600 break; 601 if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL) 602 break; 603 if (pe2->pe_type == PCIC_EVENT_REMOVAL) { 604 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 605 free(pe1, M_TEMP); 606 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 607 free(pe2, M_TEMP); 608 } 609 } 610 splx(s); 611 612 DPRINTF(("%s: removal event\n", 613 h->ph_parent->dv_xname)); 614 pcic_detach_card(h, DETACH_FORCE); 615 break; 616 617 default: 618 panic("pcic_event_thread: unknown event %d", 619 pe->pe_type); 620 } 621 free(pe, M_TEMP); 622 623 (void) lockmgr(&sc->sc_pcic_lock, LK_RELEASE, NULL); 624 } 625 626 h->event_thread = NULL; 627 628 /* In case parent is waiting for us to exit. */ 629 wakeup(sc); 630 631 kthread_exit(0); 632 } 633 634 int 635 pcic_submatch(parent, cf, aux) 636 struct device *parent; 637 struct cfdata *cf; 638 void *aux; 639 { 640 641 struct pcmciabus_attach_args *paa = aux; 642 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 643 644 switch (h->sock) { 645 case C0SA: 646 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 647 PCMCIABUSCF_CONTROLLER_DEFAULT && 648 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 649 return 0; 650 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 651 PCMCIABUSCF_SOCKET_DEFAULT && 652 cf->cf_loc[PCMCIABUSCF_SOCKET] != 0) 653 return 0; 654 655 break; 656 case C0SB: 657 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 658 PCMCIABUSCF_CONTROLLER_DEFAULT && 659 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 660 return 0; 661 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 662 PCMCIABUSCF_SOCKET_DEFAULT && 663 cf->cf_loc[PCMCIABUSCF_SOCKET] != 1) 664 return 0; 665 666 break; 667 case C1SA: 668 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 669 PCMCIABUSCF_CONTROLLER_DEFAULT && 670 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 671 return 0; 672 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 673 PCMCIABUSCF_SOCKET_DEFAULT && 674 cf->cf_loc[PCMCIABUSCF_SOCKET] != 0) 675 return 0; 676 677 break; 678 case C1SB: 679 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 680 PCMCIABUSCF_CONTROLLER_DEFAULT && 681 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 682 return 0; 683 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 684 PCMCIABUSCF_SOCKET_DEFAULT && 685 cf->cf_loc[PCMCIABUSCF_SOCKET] != 1) 686 return 0; 687 688 break; 689 default: 690 panic("unknown pcic socket"); 691 } 692 693 return (config_match(parent, cf, aux)); 694 } 695 696 int 697 pcic_print(arg, pnp) 698 void *arg; 699 const char *pnp; 700 { 701 struct pcmciabus_attach_args *paa = arg; 702 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 703 704 /* Only "pcmcia"s can attach to "pcic"s... easy. */ 705 if (pnp) 706 aprint_normal("pcmcia at %s", pnp); 707 708 switch (h->sock) { 709 case C0SA: 710 aprint_normal(" controller 0 socket 0"); 711 break; 712 case C0SB: 713 aprint_normal(" controller 0 socket 1"); 714 break; 715 case C1SA: 716 aprint_normal(" controller 1 socket 0"); 717 break; 718 case C1SB: 719 aprint_normal(" controller 1 socket 1"); 720 break; 721 default: 722 panic("unknown pcic socket"); 723 } 724 725 return (UNCONF); 726 } 727 728 void 729 pcic_poll_intr(arg) 730 void *arg; 731 { 732 struct pcic_softc *sc; 733 int i, s; 734 735 s = spltty(); 736 sc = arg; 737 for (i = 0; i < PCIC_NSLOTS; i++) 738 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 739 (void)pcic_intr_socket(&sc->handle[i]); 740 callout_reset(&sc->poll_ch, hz / 2, pcic_poll_intr, sc); 741 splx(s); 742 } 743 744 int 745 pcic_intr(arg) 746 void *arg; 747 { 748 struct pcic_softc *sc = arg; 749 int i, ret = 0; 750 751 DPRINTF(("%s: intr\n", sc->dev.dv_xname)); 752 753 for (i = 0; i < PCIC_NSLOTS; i++) 754 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 755 ret += pcic_intr_socket(&sc->handle[i]); 756 757 return (ret ? 1 : 0); 758 } 759 760 int 761 pcic_intr_socket(h) 762 struct pcic_handle *h; 763 { 764 int cscreg; 765 766 cscreg = pcic_read(h, PCIC_CSC); 767 768 cscreg &= (PCIC_CSC_GPI | 769 PCIC_CSC_CD | 770 PCIC_CSC_READY | 771 PCIC_CSC_BATTWARN | 772 PCIC_CSC_BATTDEAD); 773 774 if (cscreg & PCIC_CSC_GPI) { 775 DPRINTF(("%s: %02x GPI\n", h->ph_parent->dv_xname, h->sock)); 776 } 777 if (cscreg & PCIC_CSC_CD) { 778 int statreg; 779 780 statreg = pcic_read(h, PCIC_IF_STATUS); 781 782 DPRINTF(("%s: %02x CD %x\n", h->ph_parent->dv_xname, h->sock, 783 statreg)); 784 785 if ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 786 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 787 if (h->laststate != PCIC_LASTSTATE_PRESENT) { 788 DPRINTF(("%s: enqueing INSERTION event\n", 789 h->ph_parent->dv_xname)); 790 pcic_queue_event(h, PCIC_EVENT_INSERTION); 791 } 792 h->laststate = PCIC_LASTSTATE_PRESENT; 793 } else { 794 if (h->laststate == PCIC_LASTSTATE_PRESENT) { 795 /* Deactivate the card now. */ 796 DPRINTF(("%s: deactivating card\n", 797 h->ph_parent->dv_xname)); 798 pcic_deactivate_card(h); 799 800 DPRINTF(("%s: enqueing REMOVAL event\n", 801 h->ph_parent->dv_xname)); 802 pcic_queue_event(h, PCIC_EVENT_REMOVAL); 803 } 804 h->laststate = 805 ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 0) ? 806 PCIC_LASTSTATE_EMPTY : PCIC_LASTSTATE_HALF; 807 } 808 } 809 if (cscreg & PCIC_CSC_READY) { 810 DPRINTF(("%s: %02x READY\n", h->ph_parent->dv_xname, h->sock)); 811 /* shouldn't happen */ 812 } 813 if (cscreg & PCIC_CSC_BATTWARN) { 814 DPRINTF(("%s: %02x BATTWARN\n", h->ph_parent->dv_xname, 815 h->sock)); 816 } 817 if (cscreg & PCIC_CSC_BATTDEAD) { 818 DPRINTF(("%s: %02x BATTDEAD\n", h->ph_parent->dv_xname, 819 h->sock)); 820 } 821 return (cscreg ? 1 : 0); 822 } 823 824 void 825 pcic_queue_event(h, event) 826 struct pcic_handle *h; 827 int event; 828 { 829 struct pcic_event *pe; 830 int s; 831 832 pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT); 833 if (pe == NULL) 834 panic("pcic_queue_event: can't allocate event"); 835 836 pe->pe_type = event; 837 s = splhigh(); 838 SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q); 839 splx(s); 840 wakeup(&h->events); 841 } 842 843 void 844 pcic_attach_card(h) 845 struct pcic_handle *h; 846 { 847 848 if (!(h->flags & PCIC_FLAG_CARDP)) { 849 /* call the MI attach function */ 850 pcmcia_card_attach(h->pcmcia); 851 852 h->flags |= PCIC_FLAG_CARDP; 853 } else { 854 DPRINTF(("pcic_attach_card: already attached")); 855 } 856 } 857 858 void 859 pcic_detach_card(h, flags) 860 struct pcic_handle *h; 861 int flags; /* DETACH_* */ 862 { 863 864 if (h->flags & PCIC_FLAG_CARDP) { 865 h->flags &= ~PCIC_FLAG_CARDP; 866 867 /* call the MI detach function */ 868 pcmcia_card_detach(h->pcmcia, flags); 869 } else { 870 DPRINTF(("pcic_detach_card: already detached")); 871 } 872 } 873 874 void 875 pcic_deactivate_card(h) 876 struct pcic_handle *h; 877 { 878 int intr; 879 880 /* call the MI deactivate function */ 881 pcmcia_card_deactivate(h->pcmcia); 882 883 /* power down the socket */ 884 pcic_write(h, PCIC_PWRCTL, 0); 885 886 /* reset the socket */ 887 intr = pcic_read(h, PCIC_INTR); 888 intr &= PCIC_INTR_ENABLE; 889 pcic_write(h, PCIC_INTR, intr); 890 } 891 892 int 893 pcic_chip_mem_alloc(pch, size, pcmhp) 894 pcmcia_chipset_handle_t pch; 895 bus_size_t size; 896 struct pcmcia_mem_handle *pcmhp; 897 { 898 struct pcic_handle *h = (struct pcic_handle *) pch; 899 bus_space_handle_t memh; 900 bus_addr_t addr; 901 bus_size_t sizepg; 902 int i, mask, mhandle; 903 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 904 905 /* out of sc->memh, allocate as many pages as necessary */ 906 907 /* convert size to PCIC pages */ 908 sizepg = (size + (PCIC_MEM_ALIGN - 1)) / PCIC_MEM_ALIGN; 909 if (sizepg > PCIC_MAX_MEM_PAGES) 910 return (1); 911 912 mask = (1 << sizepg) - 1; 913 914 addr = 0; /* XXX gcc -Wuninitialized */ 915 mhandle = 0; /* XXX gcc -Wuninitialized */ 916 917 for (i = 0; i <= PCIC_MAX_MEM_PAGES - sizepg; i++) { 918 if ((sc->subregionmask & (mask << i)) == (mask << i)) { 919 if (bus_space_subregion(sc->memt, sc->memh, 920 i * PCIC_MEM_PAGESIZE, 921 sizepg * PCIC_MEM_PAGESIZE, &memh)) 922 return (1); 923 mhandle = mask << i; 924 addr = sc->membase + (i * PCIC_MEM_PAGESIZE); 925 sc->subregionmask &= ~(mhandle); 926 pcmhp->memt = sc->memt; 927 pcmhp->memh = memh; 928 pcmhp->addr = addr; 929 pcmhp->size = size; 930 pcmhp->mhandle = mhandle; 931 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 932 return (0); 933 } 934 } 935 936 return (1); 937 } 938 939 void 940 pcic_chip_mem_free(pch, pcmhp) 941 pcmcia_chipset_handle_t pch; 942 struct pcmcia_mem_handle *pcmhp; 943 { 944 struct pcic_handle *h = (struct pcic_handle *) pch; 945 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 946 947 sc->subregionmask |= pcmhp->mhandle; 948 } 949 950 static const struct mem_map_index_st { 951 int sysmem_start_lsb; 952 int sysmem_start_msb; 953 int sysmem_stop_lsb; 954 int sysmem_stop_msb; 955 int cardmem_lsb; 956 int cardmem_msb; 957 int memenable; 958 } mem_map_index[] = { 959 { 960 PCIC_SYSMEM_ADDR0_START_LSB, 961 PCIC_SYSMEM_ADDR0_START_MSB, 962 PCIC_SYSMEM_ADDR0_STOP_LSB, 963 PCIC_SYSMEM_ADDR0_STOP_MSB, 964 PCIC_CARDMEM_ADDR0_LSB, 965 PCIC_CARDMEM_ADDR0_MSB, 966 PCIC_ADDRWIN_ENABLE_MEM0, 967 }, 968 { 969 PCIC_SYSMEM_ADDR1_START_LSB, 970 PCIC_SYSMEM_ADDR1_START_MSB, 971 PCIC_SYSMEM_ADDR1_STOP_LSB, 972 PCIC_SYSMEM_ADDR1_STOP_MSB, 973 PCIC_CARDMEM_ADDR1_LSB, 974 PCIC_CARDMEM_ADDR1_MSB, 975 PCIC_ADDRWIN_ENABLE_MEM1, 976 }, 977 { 978 PCIC_SYSMEM_ADDR2_START_LSB, 979 PCIC_SYSMEM_ADDR2_START_MSB, 980 PCIC_SYSMEM_ADDR2_STOP_LSB, 981 PCIC_SYSMEM_ADDR2_STOP_MSB, 982 PCIC_CARDMEM_ADDR2_LSB, 983 PCIC_CARDMEM_ADDR2_MSB, 984 PCIC_ADDRWIN_ENABLE_MEM2, 985 }, 986 { 987 PCIC_SYSMEM_ADDR3_START_LSB, 988 PCIC_SYSMEM_ADDR3_START_MSB, 989 PCIC_SYSMEM_ADDR3_STOP_LSB, 990 PCIC_SYSMEM_ADDR3_STOP_MSB, 991 PCIC_CARDMEM_ADDR3_LSB, 992 PCIC_CARDMEM_ADDR3_MSB, 993 PCIC_ADDRWIN_ENABLE_MEM3, 994 }, 995 { 996 PCIC_SYSMEM_ADDR4_START_LSB, 997 PCIC_SYSMEM_ADDR4_START_MSB, 998 PCIC_SYSMEM_ADDR4_STOP_LSB, 999 PCIC_SYSMEM_ADDR4_STOP_MSB, 1000 PCIC_CARDMEM_ADDR4_LSB, 1001 PCIC_CARDMEM_ADDR4_MSB, 1002 PCIC_ADDRWIN_ENABLE_MEM4, 1003 }, 1004 }; 1005 1006 void 1007 pcic_chip_do_mem_map(h, win) 1008 struct pcic_handle *h; 1009 int win; 1010 { 1011 int reg; 1012 int kind = h->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 1013 int mem8 = 1014 (h->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 1015 || (kind == PCMCIA_MEM_ATTR); 1016 1017 DPRINTF(("mem8 %d\n", mem8)); 1018 /* mem8 = 1; */ 1019 1020 pcic_write(h, mem_map_index[win].sysmem_start_lsb, 1021 (h->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 1022 pcic_write(h, mem_map_index[win].sysmem_start_msb, 1023 ((h->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 1024 PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK) | 1025 (mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT)); 1026 1027 pcic_write(h, mem_map_index[win].sysmem_stop_lsb, 1028 ((h->mem[win].addr + h->mem[win].size) >> 1029 PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 1030 pcic_write(h, mem_map_index[win].sysmem_stop_msb, 1031 (((h->mem[win].addr + h->mem[win].size) >> 1032 (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 1033 PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) | 1034 PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2); 1035 1036 pcic_write(h, mem_map_index[win].cardmem_lsb, 1037 (h->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff); 1038 pcic_write(h, mem_map_index[win].cardmem_msb, 1039 ((h->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) & 1040 PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) | 1041 ((kind == PCMCIA_MEM_ATTR) ? 1042 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0)); 1043 1044 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1045 reg |= (mem_map_index[win].memenable | PCIC_ADDRWIN_ENABLE_MEMCS16); 1046 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1047 1048 delay(100); 1049 1050 #ifdef PCICDEBUG 1051 { 1052 int r1, r2, r3, r4, r5, r6; 1053 1054 r1 = pcic_read(h, mem_map_index[win].sysmem_start_msb); 1055 r2 = pcic_read(h, mem_map_index[win].sysmem_start_lsb); 1056 r3 = pcic_read(h, mem_map_index[win].sysmem_stop_msb); 1057 r4 = pcic_read(h, mem_map_index[win].sysmem_stop_lsb); 1058 r5 = pcic_read(h, mem_map_index[win].cardmem_msb); 1059 r6 = pcic_read(h, mem_map_index[win].cardmem_lsb); 1060 1061 DPRINTF(("pcic_chip_do_mem_map window %d: %02x%02x %02x%02x " 1062 "%02x%02x\n", win, r1, r2, r3, r4, r5, r6)); 1063 } 1064 #endif 1065 } 1066 1067 int 1068 pcic_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 1069 pcmcia_chipset_handle_t pch; 1070 int kind; 1071 bus_addr_t card_addr; 1072 bus_size_t size; 1073 struct pcmcia_mem_handle *pcmhp; 1074 bus_size_t *offsetp; 1075 int *windowp; 1076 { 1077 struct pcic_handle *h = (struct pcic_handle *) pch; 1078 bus_addr_t busaddr; 1079 long card_offset; 1080 int i, win; 1081 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 1082 1083 win = -1; 1084 for (i = 0; i < (sizeof(mem_map_index) / sizeof(mem_map_index[0])); 1085 i++) { 1086 if ((h->memalloc & (1 << i)) == 0) { 1087 win = i; 1088 h->memalloc |= (1 << i); 1089 break; 1090 } 1091 } 1092 1093 if (win == -1) 1094 return (1); 1095 1096 *windowp = win; 1097 1098 /* XXX this is pretty gross */ 1099 1100 if (sc->memt != pcmhp->memt) 1101 panic("pcic_chip_mem_map memt is bogus"); 1102 1103 busaddr = pcmhp->addr; 1104 1105 /* 1106 * compute the address offset to the pcmcia address space for the 1107 * pcic. this is intentionally signed. The masks and shifts below 1108 * will cause TRT to happen in the pcic registers. Deal with making 1109 * sure the address is aligned, and return the alignment offset. 1110 */ 1111 1112 *offsetp = card_addr % PCIC_MEM_ALIGN; 1113 card_addr -= *offsetp; 1114 1115 DPRINTF(("pcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 1116 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 1117 (u_long) card_addr)); 1118 1119 /* 1120 * include the offset in the size, and decrement size by one, since 1121 * the hw wants start/stop 1122 */ 1123 size += *offsetp - 1; 1124 1125 card_offset = (((long) card_addr) - ((long) busaddr)); 1126 1127 h->mem[win].addr = busaddr; 1128 h->mem[win].size = size; 1129 h->mem[win].offset = card_offset; 1130 h->mem[win].kind = kind; 1131 1132 pcic_chip_do_mem_map(h, win); 1133 1134 return (0); 1135 } 1136 1137 void 1138 pcic_chip_mem_unmap(pch, window) 1139 pcmcia_chipset_handle_t pch; 1140 int window; 1141 { 1142 struct pcic_handle *h = (struct pcic_handle *) pch; 1143 int reg; 1144 1145 if (window >= (sizeof(mem_map_index) / sizeof(mem_map_index[0]))) 1146 panic("pcic_chip_mem_unmap: window out of range"); 1147 1148 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1149 reg &= ~mem_map_index[window].memenable; 1150 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1151 1152 h->memalloc &= ~(1 << window); 1153 } 1154 1155 int 1156 pcic_chip_io_alloc(pch, start, size, align, pcihp) 1157 pcmcia_chipset_handle_t pch; 1158 bus_addr_t start; 1159 bus_size_t size; 1160 bus_size_t align; 1161 struct pcmcia_io_handle *pcihp; 1162 { 1163 struct pcic_handle *h = (struct pcic_handle *) pch; 1164 bus_space_tag_t iot; 1165 bus_space_handle_t ioh; 1166 bus_addr_t ioaddr; 1167 int flags = 0; 1168 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 1169 1170 /* 1171 * Allocate some arbitrary I/O space. 1172 */ 1173 1174 iot = sc->iot; 1175 1176 if (start) { 1177 ioaddr = start; 1178 if (bus_space_map(iot, start, size, 0, &ioh)) 1179 return (1); 1180 DPRINTF(("pcic_chip_io_alloc map port %lx+%lx\n", 1181 (u_long) ioaddr, (u_long) size)); 1182 } else { 1183 flags |= PCMCIA_IO_ALLOCATED; 1184 if (bus_space_alloc(iot, sc->iobase, 1185 sc->iobase + sc->iosize, size, align, 0, 0, 1186 &ioaddr, &ioh)) 1187 return (1); 1188 DPRINTF(("pcic_chip_io_alloc alloc port %lx+%lx\n", 1189 (u_long) ioaddr, (u_long) size)); 1190 } 1191 1192 pcihp->iot = iot; 1193 pcihp->ioh = ioh; 1194 pcihp->addr = ioaddr; 1195 pcihp->size = size; 1196 pcihp->flags = flags; 1197 1198 return (0); 1199 } 1200 1201 void 1202 pcic_chip_io_free(pch, pcihp) 1203 pcmcia_chipset_handle_t pch; 1204 struct pcmcia_io_handle *pcihp; 1205 { 1206 bus_space_tag_t iot = pcihp->iot; 1207 bus_space_handle_t ioh = pcihp->ioh; 1208 bus_size_t size = pcihp->size; 1209 1210 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1211 bus_space_free(iot, ioh, size); 1212 else 1213 bus_space_unmap(iot, ioh, size); 1214 } 1215 1216 1217 static const struct io_map_index_st { 1218 int start_lsb; 1219 int start_msb; 1220 int stop_lsb; 1221 int stop_msb; 1222 int ioenable; 1223 int ioctlmask; 1224 int ioctlbits[3]; /* indexed by PCMCIA_WIDTH_* */ 1225 } io_map_index[] = { 1226 { 1227 PCIC_IOADDR0_START_LSB, 1228 PCIC_IOADDR0_START_MSB, 1229 PCIC_IOADDR0_STOP_LSB, 1230 PCIC_IOADDR0_STOP_MSB, 1231 PCIC_ADDRWIN_ENABLE_IO0, 1232 PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1233 PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK, 1234 { 1235 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1236 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1237 PCIC_IOCTL_IO0_DATASIZE_8BIT, 1238 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1239 PCIC_IOCTL_IO0_DATASIZE_16BIT, 1240 }, 1241 }, 1242 { 1243 PCIC_IOADDR1_START_LSB, 1244 PCIC_IOADDR1_START_MSB, 1245 PCIC_IOADDR1_STOP_LSB, 1246 PCIC_IOADDR1_STOP_MSB, 1247 PCIC_ADDRWIN_ENABLE_IO1, 1248 PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1249 PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK, 1250 { 1251 PCIC_IOCTL_IO1_IOCS16SRC_CARD, 1252 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1253 PCIC_IOCTL_IO1_DATASIZE_8BIT, 1254 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1255 PCIC_IOCTL_IO1_DATASIZE_16BIT, 1256 }, 1257 }, 1258 }; 1259 1260 void 1261 pcic_chip_do_io_map(h, win) 1262 struct pcic_handle *h; 1263 int win; 1264 { 1265 int reg; 1266 1267 DPRINTF(("pcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 1268 win, (long) h->io[win].addr, (long) h->io[win].size, 1269 h->io[win].width * 8)); 1270 1271 pcic_write(h, io_map_index[win].start_lsb, h->io[win].addr & 0xff); 1272 pcic_write(h, io_map_index[win].start_msb, 1273 (h->io[win].addr >> 8) & 0xff); 1274 1275 pcic_write(h, io_map_index[win].stop_lsb, 1276 (h->io[win].addr + h->io[win].size - 1) & 0xff); 1277 pcic_write(h, io_map_index[win].stop_msb, 1278 ((h->io[win].addr + h->io[win].size - 1) >> 8) & 0xff); 1279 1280 reg = pcic_read(h, PCIC_IOCTL); 1281 reg &= ~io_map_index[win].ioctlmask; 1282 reg |= io_map_index[win].ioctlbits[h->io[win].width]; 1283 pcic_write(h, PCIC_IOCTL, reg); 1284 1285 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1286 reg |= io_map_index[win].ioenable; 1287 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1288 } 1289 1290 int 1291 pcic_chip_io_map(pch, width, offset, size, pcihp, windowp) 1292 pcmcia_chipset_handle_t pch; 1293 int width; 1294 bus_addr_t offset; 1295 bus_size_t size; 1296 struct pcmcia_io_handle *pcihp; 1297 int *windowp; 1298 { 1299 struct pcic_handle *h = (struct pcic_handle *) pch; 1300 bus_addr_t ioaddr = pcihp->addr + offset; 1301 int i, win; 1302 #ifdef PCICDEBUG 1303 static char *width_names[] = { "auto", "io8", "io16" }; 1304 #endif 1305 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 1306 1307 /* XXX Sanity check offset/size. */ 1308 1309 win = -1; 1310 for (i = 0; i < (sizeof(io_map_index) / sizeof(io_map_index[0])); i++) { 1311 if ((h->ioalloc & (1 << i)) == 0) { 1312 win = i; 1313 h->ioalloc |= (1 << i); 1314 break; 1315 } 1316 } 1317 1318 if (win == -1) 1319 return (1); 1320 1321 *windowp = win; 1322 1323 /* XXX this is pretty gross */ 1324 1325 if (sc->iot != pcihp->iot) 1326 panic("pcic_chip_io_map iot is bogus"); 1327 1328 DPRINTF(("pcic_chip_io_map window %d %s port %lx+%lx\n", 1329 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1330 1331 /* XXX wtf is this doing here? */ 1332 1333 printf("%s: port 0x%lx", sc->dev.dv_xname, (u_long) ioaddr); 1334 if (size > 1) 1335 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1336 printf("\n"); 1337 1338 h->io[win].addr = ioaddr; 1339 h->io[win].size = size; 1340 h->io[win].width = width; 1341 1342 pcic_chip_do_io_map(h, win); 1343 1344 return (0); 1345 } 1346 1347 void 1348 pcic_chip_io_unmap(pch, window) 1349 pcmcia_chipset_handle_t pch; 1350 int window; 1351 { 1352 struct pcic_handle *h = (struct pcic_handle *) pch; 1353 int reg; 1354 1355 if (window >= (sizeof(io_map_index) / sizeof(io_map_index[0]))) 1356 panic("pcic_chip_io_unmap: window out of range"); 1357 1358 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1359 reg &= ~io_map_index[window].ioenable; 1360 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1361 1362 h->ioalloc &= ~(1 << window); 1363 } 1364 1365 static void 1366 pcic_wait_ready(h) 1367 struct pcic_handle *h; 1368 { 1369 int i; 1370 1371 /* wait an initial 10ms for quick cards */ 1372 if (pcic_read(h, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) 1373 return; 1374 pcic_delay(h, 10, "pccwr0"); 1375 for (i = 0; i < 50; i++) { 1376 if (pcic_read(h, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) 1377 return; 1378 /* wait .1s (100ms) each iteration now */ 1379 pcic_delay(h, 100, "pccwr1"); 1380 #ifdef PCICDEBUG 1381 if (pcic_debug) { 1382 if ((i > 20) && (i % 100 == 99)) 1383 printf("."); 1384 } 1385 #endif 1386 } 1387 1388 #ifdef DIAGNOSTIC 1389 printf("pcic_wait_ready: ready never happened, status = %02x\n", 1390 pcic_read(h, PCIC_IF_STATUS)); 1391 #endif 1392 } 1393 1394 /* 1395 * Perform long (msec order) delay. 1396 */ 1397 static void 1398 pcic_delay(h, timo, wmesg) 1399 struct pcic_handle *h; 1400 int timo; /* in ms. must not be zero */ 1401 const char *wmesg; 1402 { 1403 1404 #ifdef DIAGNOSTIC 1405 if (timo <= 0) { 1406 printf("called with timeout %d\n", timo); 1407 panic("pcic_delay"); 1408 } 1409 if (curlwp == NULL) { 1410 printf("called in interrupt context\n"); 1411 panic("pcic_delay"); 1412 } 1413 if (h->event_thread == NULL) { 1414 printf("no event thread\n"); 1415 panic("pcic_delay"); 1416 } 1417 #endif 1418 DPRINTF(("pcic_delay: \"%s\" %p, sleep %d ms\n", 1419 wmesg, h->event_thread, timo)); 1420 tsleep(pcic_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 1421 } 1422 1423 void 1424 pcic_chip_socket_enable(pch) 1425 pcmcia_chipset_handle_t pch; 1426 { 1427 struct pcic_handle *h = (struct pcic_handle *) pch; 1428 int cardtype, win, intr, pwr; 1429 #if defined(DIAGNOSTIC) || defined(PCICDEBUG) 1430 int reg; 1431 #endif 1432 1433 #ifdef DIAGNOSTIC 1434 if (h->flags & PCIC_FLAG_ENABLED) 1435 printf("pcic_chip_socket_enable: enabling twice\n"); 1436 #endif 1437 1438 /* disable interrupts */ 1439 intr = pcic_read(h, PCIC_INTR); 1440 intr &= ~PCIC_INTR_IRQ_MASK; 1441 pcic_write(h, PCIC_INTR, intr); 1442 1443 /* power down the socket to reset it, clear the card reset pin */ 1444 pwr = 0; 1445 pcic_write(h, PCIC_PWRCTL, pwr); 1446 1447 /* 1448 * wait 300ms until power fails (Tpf). Then, wait 100ms since 1449 * we are changing Vcc (Toff). 1450 */ 1451 pcic_delay(h, 300 + 100, "pccen0"); 1452 1453 /* 1454 * power hack for RICOH RF5C[23]96 1455 */ 1456 switch( h->vendor ) { 1457 case PCIC_VENDOR_RICOH_5C296: 1458 case PCIC_VENDOR_RICOH_5C396: 1459 { 1460 int regtmp; 1461 regtmp = pcic_read(h, PCIC_RICOH_REG_MCR2); 1462 #ifdef RICOH_POWER_HACK 1463 regtmp |= PCIC_RICOH_MCR2_VCC_DIRECT; 1464 #else 1465 regtmp &= ~(PCIC_RICOH_MCR2_VCC_DIRECT|PCIC_RICOH_MCR2_VCC_SEL_3V); 1466 #endif 1467 pcic_write(h, PCIC_RICOH_REG_MCR2, regtmp); 1468 } 1469 break; 1470 default: 1471 break; 1472 } 1473 1474 #ifdef VADEM_POWER_HACK 1475 bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x0e); 1476 bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x37); 1477 printf("prcr = %02x\n", pcic_read(h, 0x02)); 1478 printf("cvsr = %02x\n", pcic_read(h, 0x2f)); 1479 printf("DANGER WILL ROBINSON! Changing voltage select!\n"); 1480 pcic_write(h, 0x2f, pcic_read(h, 0x2f) & ~0x03); 1481 printf("cvsr = %02x\n", pcic_read(h, 0x2f)); 1482 #endif 1483 /* power up the socket */ 1484 pwr |= PCIC_PWRCTL_DISABLE_RESETDRV | PCIC_PWRCTL_PWR_ENABLE | PCIC_PWRCTL_VPP1_VCC; 1485 pcic_write(h, PCIC_PWRCTL, pwr); 1486 1487 /* 1488 * wait 100ms until power raise (Tpr) and 20ms to become 1489 * stable (Tsu(Vcc)). 1490 * 1491 * some machines require some more time to be settled 1492 * (300ms is added here). 1493 */ 1494 pcic_delay(h, 100 + 20 + 300, "pccen1"); 1495 pwr |= PCIC_PWRCTL_OE; 1496 pcic_write(h, PCIC_PWRCTL, pwr); 1497 1498 /* now make sure we have reset# active */ 1499 intr &= ~PCIC_INTR_RESET; 1500 pcic_write(h, PCIC_INTR, intr); 1501 1502 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV | 1503 PCIC_PWRCTL_OE | PCIC_PWRCTL_PWR_ENABLE | PCIC_PWRCTL_VPP1_VCC); 1504 /* 1505 * hold RESET at least 10us, this is a min allow for slop in 1506 * delay routine. 1507 */ 1508 delay(20); 1509 1510 /* clear the reset flag */ 1511 intr |= PCIC_INTR_RESET; 1512 pcic_write(h, PCIC_INTR, intr); 1513 1514 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1515 pcic_delay(h, 20, "pccen2"); 1516 1517 #if defined(DIAGNOSTIC) || defined(PCICDEBUG) 1518 reg = pcic_read(h, PCIC_IF_STATUS); 1519 #endif 1520 #ifdef DIAGNOSTIC 1521 if (!(reg & PCIC_IF_STATUS_POWERACTIVE)) { 1522 printf("pcic_chip_socket_enable: status %x\n", reg); 1523 } 1524 #endif 1525 /* wait for the chip to finish initializing */ 1526 pcic_wait_ready(h); 1527 1528 /* zero out the address windows */ 1529 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1530 1531 /* set the card type and enable the interrupt */ 1532 cardtype = pcmcia_card_gettype(h->pcmcia); 1533 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 1534 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 1535 pcic_write(h, PCIC_INTR, intr); 1536 1537 DPRINTF(("%s: pcic_chip_socket_enable %02x cardtype %s %02x\n", 1538 h->ph_parent->dv_xname, h->sock, 1539 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg)); 1540 1541 /* reinstall all the memory and io mappings */ 1542 for (win = 0; win < PCIC_MEM_WINS; win++) 1543 if (h->memalloc & (1 << win)) 1544 pcic_chip_do_mem_map(h, win); 1545 for (win = 0; win < PCIC_IO_WINS; win++) 1546 if (h->ioalloc & (1 << win)) 1547 pcic_chip_do_io_map(h, win); 1548 1549 h->flags |= PCIC_FLAG_ENABLED; 1550 1551 /* finally enable the interrupt */ 1552 intr |= h->ih_irq; 1553 pcic_write(h, PCIC_INTR, intr); 1554 } 1555 1556 void 1557 pcic_chip_socket_disable(pch) 1558 pcmcia_chipset_handle_t pch; 1559 { 1560 struct pcic_handle *h = (struct pcic_handle *) pch; 1561 int intr; 1562 1563 DPRINTF(("pcic_chip_socket_disable\n")); 1564 1565 /* disable interrupts */ 1566 intr = pcic_read(h, PCIC_INTR); 1567 intr &= ~PCIC_INTR_IRQ_MASK; 1568 pcic_write(h, PCIC_INTR, intr); 1569 1570 /* power down the socket */ 1571 pcic_write(h, PCIC_PWRCTL, 0); 1572 1573 /* zero out the address windows */ 1574 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1575 1576 h->flags &= ~PCIC_FLAG_ENABLED; 1577 } 1578 1579 static u_int8_t 1580 st_pcic_read(h, idx) 1581 struct pcic_handle *h; 1582 int idx; 1583 { 1584 1585 if (idx != -1) 1586 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX, 1587 h->sock + idx); 1588 return (bus_space_read_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA)); 1589 } 1590 1591 static void 1592 st_pcic_write(h, idx, data) 1593 struct pcic_handle *h; 1594 int idx; 1595 u_int8_t data; 1596 { 1597 1598 if (idx != -1) 1599 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX, 1600 h->sock + idx); 1601 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA, data); 1602 }
Cache object: 0d399766f2f609c9bcc28e83f2738074
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