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sys/dev/ic/i82365.c
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1 /* $NetBSD: i82365.c,v 1.97 2006/11/16 01:32:51 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Charles M. Hannum. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 */ 20 21 /* 22 * Copyright (c) 2000 Christian E. Hopps. All rights reserved. 23 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 24 * 25 * Redistribution and use in source and binary forms, with or without 26 * modification, are permitted provided that the following conditions 27 * are met: 28 * 1. Redistributions of source code must retain the above copyright 29 * notice, this list of conditions and the following disclaimer. 30 * 2. Redistributions in binary form must reproduce the above copyright 31 * notice, this list of conditions and the following disclaimer in the 32 * documentation and/or other materials provided with the distribution. 33 * 3. All advertising materials mentioning features or use of this software 34 * must display the following acknowledgement: 35 * This product includes software developed by Marc Horowitz. 36 * 4. The name of the author may not be used to endorse or promote products 37 * derived from this software without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 40 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 41 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 42 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 43 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 44 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 45 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 46 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 47 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 48 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: i82365.c,v 1.97 2006/11/16 01:32:51 christos Exp $"); 53 54 #define PCICDEBUG 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/device.h> 59 #include <sys/extent.h> 60 #include <sys/kernel.h> 61 #include <sys/malloc.h> 62 #include <sys/kthread.h> 63 64 #include <machine/bus.h> 65 #include <machine/intr.h> 66 67 #include <dev/pcmcia/pcmciareg.h> 68 #include <dev/pcmcia/pcmciavar.h> 69 70 #include <dev/ic/i82365reg.h> 71 #include <dev/ic/i82365var.h> 72 73 #include "locators.h" 74 75 #ifdef PCICDEBUG 76 int pcic_debug = 0; 77 #define DPRINTF(arg) if (pcic_debug) printf arg; 78 #else 79 #define DPRINTF(arg) 80 #endif 81 82 /* 83 * Individual drivers will allocate their own memory and io regions. Memory 84 * regions must be a multiple of 4k, aligned on a 4k boundary. 85 */ 86 87 #define PCIC_MEM_ALIGN PCIC_MEM_PAGESIZE 88 89 void pcic_attach_socket(struct pcic_handle *); 90 void pcic_attach_socket_finish(struct pcic_handle *); 91 92 int pcic_print (void *arg, const char *pnp); 93 int pcic_intr_socket(struct pcic_handle *); 94 void pcic_poll_intr(void *); 95 96 void pcic_attach_card(struct pcic_handle *); 97 void pcic_detach_card(struct pcic_handle *, int); 98 void pcic_deactivate_card(struct pcic_handle *); 99 100 void pcic_chip_do_mem_map(struct pcic_handle *, int); 101 void pcic_chip_do_io_map(struct pcic_handle *, int); 102 103 void pcic_create_event_thread(void *); 104 void pcic_event_thread(void *); 105 106 void pcic_queue_event(struct pcic_handle *, int); 107 void pcic_power(int, void *); 108 109 static int pcic_wait_ready(struct pcic_handle *); 110 static void pcic_delay(struct pcic_handle *, int, const char *); 111 112 static u_int8_t st_pcic_read(struct pcic_handle *, int); 113 static void st_pcic_write(struct pcic_handle *, int, u_int8_t); 114 115 int 116 pcic_ident_ok(ident) 117 int ident; 118 { 119 /* this is very empirical and heuristic */ 120 121 if ((ident == 0) || (ident == 0xff) || (ident & PCIC_IDENT_ZERO)) 122 return (0); 123 124 if ((ident & PCIC_IDENT_REV_MASK) == 0) 125 return (0); 126 127 if ((ident & PCIC_IDENT_IFTYPE_MASK) != PCIC_IDENT_IFTYPE_MEM_AND_IO) { 128 #ifdef DIAGNOSTIC 129 printf("pcic: does not support memory and I/O cards, " 130 "ignored (ident=%0x)\n", ident); 131 #endif 132 return (0); 133 } 134 135 return (1); 136 } 137 138 int 139 pcic_vendor(h) 140 struct pcic_handle *h; 141 { 142 int reg; 143 int vendor; 144 145 reg = pcic_read(h, PCIC_IDENT); 146 147 if ((reg & PCIC_IDENT_REV_MASK) == 0) 148 return (PCIC_VENDOR_NONE); 149 150 switch (reg) { 151 case 0x00: 152 case 0xff: 153 return (PCIC_VENDOR_NONE); 154 case PCIC_IDENT_ID_INTEL0: 155 vendor = PCIC_VENDOR_I82365SLR0; 156 break; 157 case PCIC_IDENT_ID_INTEL1: 158 vendor = PCIC_VENDOR_I82365SLR1; 159 break; 160 case PCIC_IDENT_ID_INTEL2: 161 vendor = PCIC_VENDOR_I82365SL_DF; 162 break; 163 case PCIC_IDENT_ID_IBM1: 164 case PCIC_IDENT_ID_IBM2: 165 vendor = PCIC_VENDOR_IBM; 166 break; 167 case PCIC_IDENT_ID_IBM3: 168 vendor = PCIC_VENDOR_IBM_KING; 169 break; 170 default: 171 vendor = PCIC_VENDOR_UNKNOWN; 172 break; 173 } 174 175 if (vendor == PCIC_VENDOR_I82365SLR0 || 176 vendor == PCIC_VENDOR_I82365SLR1) { 177 /* 178 * Check for Cirrus PD67xx. 179 * the chip_id of the cirrus toggles between 11 and 00 after a 180 * write. weird. 181 */ 182 pcic_write(h, PCIC_CIRRUS_CHIP_INFO, 0); 183 reg = pcic_read(h, -1); 184 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 185 PCIC_CIRRUS_CHIP_INFO_CHIP_ID) { 186 reg = pcic_read(h, -1); 187 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0) 188 return (PCIC_VENDOR_CIRRUS_PD67XX); 189 } 190 191 /* 192 * check for Ricoh RF5C[23]96 193 */ 194 reg = pcic_read(h, PCIC_RICOH_REG_CHIP_ID); 195 switch (reg) { 196 case PCIC_RICOH_CHIP_ID_5C296: 197 return (PCIC_VENDOR_RICOH_5C296); 198 case PCIC_RICOH_CHIP_ID_5C396: 199 return (PCIC_VENDOR_RICOH_5C396); 200 } 201 } 202 203 return (vendor); 204 } 205 206 const char * 207 pcic_vendor_to_string(vendor) 208 int vendor; 209 { 210 switch (vendor) { 211 case PCIC_VENDOR_I82365SLR0: 212 return ("Intel 82365SL Revision 0"); 213 case PCIC_VENDOR_I82365SLR1: 214 return ("Intel 82365SL Revision 1"); 215 case PCIC_VENDOR_CIRRUS_PD67XX: 216 return ("Cirrus PD6710/2X"); 217 case PCIC_VENDOR_I82365SL_DF: 218 return ("Intel 82365SL-DF"); 219 case PCIC_VENDOR_RICOH_5C296: 220 return ("Ricoh RF5C296"); 221 case PCIC_VENDOR_RICOH_5C396: 222 return ("Ricoh RF5C396"); 223 case PCIC_VENDOR_IBM: 224 return ("IBM PCIC"); 225 case PCIC_VENDOR_IBM_KING: 226 return ("IBM KING"); 227 } 228 229 return ("Unknown controller"); 230 } 231 232 void 233 pcic_attach(sc) 234 struct pcic_softc *sc; 235 { 236 int i, reg, chip, socket; 237 struct pcic_handle *h; 238 239 DPRINTF(("pcic ident regs:")); 240 241 lockinit(&sc->sc_pcic_lock, PWAIT, "pciclk", 0, 0); 242 243 /* find and configure for the available sockets */ 244 for (i = 0; i < __arraycount(sc->handle); i++) { 245 h = &sc->handle[i]; 246 chip = i / 2; 247 socket = i % 2; 248 249 h->ph_parent = (struct device *)sc; 250 h->chip = chip; 251 h->socket = socket; 252 h->sock = chip * PCIC_CHIP_OFFSET + socket * PCIC_SOCKET_OFFSET; 253 h->laststate = PCIC_LASTSTATE_EMPTY; 254 /* initialize pcic_read and pcic_write functions */ 255 h->ph_read = st_pcic_read; 256 h->ph_write = st_pcic_write; 257 h->ph_bus_t = sc->iot; 258 h->ph_bus_h = sc->ioh; 259 h->flags = 0; 260 261 /* need to read vendor -- for cirrus to report no xtra chip */ 262 if (socket == 0) { 263 h->vendor = pcic_vendor(h); 264 if (i < __arraycount(sc->handle) - 1) 265 (h+1)->vendor = h->vendor; 266 } 267 268 switch (h->vendor) { 269 case PCIC_VENDOR_NONE: 270 /* no chip */ 271 continue; 272 case PCIC_VENDOR_CIRRUS_PD67XX: 273 reg = pcic_read(h, PCIC_CIRRUS_CHIP_INFO); 274 if (socket == 0 || 275 (reg & PCIC_CIRRUS_CHIP_INFO_SLOTS)) 276 h->flags = PCIC_FLAG_SOCKETP; 277 break; 278 default: 279 /* 280 * During the socket probe, read the ident register 281 * twice. I don't understand why, but sometimes the 282 * clone chips in hpcmips boxes read all-0s the first 283 * time. -- mycroft 284 */ 285 reg = pcic_read(h, PCIC_IDENT); 286 DPRINTF(("socket %d ident reg 0x%02x\n", i, reg)); 287 reg = pcic_read(h, PCIC_IDENT); 288 DPRINTF(("socket %d ident reg 0x%02x\n", i, reg)); 289 if (pcic_ident_ok(reg)) 290 h->flags = PCIC_FLAG_SOCKETP; 291 break; 292 } 293 } 294 295 for (i = 0; i < __arraycount(sc->handle); i++) { 296 h = &sc->handle[i]; 297 298 if (h->flags & PCIC_FLAG_SOCKETP) { 299 SIMPLEQ_INIT(&h->events); 300 301 /* disable interrupts and leave socket in reset */ 302 pcic_write(h, PCIC_INTR, 0); 303 304 /* zero out the address windows */ 305 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 306 307 /* power down the socket */ 308 pcic_write(h, PCIC_PWRCTL, 0); 309 310 pcic_write(h, PCIC_CSC_INTR, 0); 311 (void) pcic_read(h, PCIC_CSC); 312 } 313 } 314 315 /* print detected info */ 316 for (i = 0; i < __arraycount(sc->handle) - 1; i += 2) { 317 h = &sc->handle[i]; 318 chip = i / 2; 319 320 if (h->vendor == PCIC_VENDOR_NONE) 321 continue; 322 323 aprint_normal("%s: controller %d (%s) has ", sc->dev.dv_xname, 324 chip, pcic_vendor_to_string(sc->handle[i].vendor)); 325 326 if ((h->flags & PCIC_FLAG_SOCKETP) && 327 ((h+1)->flags & PCIC_FLAG_SOCKETP)) 328 aprint_normal("sockets A and B\n"); 329 else if (h->flags & PCIC_FLAG_SOCKETP) 330 aprint_normal("socket A only\n"); 331 else if ((h+1)->flags & PCIC_FLAG_SOCKETP) 332 aprint_normal("socket B only\n"); 333 else 334 aprint_normal("no sockets\n"); 335 } 336 } 337 338 /* 339 * attach the sockets before we know what interrupts we have 340 */ 341 void 342 pcic_attach_sockets(sc) 343 struct pcic_softc *sc; 344 { 345 int i; 346 347 for (i = 0; i < __arraycount(sc->handle); i++) 348 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 349 pcic_attach_socket(&sc->handle[i]); 350 } 351 352 void 353 pcic_power(why, arg) 354 int why; 355 void *arg; 356 { 357 struct pcic_handle *h = (struct pcic_handle *)arg; 358 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 359 int reg; 360 361 DPRINTF(("%s: power: why %d\n", h->ph_parent->dv_xname, why)); 362 363 if (h->flags & PCIC_FLAG_SOCKETP) { 364 if ((why == PWR_RESUME) && 365 (pcic_read(h, PCIC_CSC_INTR) == 0)) { 366 #ifdef PCICDEBUG 367 char bitbuf[64]; 368 #endif 369 reg = PCIC_CSC_INTR_CD_ENABLE; 370 if (sc->irq != -1) 371 reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT; 372 pcic_write(h, PCIC_CSC_INTR, reg); 373 DPRINTF(("%s: CSC_INTR was zero; reset to %s\n", 374 sc->dev.dv_xname, 375 bitmask_snprintf(pcic_read(h, PCIC_CSC_INTR), 376 PCIC_CSC_INTR_FORMAT, 377 bitbuf, sizeof(bitbuf)))); 378 } 379 380 /* 381 * check for card insertion or removal during suspend period. 382 * XXX: the code can't cope with card swap (remove then insert). 383 * how can we detect such situation? 384 */ 385 if (why == PWR_RESUME) 386 (void)pcic_intr_socket(h); 387 } 388 } 389 390 391 /* 392 * attach a socket -- we don't know about irqs yet 393 */ 394 void 395 pcic_attach_socket(h) 396 struct pcic_handle *h; 397 { 398 struct pcmciabus_attach_args paa; 399 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 400 int locs[PCMCIABUSCF_NLOCS]; 401 402 /* initialize the rest of the handle */ 403 404 h->shutdown = 0; 405 h->memalloc = 0; 406 h->ioalloc = 0; 407 h->ih_irq = 0; 408 409 /* now, config one pcmcia device per socket */ 410 411 paa.paa_busname = "pcmcia"; 412 paa.pct = (pcmcia_chipset_tag_t) sc->pct; 413 paa.pch = (pcmcia_chipset_handle_t) h; 414 paa.iobase = sc->iobase; 415 paa.iosize = sc->iosize; 416 417 locs[PCMCIABUSCF_CONTROLLER] = h->chip; 418 locs[PCMCIABUSCF_SOCKET] = h->socket; 419 420 h->pcmcia = config_found_sm_loc(&sc->dev, "pcmciabus", locs, &paa, 421 pcic_print, config_stdsubmatch); 422 if (h->pcmcia == NULL) { 423 h->flags &= ~PCIC_FLAG_SOCKETP; 424 return; 425 } 426 427 /* 428 * queue creation of a kernel thread to handle insert/removal events. 429 */ 430 #ifdef DIAGNOSTIC 431 if (h->event_thread != NULL) 432 panic("pcic_attach_socket: event thread"); 433 #endif 434 config_pending_incr(); 435 kthread_create(pcic_create_event_thread, h); 436 } 437 438 /* 439 * now finish attaching the sockets, we are ready to allocate 440 * interrupts 441 */ 442 void 443 pcic_attach_sockets_finish(sc) 444 struct pcic_softc *sc; 445 { 446 int i; 447 448 for (i = 0; i < __arraycount(sc->handle); i++) 449 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 450 pcic_attach_socket_finish(&sc->handle[i]); 451 } 452 453 /* 454 * finishing attaching the socket. Interrupts may now be on 455 * if so expects the pcic interrupt to be blocked 456 */ 457 void 458 pcic_attach_socket_finish(h) 459 struct pcic_handle *h; 460 { 461 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 462 int reg; 463 464 DPRINTF(("%s: attach finish socket %ld\n", h->ph_parent->dv_xname, 465 (long) (h - &sc->handle[0]))); 466 467 /* 468 * Set up a powerhook to ensure it continues to interrupt on 469 * card detect even after suspend. 470 * (this works around a bug seen in suspend-to-disk on the 471 * Sony VAIO Z505; on resume, the CSC_INTR state is not preserved). 472 */ 473 powerhook_establish(h->ph_parent->dv_xname, pcic_power, h); 474 475 /* enable interrupts on card detect, poll for them if no irq avail */ 476 reg = PCIC_CSC_INTR_CD_ENABLE; 477 if (sc->irq == -1) { 478 if (sc->poll_established == 0) { 479 callout_init(&sc->poll_ch); 480 callout_reset(&sc->poll_ch, hz / 2, pcic_poll_intr, sc); 481 sc->poll_established = 1; 482 } 483 } else 484 reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT; 485 pcic_write(h, PCIC_CSC_INTR, reg); 486 487 /* steer above mgmt interrupt to configured place */ 488 if (sc->irq == 0) 489 pcic_write(h, PCIC_INTR, PCIC_INTR_ENABLE); 490 491 /* clear possible card detect interrupt */ 492 (void) pcic_read(h, PCIC_CSC); 493 494 DPRINTF(("%s: attach finish vendor 0x%02x\n", h->ph_parent->dv_xname, 495 h->vendor)); 496 497 /* unsleep the cirrus controller */ 498 if (h->vendor == PCIC_VENDOR_CIRRUS_PD67XX) { 499 reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2); 500 if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) { 501 DPRINTF(("%s: socket %02x was suspended\n", 502 h->ph_parent->dv_xname, h->sock)); 503 reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND; 504 pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg); 505 } 506 } 507 508 /* if there's a card there, then attach it. */ 509 reg = pcic_read(h, PCIC_IF_STATUS); 510 if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) == 511 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 512 pcic_queue_event(h, PCIC_EVENT_INSERTION); 513 h->laststate = PCIC_LASTSTATE_PRESENT; 514 } else { 515 h->laststate = PCIC_LASTSTATE_EMPTY; 516 } 517 } 518 519 void 520 pcic_create_event_thread(arg) 521 void *arg; 522 { 523 struct pcic_handle *h = arg; 524 char cs[4]; 525 526 snprintf(cs, sizeof(cs), "%d,%d", h->chip, h->socket); 527 528 if (kthread_create1(pcic_event_thread, h, &h->event_thread, 529 "%s,%s", h->ph_parent->dv_xname, cs)) { 530 printf("%s: unable to create event thread for sock 0x%02x\n", 531 h->ph_parent->dv_xname, h->sock); 532 panic("pcic_create_event_thread"); 533 } 534 } 535 536 void 537 pcic_event_thread(arg) 538 void *arg; 539 { 540 struct pcic_handle *h = arg; 541 struct pcic_event *pe; 542 int s, first = 1; 543 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 544 545 while (h->shutdown == 0) { 546 /* 547 * Serialize event processing on the PCIC. We may 548 * sleep while we hold this lock. 549 */ 550 (void) lockmgr(&sc->sc_pcic_lock, LK_EXCLUSIVE, NULL); 551 552 s = splhigh(); 553 if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) { 554 splx(s); 555 if (first) { 556 first = 0; 557 config_pending_decr(); 558 } 559 /* 560 * No events to process; release the PCIC lock. 561 */ 562 (void) lockmgr(&sc->sc_pcic_lock, LK_RELEASE, NULL); 563 (void) tsleep(&h->events, PWAIT, "pcicev", 0); 564 continue; 565 } else { 566 splx(s); 567 /* sleep .25s to be enqueued chatterling interrupts */ 568 (void) tsleep((caddr_t)pcic_event_thread, PWAIT, 569 "pcicss", hz/4); 570 } 571 s = splhigh(); 572 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 573 splx(s); 574 575 switch (pe->pe_type) { 576 case PCIC_EVENT_INSERTION: 577 s = splhigh(); 578 while (1) { 579 struct pcic_event *pe1, *pe2; 580 581 if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL) 582 break; 583 if (pe1->pe_type != PCIC_EVENT_REMOVAL) 584 break; 585 if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL) 586 break; 587 if (pe2->pe_type == PCIC_EVENT_INSERTION) { 588 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 589 free(pe1, M_TEMP); 590 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 591 free(pe2, M_TEMP); 592 } 593 } 594 splx(s); 595 596 DPRINTF(("%s: insertion event\n", 597 h->ph_parent->dv_xname)); 598 pcic_attach_card(h); 599 break; 600 601 case PCIC_EVENT_REMOVAL: 602 s = splhigh(); 603 while (1) { 604 struct pcic_event *pe1, *pe2; 605 606 if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL) 607 break; 608 if (pe1->pe_type != PCIC_EVENT_INSERTION) 609 break; 610 if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL) 611 break; 612 if (pe2->pe_type == PCIC_EVENT_REMOVAL) { 613 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 614 free(pe1, M_TEMP); 615 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 616 free(pe2, M_TEMP); 617 } 618 } 619 splx(s); 620 621 DPRINTF(("%s: removal event\n", 622 h->ph_parent->dv_xname)); 623 pcic_detach_card(h, DETACH_FORCE); 624 break; 625 626 default: 627 panic("pcic_event_thread: unknown event %d", 628 pe->pe_type); 629 } 630 free(pe, M_TEMP); 631 632 (void) lockmgr(&sc->sc_pcic_lock, LK_RELEASE, NULL); 633 } 634 635 h->event_thread = NULL; 636 637 /* In case parent is waiting for us to exit. */ 638 wakeup(sc); 639 640 kthread_exit(0); 641 } 642 643 int 644 pcic_print(arg, pnp) 645 void *arg; 646 const char *pnp; 647 { 648 struct pcmciabus_attach_args *paa = arg; 649 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 650 651 /* Only "pcmcia"s can attach to "pcic"s... easy. */ 652 if (pnp) 653 aprint_normal("pcmcia at %s", pnp); 654 655 aprint_normal(" controller %d socket %d", h->chip, h->socket); 656 657 return (UNCONF); 658 } 659 660 void 661 pcic_poll_intr(arg) 662 void *arg; 663 { 664 struct pcic_softc *sc; 665 int i, s; 666 667 s = spltty(); 668 sc = arg; 669 for (i = 0; i < __arraycount(sc->handle); i++) 670 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 671 (void)pcic_intr_socket(&sc->handle[i]); 672 callout_reset(&sc->poll_ch, hz / 2, pcic_poll_intr, sc); 673 splx(s); 674 } 675 676 int 677 pcic_intr(arg) 678 void *arg; 679 { 680 struct pcic_softc *sc = arg; 681 int i, ret = 0; 682 683 DPRINTF(("%s: intr\n", sc->dev.dv_xname)); 684 685 for (i = 0; i < __arraycount(sc->handle); i++) 686 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 687 ret += pcic_intr_socket(&sc->handle[i]); 688 689 return (ret ? 1 : 0); 690 } 691 692 int 693 pcic_intr_socket(h) 694 struct pcic_handle *h; 695 { 696 int cscreg; 697 698 cscreg = pcic_read(h, PCIC_CSC); 699 700 cscreg &= (PCIC_CSC_GPI | 701 PCIC_CSC_CD | 702 PCIC_CSC_READY | 703 PCIC_CSC_BATTWARN | 704 PCIC_CSC_BATTDEAD); 705 706 if (cscreg & PCIC_CSC_GPI) { 707 DPRINTF(("%s: %02x GPI\n", h->ph_parent->dv_xname, h->sock)); 708 } 709 if (cscreg & PCIC_CSC_CD) { 710 int statreg; 711 712 statreg = pcic_read(h, PCIC_IF_STATUS); 713 714 DPRINTF(("%s: %02x CD %x\n", h->ph_parent->dv_xname, h->sock, 715 statreg)); 716 717 if ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 718 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 719 if (h->laststate != PCIC_LASTSTATE_PRESENT) { 720 DPRINTF(("%s: enqueing INSERTION event\n", 721 h->ph_parent->dv_xname)); 722 pcic_queue_event(h, PCIC_EVENT_INSERTION); 723 } 724 h->laststate = PCIC_LASTSTATE_PRESENT; 725 } else { 726 if (h->laststate == PCIC_LASTSTATE_PRESENT) { 727 /* Deactivate the card now. */ 728 DPRINTF(("%s: deactivating card\n", 729 h->ph_parent->dv_xname)); 730 pcic_deactivate_card(h); 731 732 DPRINTF(("%s: enqueing REMOVAL event\n", 733 h->ph_parent->dv_xname)); 734 pcic_queue_event(h, PCIC_EVENT_REMOVAL); 735 } 736 h->laststate = PCIC_LASTSTATE_EMPTY; 737 } 738 } 739 if (cscreg & PCIC_CSC_READY) { 740 DPRINTF(("%s: %02x READY\n", h->ph_parent->dv_xname, h->sock)); 741 /* shouldn't happen */ 742 } 743 if (cscreg & PCIC_CSC_BATTWARN) { 744 DPRINTF(("%s: %02x BATTWARN\n", h->ph_parent->dv_xname, 745 h->sock)); 746 } 747 if (cscreg & PCIC_CSC_BATTDEAD) { 748 DPRINTF(("%s: %02x BATTDEAD\n", h->ph_parent->dv_xname, 749 h->sock)); 750 } 751 return (cscreg ? 1 : 0); 752 } 753 754 void 755 pcic_queue_event(h, event) 756 struct pcic_handle *h; 757 int event; 758 { 759 struct pcic_event *pe; 760 int s; 761 762 pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT); 763 if (pe == NULL) 764 panic("pcic_queue_event: can't allocate event"); 765 766 pe->pe_type = event; 767 s = splhigh(); 768 SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q); 769 splx(s); 770 wakeup(&h->events); 771 } 772 773 void 774 pcic_attach_card(h) 775 struct pcic_handle *h; 776 { 777 778 if (!(h->flags & PCIC_FLAG_CARDP)) { 779 /* call the MI attach function */ 780 pcmcia_card_attach(h->pcmcia); 781 782 h->flags |= PCIC_FLAG_CARDP; 783 } else { 784 DPRINTF(("pcic_attach_card: already attached")); 785 } 786 } 787 788 void 789 pcic_detach_card(h, flags) 790 struct pcic_handle *h; 791 int flags; /* DETACH_* */ 792 { 793 794 if (h->flags & PCIC_FLAG_CARDP) { 795 h->flags &= ~PCIC_FLAG_CARDP; 796 797 /* call the MI detach function */ 798 pcmcia_card_detach(h->pcmcia, flags); 799 } else { 800 DPRINTF(("pcic_detach_card: already detached")); 801 } 802 } 803 804 void 805 pcic_deactivate_card(h) 806 struct pcic_handle *h; 807 { 808 int intr; 809 810 /* call the MI deactivate function */ 811 pcmcia_card_deactivate(h->pcmcia); 812 813 /* reset the socket */ 814 intr = pcic_read(h, PCIC_INTR); 815 intr &= PCIC_INTR_ENABLE; 816 pcic_write(h, PCIC_INTR, intr); 817 818 /* power down the socket */ 819 pcic_write(h, PCIC_PWRCTL, 0); 820 } 821 822 int 823 pcic_chip_mem_alloc(pch, size, pcmhp) 824 pcmcia_chipset_handle_t pch; 825 bus_size_t size; 826 struct pcmcia_mem_handle *pcmhp; 827 { 828 struct pcic_handle *h = (struct pcic_handle *) pch; 829 bus_space_handle_t memh; 830 bus_addr_t addr; 831 bus_size_t sizepg; 832 int i, mask, mhandle; 833 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 834 835 /* out of sc->memh, allocate as many pages as necessary */ 836 837 /* convert size to PCIC pages */ 838 sizepg = (size + (PCIC_MEM_ALIGN - 1)) / PCIC_MEM_ALIGN; 839 if (sizepg > PCIC_MAX_MEM_PAGES) 840 return (1); 841 842 mask = (1 << sizepg) - 1; 843 844 addr = 0; /* XXX gcc -Wuninitialized */ 845 mhandle = 0; /* XXX gcc -Wuninitialized */ 846 847 for (i = 0; i <= PCIC_MAX_MEM_PAGES - sizepg; i++) { 848 if ((sc->subregionmask & (mask << i)) == (mask << i)) { 849 if (bus_space_subregion(sc->memt, sc->memh, 850 i * PCIC_MEM_PAGESIZE, 851 sizepg * PCIC_MEM_PAGESIZE, &memh)) 852 return (1); 853 mhandle = mask << i; 854 addr = sc->membase + (i * PCIC_MEM_PAGESIZE); 855 sc->subregionmask &= ~(mhandle); 856 pcmhp->memt = sc->memt; 857 pcmhp->memh = memh; 858 pcmhp->addr = addr; 859 pcmhp->size = size; 860 pcmhp->mhandle = mhandle; 861 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 862 return (0); 863 } 864 } 865 866 return (1); 867 } 868 869 void 870 pcic_chip_mem_free(pch, pcmhp) 871 pcmcia_chipset_handle_t pch; 872 struct pcmcia_mem_handle *pcmhp; 873 { 874 struct pcic_handle *h = (struct pcic_handle *) pch; 875 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 876 877 sc->subregionmask |= pcmhp->mhandle; 878 } 879 880 static const struct mem_map_index_st { 881 int sysmem_start_lsb; 882 int sysmem_start_msb; 883 int sysmem_stop_lsb; 884 int sysmem_stop_msb; 885 int cardmem_lsb; 886 int cardmem_msb; 887 int memenable; 888 } mem_map_index[] = { 889 { 890 PCIC_SYSMEM_ADDR0_START_LSB, 891 PCIC_SYSMEM_ADDR0_START_MSB, 892 PCIC_SYSMEM_ADDR0_STOP_LSB, 893 PCIC_SYSMEM_ADDR0_STOP_MSB, 894 PCIC_CARDMEM_ADDR0_LSB, 895 PCIC_CARDMEM_ADDR0_MSB, 896 PCIC_ADDRWIN_ENABLE_MEM0, 897 }, 898 { 899 PCIC_SYSMEM_ADDR1_START_LSB, 900 PCIC_SYSMEM_ADDR1_START_MSB, 901 PCIC_SYSMEM_ADDR1_STOP_LSB, 902 PCIC_SYSMEM_ADDR1_STOP_MSB, 903 PCIC_CARDMEM_ADDR1_LSB, 904 PCIC_CARDMEM_ADDR1_MSB, 905 PCIC_ADDRWIN_ENABLE_MEM1, 906 }, 907 { 908 PCIC_SYSMEM_ADDR2_START_LSB, 909 PCIC_SYSMEM_ADDR2_START_MSB, 910 PCIC_SYSMEM_ADDR2_STOP_LSB, 911 PCIC_SYSMEM_ADDR2_STOP_MSB, 912 PCIC_CARDMEM_ADDR2_LSB, 913 PCIC_CARDMEM_ADDR2_MSB, 914 PCIC_ADDRWIN_ENABLE_MEM2, 915 }, 916 { 917 PCIC_SYSMEM_ADDR3_START_LSB, 918 PCIC_SYSMEM_ADDR3_START_MSB, 919 PCIC_SYSMEM_ADDR3_STOP_LSB, 920 PCIC_SYSMEM_ADDR3_STOP_MSB, 921 PCIC_CARDMEM_ADDR3_LSB, 922 PCIC_CARDMEM_ADDR3_MSB, 923 PCIC_ADDRWIN_ENABLE_MEM3, 924 }, 925 { 926 PCIC_SYSMEM_ADDR4_START_LSB, 927 PCIC_SYSMEM_ADDR4_START_MSB, 928 PCIC_SYSMEM_ADDR4_STOP_LSB, 929 PCIC_SYSMEM_ADDR4_STOP_MSB, 930 PCIC_CARDMEM_ADDR4_LSB, 931 PCIC_CARDMEM_ADDR4_MSB, 932 PCIC_ADDRWIN_ENABLE_MEM4, 933 }, 934 }; 935 936 void 937 pcic_chip_do_mem_map(h, win) 938 struct pcic_handle *h; 939 int win; 940 { 941 int reg; 942 int kind = h->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 943 int mem8 = 944 (h->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 945 || (kind == PCMCIA_MEM_ATTR); 946 947 DPRINTF(("mem8 %d\n", mem8)); 948 /* mem8 = 1; */ 949 950 pcic_write(h, mem_map_index[win].sysmem_start_lsb, 951 (h->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 952 pcic_write(h, mem_map_index[win].sysmem_start_msb, 953 ((h->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 954 PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK) | 955 (mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT)); 956 957 pcic_write(h, mem_map_index[win].sysmem_stop_lsb, 958 ((h->mem[win].addr + h->mem[win].size) >> 959 PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 960 pcic_write(h, mem_map_index[win].sysmem_stop_msb, 961 (((h->mem[win].addr + h->mem[win].size) >> 962 (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 963 PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) | 964 PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2); 965 966 pcic_write(h, mem_map_index[win].cardmem_lsb, 967 (h->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff); 968 pcic_write(h, mem_map_index[win].cardmem_msb, 969 ((h->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) & 970 PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) | 971 ((kind == PCMCIA_MEM_ATTR) ? 972 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0)); 973 974 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 975 reg |= (mem_map_index[win].memenable | PCIC_ADDRWIN_ENABLE_MEMCS16); 976 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 977 978 delay(100); 979 980 #ifdef PCICDEBUG 981 { 982 int r1, r2, r3, r4, r5, r6; 983 984 r1 = pcic_read(h, mem_map_index[win].sysmem_start_msb); 985 r2 = pcic_read(h, mem_map_index[win].sysmem_start_lsb); 986 r3 = pcic_read(h, mem_map_index[win].sysmem_stop_msb); 987 r4 = pcic_read(h, mem_map_index[win].sysmem_stop_lsb); 988 r5 = pcic_read(h, mem_map_index[win].cardmem_msb); 989 r6 = pcic_read(h, mem_map_index[win].cardmem_lsb); 990 991 DPRINTF(("pcic_chip_do_mem_map window %d: %02x%02x %02x%02x " 992 "%02x%02x\n", win, r1, r2, r3, r4, r5, r6)); 993 } 994 #endif 995 } 996 997 int 998 pcic_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 999 pcmcia_chipset_handle_t pch; 1000 int kind; 1001 bus_addr_t card_addr; 1002 bus_size_t size; 1003 struct pcmcia_mem_handle *pcmhp; 1004 bus_size_t *offsetp; 1005 int *windowp; 1006 { 1007 struct pcic_handle *h = (struct pcic_handle *) pch; 1008 bus_addr_t busaddr; 1009 long card_offset; 1010 int i, win; 1011 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 1012 1013 win = -1; 1014 for (i = 0; i < (sizeof(mem_map_index) / sizeof(mem_map_index[0])); 1015 i++) { 1016 if ((h->memalloc & (1 << i)) == 0) { 1017 win = i; 1018 h->memalloc |= (1 << i); 1019 break; 1020 } 1021 } 1022 1023 if (win == -1) 1024 return (1); 1025 1026 *windowp = win; 1027 1028 /* XXX this is pretty gross */ 1029 1030 if (sc->memt != pcmhp->memt) 1031 panic("pcic_chip_mem_map memt is bogus"); 1032 1033 busaddr = pcmhp->addr; 1034 1035 /* 1036 * compute the address offset to the pcmcia address space for the 1037 * pcic. this is intentionally signed. The masks and shifts below 1038 * will cause TRT to happen in the pcic registers. Deal with making 1039 * sure the address is aligned, and return the alignment offset. 1040 */ 1041 1042 *offsetp = card_addr % PCIC_MEM_ALIGN; 1043 card_addr -= *offsetp; 1044 1045 DPRINTF(("pcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 1046 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 1047 (u_long) card_addr)); 1048 1049 /* 1050 * include the offset in the size, and decrement size by one, since 1051 * the hw wants start/stop 1052 */ 1053 size += *offsetp - 1; 1054 1055 card_offset = (((long) card_addr) - ((long) busaddr)); 1056 1057 h->mem[win].addr = busaddr; 1058 h->mem[win].size = size; 1059 h->mem[win].offset = card_offset; 1060 h->mem[win].kind = kind; 1061 1062 pcic_chip_do_mem_map(h, win); 1063 1064 return (0); 1065 } 1066 1067 void 1068 pcic_chip_mem_unmap(pch, window) 1069 pcmcia_chipset_handle_t pch; 1070 int window; 1071 { 1072 struct pcic_handle *h = (struct pcic_handle *) pch; 1073 int reg; 1074 1075 if (window >= (sizeof(mem_map_index) / sizeof(mem_map_index[0]))) 1076 panic("pcic_chip_mem_unmap: window out of range"); 1077 1078 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1079 reg &= ~mem_map_index[window].memenable; 1080 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1081 1082 h->memalloc &= ~(1 << window); 1083 } 1084 1085 int 1086 pcic_chip_io_alloc(pch, start, size, align, pcihp) 1087 pcmcia_chipset_handle_t pch; 1088 bus_addr_t start; 1089 bus_size_t size; 1090 bus_size_t align; 1091 struct pcmcia_io_handle *pcihp; 1092 { 1093 struct pcic_handle *h = (struct pcic_handle *) pch; 1094 bus_space_tag_t iot; 1095 bus_space_handle_t ioh; 1096 bus_addr_t ioaddr; 1097 int flags = 0; 1098 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 1099 1100 /* 1101 * Allocate some arbitrary I/O space. 1102 */ 1103 1104 iot = sc->iot; 1105 1106 if (start) { 1107 ioaddr = start; 1108 if (bus_space_map(iot, start, size, 0, &ioh)) 1109 return (1); 1110 DPRINTF(("pcic_chip_io_alloc map port %lx+%lx\n", 1111 (u_long) ioaddr, (u_long) size)); 1112 } else { 1113 flags |= PCMCIA_IO_ALLOCATED; 1114 if (bus_space_alloc(iot, sc->iobase, 1115 sc->iobase + sc->iosize, size, align, 0, 0, 1116 &ioaddr, &ioh)) 1117 return (1); 1118 DPRINTF(("pcic_chip_io_alloc alloc port %lx+%lx\n", 1119 (u_long) ioaddr, (u_long) size)); 1120 } 1121 1122 pcihp->iot = iot; 1123 pcihp->ioh = ioh; 1124 pcihp->addr = ioaddr; 1125 pcihp->size = size; 1126 pcihp->flags = flags; 1127 1128 return (0); 1129 } 1130 1131 void 1132 pcic_chip_io_free(pcmcia_chipset_handle_t pch, 1133 struct pcmcia_io_handle *pcihp) 1134 { 1135 bus_space_tag_t iot = pcihp->iot; 1136 bus_space_handle_t ioh = pcihp->ioh; 1137 bus_size_t size = pcihp->size; 1138 1139 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1140 bus_space_free(iot, ioh, size); 1141 else 1142 bus_space_unmap(iot, ioh, size); 1143 } 1144 1145 1146 static const struct io_map_index_st { 1147 int start_lsb; 1148 int start_msb; 1149 int stop_lsb; 1150 int stop_msb; 1151 int ioenable; 1152 int ioctlmask; 1153 int ioctlbits[3]; /* indexed by PCMCIA_WIDTH_* */ 1154 } io_map_index[] = { 1155 { 1156 PCIC_IOADDR0_START_LSB, 1157 PCIC_IOADDR0_START_MSB, 1158 PCIC_IOADDR0_STOP_LSB, 1159 PCIC_IOADDR0_STOP_MSB, 1160 PCIC_ADDRWIN_ENABLE_IO0, 1161 PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1162 PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK, 1163 { 1164 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1165 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1166 PCIC_IOCTL_IO0_DATASIZE_8BIT, 1167 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1168 PCIC_IOCTL_IO0_DATASIZE_16BIT, 1169 }, 1170 }, 1171 { 1172 PCIC_IOADDR1_START_LSB, 1173 PCIC_IOADDR1_START_MSB, 1174 PCIC_IOADDR1_STOP_LSB, 1175 PCIC_IOADDR1_STOP_MSB, 1176 PCIC_ADDRWIN_ENABLE_IO1, 1177 PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1178 PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK, 1179 { 1180 PCIC_IOCTL_IO1_IOCS16SRC_CARD, 1181 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1182 PCIC_IOCTL_IO1_DATASIZE_8BIT, 1183 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1184 PCIC_IOCTL_IO1_DATASIZE_16BIT, 1185 }, 1186 }, 1187 }; 1188 1189 void 1190 pcic_chip_do_io_map(h, win) 1191 struct pcic_handle *h; 1192 int win; 1193 { 1194 int reg; 1195 1196 DPRINTF(("pcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 1197 win, (long) h->io[win].addr, (long) h->io[win].size, 1198 h->io[win].width * 8)); 1199 1200 pcic_write(h, io_map_index[win].start_lsb, h->io[win].addr & 0xff); 1201 pcic_write(h, io_map_index[win].start_msb, 1202 (h->io[win].addr >> 8) & 0xff); 1203 1204 pcic_write(h, io_map_index[win].stop_lsb, 1205 (h->io[win].addr + h->io[win].size - 1) & 0xff); 1206 pcic_write(h, io_map_index[win].stop_msb, 1207 ((h->io[win].addr + h->io[win].size - 1) >> 8) & 0xff); 1208 1209 reg = pcic_read(h, PCIC_IOCTL); 1210 reg &= ~io_map_index[win].ioctlmask; 1211 reg |= io_map_index[win].ioctlbits[h->io[win].width]; 1212 pcic_write(h, PCIC_IOCTL, reg); 1213 1214 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1215 reg |= io_map_index[win].ioenable; 1216 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1217 } 1218 1219 int 1220 pcic_chip_io_map(pch, width, offset, size, pcihp, windowp) 1221 pcmcia_chipset_handle_t pch; 1222 int width; 1223 bus_addr_t offset; 1224 bus_size_t size; 1225 struct pcmcia_io_handle *pcihp; 1226 int *windowp; 1227 { 1228 struct pcic_handle *h = (struct pcic_handle *) pch; 1229 bus_addr_t ioaddr = pcihp->addr + offset; 1230 int i, win; 1231 #ifdef PCICDEBUG 1232 static const char *width_names[] = { "auto", "io8", "io16" }; 1233 #endif 1234 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 1235 1236 /* XXX Sanity check offset/size. */ 1237 1238 win = -1; 1239 for (i = 0; i < (sizeof(io_map_index) / sizeof(io_map_index[0])); i++) { 1240 if ((h->ioalloc & (1 << i)) == 0) { 1241 win = i; 1242 h->ioalloc |= (1 << i); 1243 break; 1244 } 1245 } 1246 1247 if (win == -1) 1248 return (1); 1249 1250 *windowp = win; 1251 1252 /* XXX this is pretty gross */ 1253 1254 if (sc->iot != pcihp->iot) 1255 panic("pcic_chip_io_map iot is bogus"); 1256 1257 DPRINTF(("pcic_chip_io_map window %d %s port %lx+%lx\n", 1258 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1259 1260 /* XXX wtf is this doing here? */ 1261 1262 printf("%s: port 0x%lx", sc->dev.dv_xname, (u_long) ioaddr); 1263 if (size > 1) 1264 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1265 printf("\n"); 1266 1267 h->io[win].addr = ioaddr; 1268 h->io[win].size = size; 1269 h->io[win].width = width; 1270 1271 pcic_chip_do_io_map(h, win); 1272 1273 return (0); 1274 } 1275 1276 void 1277 pcic_chip_io_unmap(pch, window) 1278 pcmcia_chipset_handle_t pch; 1279 int window; 1280 { 1281 struct pcic_handle *h = (struct pcic_handle *) pch; 1282 int reg; 1283 1284 if (window >= (sizeof(io_map_index) / sizeof(io_map_index[0]))) 1285 panic("pcic_chip_io_unmap: window out of range"); 1286 1287 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1288 reg &= ~io_map_index[window].ioenable; 1289 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1290 1291 h->ioalloc &= ~(1 << window); 1292 } 1293 1294 static int 1295 pcic_wait_ready(h) 1296 struct pcic_handle *h; 1297 { 1298 u_int8_t stat; 1299 int i; 1300 1301 /* wait an initial 10ms for quick cards */ 1302 stat = pcic_read(h, PCIC_IF_STATUS); 1303 if (stat & PCIC_IF_STATUS_READY) 1304 return (0); 1305 pcic_delay(h, 10, "pccwr0"); 1306 for (i = 0; i < 50; i++) { 1307 stat = pcic_read(h, PCIC_IF_STATUS); 1308 if (stat & PCIC_IF_STATUS_READY) 1309 return (0); 1310 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 1311 PCIC_IF_STATUS_CARDDETECT_PRESENT) 1312 return (ENXIO); 1313 /* wait .1s (100ms) each iteration now */ 1314 pcic_delay(h, 100, "pccwr1"); 1315 } 1316 1317 printf("pcic_wait_ready: ready never happened, status=%02x\n", stat); 1318 return (EWOULDBLOCK); 1319 } 1320 1321 /* 1322 * Perform long (msec order) delay. 1323 */ 1324 static void 1325 pcic_delay(h, timo, wmesg) 1326 struct pcic_handle *h; 1327 int timo; /* in ms. must not be zero */ 1328 const char *wmesg; 1329 { 1330 1331 #ifdef DIAGNOSTIC 1332 if (timo <= 0) 1333 panic("pcic_delay: called with timeout %d", timo); 1334 if (!curlwp) 1335 panic("pcic_delay: called in interrupt context"); 1336 if (!h->event_thread) 1337 panic("pcic_delay: no event thread"); 1338 #endif 1339 DPRINTF(("pcic_delay: \"%s\" %p, sleep %d ms\n", 1340 wmesg, h->event_thread, timo)); 1341 tsleep(pcic_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 1342 } 1343 1344 void 1345 pcic_chip_socket_enable(pch) 1346 pcmcia_chipset_handle_t pch; 1347 { 1348 struct pcic_handle *h = (struct pcic_handle *) pch; 1349 int win; 1350 u_int8_t power, intr; 1351 #ifdef DIAGNOSTIC 1352 int reg; 1353 #endif 1354 1355 #ifdef DIAGNOSTIC 1356 if (h->flags & PCIC_FLAG_ENABLED) 1357 printf("pcic_chip_socket_enable: enabling twice\n"); 1358 #endif 1359 1360 /* disable interrupts; assert RESET */ 1361 intr = pcic_read(h, PCIC_INTR); 1362 intr &= PCIC_INTR_ENABLE; 1363 pcic_write(h, PCIC_INTR, intr); 1364 1365 /* zero out the address windows */ 1366 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1367 1368 /* power off; assert output enable bit */ 1369 power = PCIC_PWRCTL_OE; 1370 pcic_write(h, PCIC_PWRCTL, power); 1371 1372 /* 1373 * power hack for RICOH RF5C[23]96 1374 */ 1375 switch( h->vendor ) { 1376 case PCIC_VENDOR_RICOH_5C296: 1377 case PCIC_VENDOR_RICOH_5C396: 1378 { 1379 int regtmp; 1380 regtmp = pcic_read(h, PCIC_RICOH_REG_MCR2); 1381 #ifdef RICOH_POWER_HACK 1382 regtmp |= PCIC_RICOH_MCR2_VCC_DIRECT; 1383 #else 1384 regtmp &= ~(PCIC_RICOH_MCR2_VCC_DIRECT|PCIC_RICOH_MCR2_VCC_SEL_3V); 1385 #endif 1386 pcic_write(h, PCIC_RICOH_REG_MCR2, regtmp); 1387 } 1388 break; 1389 default: 1390 break; 1391 } 1392 1393 #ifdef VADEM_POWER_HACK 1394 bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x0e); 1395 bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x37); 1396 printf("prcr = %02x\n", pcic_read(h, 0x02)); 1397 printf("cvsr = %02x\n", pcic_read(h, 0x2f)); 1398 printf("DANGER WILL ROBINSON! Changing voltage select!\n"); 1399 pcic_write(h, 0x2f, pcic_read(h, 0x2f) & ~0x03); 1400 printf("cvsr = %02x\n", pcic_read(h, 0x2f)); 1401 #endif 1402 1403 /* power up the socket */ 1404 power |= PCIC_PWRCTL_PWR_ENABLE | PCIC_PWRCTL_VPP1_VCC; 1405 pcic_write(h, PCIC_PWRCTL, power); 1406 1407 /* 1408 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 1409 * Vcc Rising Time (Tpr) = 100ms 1410 * RESET Width (Th (Hi-z RESET)) = 1ms 1411 * RESET Width (Tw (RESET)) = 10us 1412 * 1413 * some machines require some more time to be settled 1414 * (100ms is added here). 1415 */ 1416 pcic_delay(h, 200 + 1, "pccen1"); 1417 1418 /* negate RESET */ 1419 intr |= PCIC_INTR_RESET; 1420 pcic_write(h, PCIC_INTR, intr); 1421 1422 /* 1423 * RESET Setup Time (Tsu (RESET)) = 20ms 1424 */ 1425 pcic_delay(h, 20, "pccen2"); 1426 1427 #ifdef DIAGNOSTIC 1428 reg = pcic_read(h, PCIC_IF_STATUS); 1429 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 1430 printf("pcic_chip_socket_enable: no power, status=%x\n", reg); 1431 #endif 1432 1433 /* wait for the chip to finish initializing */ 1434 if (pcic_wait_ready(h)) { 1435 /* XXX return a failure status?? */ 1436 pcic_write(h, PCIC_PWRCTL, 0); 1437 return; 1438 } 1439 1440 /* reinstall all the memory and io mappings */ 1441 for (win = 0; win < PCIC_MEM_WINS; win++) 1442 if (h->memalloc & (1 << win)) 1443 pcic_chip_do_mem_map(h, win); 1444 for (win = 0; win < PCIC_IO_WINS; win++) 1445 if (h->ioalloc & (1 << win)) 1446 pcic_chip_do_io_map(h, win); 1447 1448 h->flags |= PCIC_FLAG_ENABLED; 1449 } 1450 1451 void 1452 pcic_chip_socket_disable(pch) 1453 pcmcia_chipset_handle_t pch; 1454 { 1455 struct pcic_handle *h = (struct pcic_handle *) pch; 1456 u_int8_t intr; 1457 1458 DPRINTF(("pcic_chip_socket_disable\n")); 1459 1460 /* disable interrupts; assert RESET */ 1461 intr = pcic_read(h, PCIC_INTR); 1462 intr &= PCIC_INTR_ENABLE; 1463 pcic_write(h, PCIC_INTR, intr); 1464 1465 /* zero out the address windows */ 1466 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1467 1468 /* disable socket: negate output enable bit and power off */ 1469 pcic_write(h, PCIC_PWRCTL, 0); 1470 1471 /* 1472 * Vcc Falling Time (Tpf) = 300ms 1473 */ 1474 pcic_delay(h, 300, "pccwr1"); 1475 1476 h->flags &= ~PCIC_FLAG_ENABLED; 1477 } 1478 1479 void 1480 pcic_chip_socket_settype(pch, type) 1481 pcmcia_chipset_handle_t pch; 1482 int type; 1483 { 1484 struct pcic_handle *h = (struct pcic_handle *) pch; 1485 int intr; 1486 1487 intr = pcic_read(h, PCIC_INTR); 1488 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 1489 if (type == PCMCIA_IFTYPE_IO) { 1490 intr |= PCIC_INTR_CARDTYPE_IO; 1491 intr |= h->ih_irq << PCIC_INTR_IRQ_SHIFT; 1492 } else 1493 intr |= PCIC_INTR_CARDTYPE_MEM; 1494 pcic_write(h, PCIC_INTR, intr); 1495 1496 DPRINTF(("%s: pcic_chip_socket_settype %02x type %s %02x\n", 1497 h->ph_parent->dv_xname, h->sock, 1498 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 1499 } 1500 1501 static u_int8_t 1502 st_pcic_read(h, idx) 1503 struct pcic_handle *h; 1504 int idx; 1505 { 1506 1507 if (idx != -1) 1508 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX, 1509 h->sock + idx); 1510 return (bus_space_read_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA)); 1511 } 1512 1513 static void 1514 st_pcic_write(h, idx, data) 1515 struct pcic_handle *h; 1516 int idx; 1517 u_int8_t data; 1518 { 1519 1520 if (idx != -1) 1521 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX, 1522 h->sock + idx); 1523 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA, data); 1524 }
Cache object: 4e9643b8abc4bb039418f2161af0e61c
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