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sys/dev/ic/i82365.c
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1 /* $NetBSD: i82365.c,v 1.102.14.1 2009/08/14 21:37:03 snj Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Charles M. Hannum. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 */ 20 21 /* 22 * Copyright (c) 2000 Christian E. Hopps. All rights reserved. 23 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 24 * 25 * Redistribution and use in source and binary forms, with or without 26 * modification, are permitted provided that the following conditions 27 * are met: 28 * 1. Redistributions of source code must retain the above copyright 29 * notice, this list of conditions and the following disclaimer. 30 * 2. Redistributions in binary form must reproduce the above copyright 31 * notice, this list of conditions and the following disclaimer in the 32 * documentation and/or other materials provided with the distribution. 33 * 3. All advertising materials mentioning features or use of this software 34 * must display the following acknowledgement: 35 * This product includes software developed by Marc Horowitz. 36 * 4. The name of the author may not be used to endorse or promote products 37 * derived from this software without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 40 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 41 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 42 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 43 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 44 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 45 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 46 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 47 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 48 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: i82365.c,v 1.102.14.1 2009/08/14 21:37:03 snj Exp $"); 53 54 #define PCICDEBUG 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/device.h> 59 #include <sys/extent.h> 60 #include <sys/kernel.h> 61 #include <sys/malloc.h> 62 #include <sys/kthread.h> 63 64 #include <sys/bus.h> 65 #include <sys/intr.h> 66 67 #include <dev/pcmcia/pcmciareg.h> 68 #include <dev/pcmcia/pcmciavar.h> 69 70 #include <dev/ic/i82365reg.h> 71 #include <dev/ic/i82365var.h> 72 73 #include "locators.h" 74 75 #ifdef PCICDEBUG 76 int pcic_debug = 0; 77 #define DPRINTF(arg) if (pcic_debug) printf arg; 78 #else 79 #define DPRINTF(arg) 80 #endif 81 82 /* 83 * Individual drivers will allocate their own memory and io regions. Memory 84 * regions must be a multiple of 4k, aligned on a 4k boundary. 85 */ 86 87 #define PCIC_MEM_ALIGN PCIC_MEM_PAGESIZE 88 89 void pcic_attach_socket(struct pcic_handle *); 90 void pcic_attach_socket_finish(struct pcic_handle *); 91 92 int pcic_print (void *arg, const char *pnp); 93 int pcic_intr_socket(struct pcic_handle *); 94 void pcic_poll_intr(void *); 95 96 void pcic_attach_card(struct pcic_handle *); 97 void pcic_detach_card(struct pcic_handle *, int); 98 void pcic_deactivate_card(struct pcic_handle *); 99 100 void pcic_chip_do_mem_map(struct pcic_handle *, int); 101 void pcic_chip_do_io_map(struct pcic_handle *, int); 102 103 void pcic_event_thread(void *); 104 105 void pcic_queue_event(struct pcic_handle *, int); 106 void pcic_power(int, void *); 107 108 static int pcic_wait_ready(struct pcic_handle *); 109 static void pcic_delay(struct pcic_handle *, int, const char *); 110 111 static u_int8_t st_pcic_read(struct pcic_handle *, int); 112 static void st_pcic_write(struct pcic_handle *, int, u_int8_t); 113 114 int 115 pcic_ident_ok(ident) 116 int ident; 117 { 118 /* this is very empirical and heuristic */ 119 120 if ((ident == 0) || (ident == 0xff) || (ident & PCIC_IDENT_ZERO)) 121 return (0); 122 123 if ((ident & PCIC_IDENT_REV_MASK) == 0) 124 return (0); 125 126 if ((ident & PCIC_IDENT_IFTYPE_MASK) != PCIC_IDENT_IFTYPE_MEM_AND_IO) { 127 #ifdef DIAGNOSTIC 128 printf("pcic: does not support memory and I/O cards, " 129 "ignored (ident=%0x)\n", ident); 130 #endif 131 return (0); 132 } 133 134 return (1); 135 } 136 137 int 138 pcic_vendor(h) 139 struct pcic_handle *h; 140 { 141 int reg; 142 int vendor; 143 144 reg = pcic_read(h, PCIC_IDENT); 145 146 if ((reg & PCIC_IDENT_REV_MASK) == 0) 147 return (PCIC_VENDOR_NONE); 148 149 switch (reg) { 150 case 0x00: 151 case 0xff: 152 return (PCIC_VENDOR_NONE); 153 case PCIC_IDENT_ID_INTEL0: 154 vendor = PCIC_VENDOR_I82365SLR0; 155 break; 156 case PCIC_IDENT_ID_INTEL1: 157 vendor = PCIC_VENDOR_I82365SLR1; 158 break; 159 case PCIC_IDENT_ID_INTEL2: 160 vendor = PCIC_VENDOR_I82365SL_DF; 161 break; 162 case PCIC_IDENT_ID_IBM1: 163 case PCIC_IDENT_ID_IBM2: 164 vendor = PCIC_VENDOR_IBM; 165 break; 166 case PCIC_IDENT_ID_IBM3: 167 vendor = PCIC_VENDOR_IBM_KING; 168 break; 169 default: 170 vendor = PCIC_VENDOR_UNKNOWN; 171 break; 172 } 173 174 if (vendor == PCIC_VENDOR_I82365SLR0 || 175 vendor == PCIC_VENDOR_I82365SLR1) { 176 /* 177 * Check for Cirrus PD67xx. 178 * the chip_id of the cirrus toggles between 11 and 00 after a 179 * write. weird. 180 */ 181 pcic_write(h, PCIC_CIRRUS_CHIP_INFO, 0); 182 reg = pcic_read(h, -1); 183 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 184 PCIC_CIRRUS_CHIP_INFO_CHIP_ID) { 185 reg = pcic_read(h, -1); 186 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0) 187 return (PCIC_VENDOR_CIRRUS_PD67XX); 188 } 189 190 /* 191 * check for Ricoh RF5C[23]96 192 */ 193 reg = pcic_read(h, PCIC_RICOH_REG_CHIP_ID); 194 switch (reg) { 195 case PCIC_RICOH_CHIP_ID_5C296: 196 return (PCIC_VENDOR_RICOH_5C296); 197 case PCIC_RICOH_CHIP_ID_5C396: 198 return (PCIC_VENDOR_RICOH_5C396); 199 } 200 } 201 202 return (vendor); 203 } 204 205 const char * 206 pcic_vendor_to_string(vendor) 207 int vendor; 208 { 209 switch (vendor) { 210 case PCIC_VENDOR_I82365SLR0: 211 return ("Intel 82365SL Revision 0"); 212 case PCIC_VENDOR_I82365SLR1: 213 return ("Intel 82365SL Revision 1"); 214 case PCIC_VENDOR_CIRRUS_PD67XX: 215 return ("Cirrus PD6710/2X"); 216 case PCIC_VENDOR_I82365SL_DF: 217 return ("Intel 82365SL-DF"); 218 case PCIC_VENDOR_RICOH_5C296: 219 return ("Ricoh RF5C296"); 220 case PCIC_VENDOR_RICOH_5C396: 221 return ("Ricoh RF5C396"); 222 case PCIC_VENDOR_IBM: 223 return ("IBM PCIC"); 224 case PCIC_VENDOR_IBM_KING: 225 return ("IBM KING"); 226 } 227 228 return ("Unknown controller"); 229 } 230 231 void 232 pcic_attach(sc) 233 struct pcic_softc *sc; 234 { 235 int i, reg, chip, socket; 236 struct pcic_handle *h; 237 238 DPRINTF(("pcic ident regs:")); 239 240 mutex_init(&sc->sc_pcic_lock, MUTEX_DEFAULT, IPL_NONE); 241 242 /* find and configure for the available sockets */ 243 for (i = 0; i < __arraycount(sc->handle); i++) { 244 h = &sc->handle[i]; 245 chip = i / 2; 246 socket = i % 2; 247 248 h->ph_parent = (struct device *)sc; 249 h->chip = chip; 250 h->socket = socket; 251 h->sock = chip * PCIC_CHIP_OFFSET + socket * PCIC_SOCKET_OFFSET; 252 h->laststate = PCIC_LASTSTATE_EMPTY; 253 /* initialize pcic_read and pcic_write functions */ 254 h->ph_read = st_pcic_read; 255 h->ph_write = st_pcic_write; 256 h->ph_bus_t = sc->iot; 257 h->ph_bus_h = sc->ioh; 258 h->flags = 0; 259 260 /* need to read vendor -- for cirrus to report no xtra chip */ 261 if (socket == 0) { 262 h->vendor = pcic_vendor(h); 263 if (i < __arraycount(sc->handle) - 1) 264 (h+1)->vendor = h->vendor; 265 } 266 267 switch (h->vendor) { 268 case PCIC_VENDOR_NONE: 269 /* no chip */ 270 continue; 271 case PCIC_VENDOR_CIRRUS_PD67XX: 272 reg = pcic_read(h, PCIC_CIRRUS_CHIP_INFO); 273 if (socket == 0 || 274 (reg & PCIC_CIRRUS_CHIP_INFO_SLOTS)) 275 h->flags = PCIC_FLAG_SOCKETP; 276 break; 277 default: 278 /* 279 * During the socket probe, read the ident register 280 * twice. I don't understand why, but sometimes the 281 * clone chips in hpcmips boxes read all-0s the first 282 * time. -- mycroft 283 */ 284 reg = pcic_read(h, PCIC_IDENT); 285 DPRINTF(("socket %d ident reg 0x%02x\n", i, reg)); 286 reg = pcic_read(h, PCIC_IDENT); 287 DPRINTF(("socket %d ident reg 0x%02x\n", i, reg)); 288 if (pcic_ident_ok(reg)) 289 h->flags = PCIC_FLAG_SOCKETP; 290 break; 291 } 292 } 293 294 for (i = 0; i < __arraycount(sc->handle); i++) { 295 h = &sc->handle[i]; 296 297 if (h->flags & PCIC_FLAG_SOCKETP) { 298 SIMPLEQ_INIT(&h->events); 299 300 /* disable interrupts and leave socket in reset */ 301 pcic_write(h, PCIC_INTR, 0); 302 303 /* zero out the address windows */ 304 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 305 306 /* power down the socket */ 307 pcic_write(h, PCIC_PWRCTL, 0); 308 309 pcic_write(h, PCIC_CSC_INTR, 0); 310 (void) pcic_read(h, PCIC_CSC); 311 } 312 } 313 314 /* print detected info */ 315 for (i = 0; i < __arraycount(sc->handle) - 1; i += 2) { 316 h = &sc->handle[i]; 317 chip = i / 2; 318 319 if (h->vendor == PCIC_VENDOR_NONE) 320 continue; 321 322 aprint_normal_dev(&sc->dev, "controller %d (%s) has ", 323 chip, pcic_vendor_to_string(sc->handle[i].vendor)); 324 325 if ((h->flags & PCIC_FLAG_SOCKETP) && 326 ((h+1)->flags & PCIC_FLAG_SOCKETP)) 327 aprint_normal("sockets A and B\n"); 328 else if (h->flags & PCIC_FLAG_SOCKETP) 329 aprint_normal("socket A only\n"); 330 else if ((h+1)->flags & PCIC_FLAG_SOCKETP) 331 aprint_normal("socket B only\n"); 332 else 333 aprint_normal("no sockets\n"); 334 } 335 } 336 337 /* 338 * attach the sockets before we know what interrupts we have 339 */ 340 void 341 pcic_attach_sockets(sc) 342 struct pcic_softc *sc; 343 { 344 int i; 345 346 for (i = 0; i < __arraycount(sc->handle); i++) 347 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 348 pcic_attach_socket(&sc->handle[i]); 349 } 350 351 void 352 pcic_power(why, arg) 353 int why; 354 void *arg; 355 { 356 struct pcic_handle *h = (struct pcic_handle *)arg; 357 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 358 int reg; 359 360 DPRINTF(("%s: power: why %d\n", device_xname(h->ph_parent), why)); 361 362 if (h->flags & PCIC_FLAG_SOCKETP) { 363 if ((why == PWR_RESUME) && 364 (pcic_read(h, PCIC_CSC_INTR) == 0)) { 365 #ifdef PCICDEBUG 366 char bitbuf[64]; 367 #endif 368 reg = PCIC_CSC_INTR_CD_ENABLE; 369 if (sc->irq != -1) 370 reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT; 371 pcic_write(h, PCIC_CSC_INTR, reg); 372 DPRINTF(("%s: CSC_INTR was zero; reset to %s\n", 373 device_xname(&sc->dev), 374 bitmask_snprintf(pcic_read(h, PCIC_CSC_INTR), 375 PCIC_CSC_INTR_FORMAT, 376 bitbuf, sizeof(bitbuf)))); 377 } 378 379 /* 380 * check for card insertion or removal during suspend period. 381 * XXX: the code can't cope with card swap (remove then insert). 382 * how can we detect such situation? 383 */ 384 if (why == PWR_RESUME) 385 (void)pcic_intr_socket(h); 386 } 387 } 388 389 390 /* 391 * attach a socket -- we don't know about irqs yet 392 */ 393 void 394 pcic_attach_socket(h) 395 struct pcic_handle *h; 396 { 397 struct pcmciabus_attach_args paa; 398 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 399 int locs[PCMCIABUSCF_NLOCS]; 400 401 /* initialize the rest of the handle */ 402 403 h->shutdown = 0; 404 h->memalloc = 0; 405 h->ioalloc = 0; 406 h->ih_irq = 0; 407 408 /* now, config one pcmcia device per socket */ 409 410 paa.paa_busname = "pcmcia"; 411 paa.pct = (pcmcia_chipset_tag_t) sc->pct; 412 paa.pch = (pcmcia_chipset_handle_t) h; 413 paa.iobase = sc->iobase; 414 paa.iosize = sc->iosize; 415 416 locs[PCMCIABUSCF_CONTROLLER] = h->chip; 417 locs[PCMCIABUSCF_SOCKET] = h->socket; 418 419 h->pcmcia = config_found_sm_loc(&sc->dev, "pcmciabus", locs, &paa, 420 pcic_print, config_stdsubmatch); 421 if (h->pcmcia == NULL) { 422 h->flags &= ~PCIC_FLAG_SOCKETP; 423 return; 424 } 425 426 } 427 428 /* 429 * now finish attaching the sockets, we are ready to allocate 430 * interrupts 431 */ 432 void 433 pcic_attach_sockets_finish(sc) 434 struct pcic_softc *sc; 435 { 436 int i; 437 438 for (i = 0; i < __arraycount(sc->handle); i++) 439 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 440 pcic_attach_socket_finish(&sc->handle[i]); 441 } 442 443 /* 444 * finishing attaching the socket. Interrupts may now be on 445 * if so expects the pcic interrupt to be blocked 446 */ 447 void 448 pcic_attach_socket_finish(h) 449 struct pcic_handle *h; 450 { 451 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 452 int reg; 453 char cs[4]; 454 455 DPRINTF(("%s: attach finish socket %ld\n", device_xname(h->ph_parent), 456 (long) (h - &sc->handle[0]))); 457 458 /* 459 * Set up a powerhook to ensure it continues to interrupt on 460 * card detect even after suspend. 461 * (this works around a bug seen in suspend-to-disk on the 462 * Sony VAIO Z505; on resume, the CSC_INTR state is not preserved). 463 */ 464 powerhook_establish(device_xname(h->ph_parent), pcic_power, h); 465 466 /* enable interrupts on card detect, poll for them if no irq avail */ 467 reg = PCIC_CSC_INTR_CD_ENABLE; 468 if (sc->irq == -1) { 469 if (sc->poll_established == 0) { 470 callout_init(&sc->poll_ch, 0); 471 callout_reset(&sc->poll_ch, hz / 2, pcic_poll_intr, sc); 472 sc->poll_established = 1; 473 } 474 } else 475 reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT; 476 pcic_write(h, PCIC_CSC_INTR, reg); 477 478 /* steer above mgmt interrupt to configured place */ 479 if (sc->irq == 0) 480 pcic_write(h, PCIC_INTR, PCIC_INTR_ENABLE); 481 482 /* clear possible card detect interrupt */ 483 (void) pcic_read(h, PCIC_CSC); 484 485 DPRINTF(("%s: attach finish vendor 0x%02x\n", device_xname(h->ph_parent), 486 h->vendor)); 487 488 /* unsleep the cirrus controller */ 489 if (h->vendor == PCIC_VENDOR_CIRRUS_PD67XX) { 490 reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2); 491 if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) { 492 DPRINTF(("%s: socket %02x was suspended\n", 493 device_xname(h->ph_parent), h->sock)); 494 reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND; 495 pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg); 496 } 497 } 498 499 /* if there's a card there, then attach it. */ 500 reg = pcic_read(h, PCIC_IF_STATUS); 501 if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) == 502 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 503 pcic_queue_event(h, PCIC_EVENT_INSERTION); 504 h->laststate = PCIC_LASTSTATE_PRESENT; 505 } else { 506 h->laststate = PCIC_LASTSTATE_EMPTY; 507 } 508 509 /* 510 * queue creation of a kernel thread to handle insert/removal events. 511 */ 512 #ifdef DIAGNOSTIC 513 if (h->event_thread != NULL) 514 panic("pcic_attach_socket: event thread"); 515 #endif 516 config_pending_incr(); 517 snprintf(cs, sizeof(cs), "%d,%d", h->chip, h->socket); 518 519 if (kthread_create(PRI_NONE, 0, NULL, pcic_event_thread, h, 520 &h->event_thread, "%s,%s", device_xname(h->ph_parent), cs)) { 521 aprint_error_dev(h->ph_parent, "unable to create event thread for sock 0x%02x\n", h->sock); 522 panic("pcic_attach_socket"); 523 } 524 } 525 526 void 527 pcic_event_thread(arg) 528 void *arg; 529 { 530 struct pcic_handle *h = arg; 531 struct pcic_event *pe; 532 int s, first = 1; 533 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 534 535 while (h->shutdown == 0) { 536 /* 537 * Serialize event processing on the PCIC. We may 538 * sleep while we hold this lock. 539 */ 540 mutex_enter(&sc->sc_pcic_lock); 541 542 s = splhigh(); 543 if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) { 544 splx(s); 545 if (first) { 546 first = 0; 547 config_pending_decr(); 548 } 549 /* 550 * No events to process; release the PCIC lock. 551 */ 552 (void) mutex_exit(&sc->sc_pcic_lock); 553 (void) tsleep(&h->events, PWAIT, "pcicev", 0); 554 continue; 555 } else { 556 splx(s); 557 /* sleep .25s to be enqueued chatterling interrupts */ 558 (void) tsleep((void *)pcic_event_thread, PWAIT, 559 "pcicss", hz/4); 560 } 561 s = splhigh(); 562 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 563 splx(s); 564 565 switch (pe->pe_type) { 566 case PCIC_EVENT_INSERTION: 567 s = splhigh(); 568 while (1) { 569 struct pcic_event *pe1, *pe2; 570 571 if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL) 572 break; 573 if (pe1->pe_type != PCIC_EVENT_REMOVAL) 574 break; 575 if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL) 576 break; 577 if (pe2->pe_type == PCIC_EVENT_INSERTION) { 578 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 579 free(pe1, M_TEMP); 580 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 581 free(pe2, M_TEMP); 582 } 583 } 584 splx(s); 585 586 DPRINTF(("%s: insertion event\n", 587 device_xname(h->ph_parent))); 588 pcic_attach_card(h); 589 break; 590 591 case PCIC_EVENT_REMOVAL: 592 s = splhigh(); 593 while (1) { 594 struct pcic_event *pe1, *pe2; 595 596 if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL) 597 break; 598 if (pe1->pe_type != PCIC_EVENT_INSERTION) 599 break; 600 if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL) 601 break; 602 if (pe2->pe_type == PCIC_EVENT_REMOVAL) { 603 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 604 free(pe1, M_TEMP); 605 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 606 free(pe2, M_TEMP); 607 } 608 } 609 splx(s); 610 611 DPRINTF(("%s: removal event\n", 612 device_xname(h->ph_parent))); 613 pcic_detach_card(h, DETACH_FORCE); 614 break; 615 616 default: 617 panic("pcic_event_thread: unknown event %d", 618 pe->pe_type); 619 } 620 free(pe, M_TEMP); 621 622 mutex_exit(&sc->sc_pcic_lock); 623 } 624 625 h->event_thread = NULL; 626 627 /* In case parent is waiting for us to exit. */ 628 wakeup(sc); 629 630 kthread_exit(0); 631 } 632 633 int 634 pcic_print(arg, pnp) 635 void *arg; 636 const char *pnp; 637 { 638 struct pcmciabus_attach_args *paa = arg; 639 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 640 641 /* Only "pcmcia"s can attach to "pcic"s... easy. */ 642 if (pnp) 643 aprint_normal("pcmcia at %s", pnp); 644 645 aprint_normal(" controller %d socket %d", h->chip, h->socket); 646 647 return (UNCONF); 648 } 649 650 void 651 pcic_poll_intr(arg) 652 void *arg; 653 { 654 struct pcic_softc *sc; 655 int i, s; 656 657 s = spltty(); 658 sc = arg; 659 for (i = 0; i < __arraycount(sc->handle); i++) 660 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 661 (void)pcic_intr_socket(&sc->handle[i]); 662 callout_reset(&sc->poll_ch, hz / 2, pcic_poll_intr, sc); 663 splx(s); 664 } 665 666 int 667 pcic_intr(arg) 668 void *arg; 669 { 670 struct pcic_softc *sc = arg; 671 int i, ret = 0; 672 673 DPRINTF(("%s: intr\n", device_xname(&sc->dev))); 674 675 for (i = 0; i < __arraycount(sc->handle); i++) 676 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 677 ret += pcic_intr_socket(&sc->handle[i]); 678 679 return (ret ? 1 : 0); 680 } 681 682 int 683 pcic_intr_socket(h) 684 struct pcic_handle *h; 685 { 686 int cscreg; 687 688 cscreg = pcic_read(h, PCIC_CSC); 689 690 cscreg &= (PCIC_CSC_GPI | 691 PCIC_CSC_CD | 692 PCIC_CSC_READY | 693 PCIC_CSC_BATTWARN | 694 PCIC_CSC_BATTDEAD); 695 696 if (cscreg & PCIC_CSC_GPI) { 697 DPRINTF(("%s: %02x GPI\n", device_xname(h->ph_parent), h->sock)); 698 } 699 if (cscreg & PCIC_CSC_CD) { 700 int statreg; 701 702 statreg = pcic_read(h, PCIC_IF_STATUS); 703 704 DPRINTF(("%s: %02x CD %x\n", device_xname(h->ph_parent), h->sock, 705 statreg)); 706 707 if ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 708 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 709 if (h->laststate != PCIC_LASTSTATE_PRESENT) { 710 DPRINTF(("%s: enqueing INSERTION event\n", 711 device_xname(h->ph_parent))); 712 pcic_queue_event(h, PCIC_EVENT_INSERTION); 713 } 714 h->laststate = PCIC_LASTSTATE_PRESENT; 715 } else { 716 if (h->laststate == PCIC_LASTSTATE_PRESENT) { 717 /* Deactivate the card now. */ 718 DPRINTF(("%s: deactivating card\n", 719 device_xname(h->ph_parent))); 720 pcic_deactivate_card(h); 721 722 DPRINTF(("%s: enqueing REMOVAL event\n", 723 device_xname(h->ph_parent))); 724 pcic_queue_event(h, PCIC_EVENT_REMOVAL); 725 } 726 h->laststate = PCIC_LASTSTATE_EMPTY; 727 } 728 } 729 if (cscreg & PCIC_CSC_READY) { 730 DPRINTF(("%s: %02x READY\n", device_xname(h->ph_parent), h->sock)); 731 /* shouldn't happen */ 732 } 733 if (cscreg & PCIC_CSC_BATTWARN) { 734 DPRINTF(("%s: %02x BATTWARN\n", device_xname(h->ph_parent), 735 h->sock)); 736 } 737 if (cscreg & PCIC_CSC_BATTDEAD) { 738 DPRINTF(("%s: %02x BATTDEAD\n", device_xname(h->ph_parent), 739 h->sock)); 740 } 741 return (cscreg ? 1 : 0); 742 } 743 744 void 745 pcic_queue_event(h, event) 746 struct pcic_handle *h; 747 int event; 748 { 749 struct pcic_event *pe; 750 int s; 751 752 pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT); 753 if (pe == NULL) 754 panic("pcic_queue_event: can't allocate event"); 755 756 pe->pe_type = event; 757 s = splhigh(); 758 SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q); 759 splx(s); 760 wakeup(&h->events); 761 } 762 763 void 764 pcic_attach_card(h) 765 struct pcic_handle *h; 766 { 767 768 if (!(h->flags & PCIC_FLAG_CARDP)) { 769 /* call the MI attach function */ 770 pcmcia_card_attach(h->pcmcia); 771 772 h->flags |= PCIC_FLAG_CARDP; 773 } else { 774 DPRINTF(("pcic_attach_card: already attached")); 775 } 776 } 777 778 void 779 pcic_detach_card(h, flags) 780 struct pcic_handle *h; 781 int flags; /* DETACH_* */ 782 { 783 784 if (h->flags & PCIC_FLAG_CARDP) { 785 h->flags &= ~PCIC_FLAG_CARDP; 786 787 /* call the MI detach function */ 788 pcmcia_card_detach(h->pcmcia, flags); 789 } else { 790 DPRINTF(("pcic_detach_card: already detached")); 791 } 792 } 793 794 void 795 pcic_deactivate_card(h) 796 struct pcic_handle *h; 797 { 798 int intr; 799 800 /* call the MI deactivate function */ 801 pcmcia_card_deactivate(h->pcmcia); 802 803 /* reset the socket */ 804 intr = pcic_read(h, PCIC_INTR); 805 intr &= PCIC_INTR_ENABLE; 806 pcic_write(h, PCIC_INTR, intr); 807 808 /* power down the socket */ 809 pcic_write(h, PCIC_PWRCTL, 0); 810 } 811 812 int 813 pcic_chip_mem_alloc(pch, size, pcmhp) 814 pcmcia_chipset_handle_t pch; 815 bus_size_t size; 816 struct pcmcia_mem_handle *pcmhp; 817 { 818 struct pcic_handle *h = (struct pcic_handle *) pch; 819 bus_space_handle_t memh; 820 bus_addr_t addr; 821 bus_size_t sizepg; 822 int i, mask, mhandle; 823 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 824 825 /* out of sc->memh, allocate as many pages as necessary */ 826 827 /* convert size to PCIC pages */ 828 sizepg = (size + (PCIC_MEM_ALIGN - 1)) / PCIC_MEM_ALIGN; 829 if (sizepg > PCIC_MAX_MEM_PAGES) 830 return (1); 831 832 mask = (1 << sizepg) - 1; 833 834 addr = 0; /* XXX gcc -Wuninitialized */ 835 mhandle = 0; /* XXX gcc -Wuninitialized */ 836 837 for (i = 0; i <= PCIC_MAX_MEM_PAGES - sizepg; i++) { 838 if ((sc->subregionmask & (mask << i)) == (mask << i)) { 839 if (bus_space_subregion(sc->memt, sc->memh, 840 i * PCIC_MEM_PAGESIZE, 841 sizepg * PCIC_MEM_PAGESIZE, &memh)) 842 return (1); 843 mhandle = mask << i; 844 addr = sc->membase + (i * PCIC_MEM_PAGESIZE); 845 sc->subregionmask &= ~(mhandle); 846 pcmhp->memt = sc->memt; 847 pcmhp->memh = memh; 848 pcmhp->addr = addr; 849 pcmhp->size = size; 850 pcmhp->mhandle = mhandle; 851 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 852 return (0); 853 } 854 } 855 856 return (1); 857 } 858 859 void 860 pcic_chip_mem_free(pch, pcmhp) 861 pcmcia_chipset_handle_t pch; 862 struct pcmcia_mem_handle *pcmhp; 863 { 864 struct pcic_handle *h = (struct pcic_handle *) pch; 865 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 866 867 sc->subregionmask |= pcmhp->mhandle; 868 } 869 870 static const struct mem_map_index_st { 871 int sysmem_start_lsb; 872 int sysmem_start_msb; 873 int sysmem_stop_lsb; 874 int sysmem_stop_msb; 875 int cardmem_lsb; 876 int cardmem_msb; 877 int memenable; 878 } mem_map_index[] = { 879 { 880 PCIC_SYSMEM_ADDR0_START_LSB, 881 PCIC_SYSMEM_ADDR0_START_MSB, 882 PCIC_SYSMEM_ADDR0_STOP_LSB, 883 PCIC_SYSMEM_ADDR0_STOP_MSB, 884 PCIC_CARDMEM_ADDR0_LSB, 885 PCIC_CARDMEM_ADDR0_MSB, 886 PCIC_ADDRWIN_ENABLE_MEM0, 887 }, 888 { 889 PCIC_SYSMEM_ADDR1_START_LSB, 890 PCIC_SYSMEM_ADDR1_START_MSB, 891 PCIC_SYSMEM_ADDR1_STOP_LSB, 892 PCIC_SYSMEM_ADDR1_STOP_MSB, 893 PCIC_CARDMEM_ADDR1_LSB, 894 PCIC_CARDMEM_ADDR1_MSB, 895 PCIC_ADDRWIN_ENABLE_MEM1, 896 }, 897 { 898 PCIC_SYSMEM_ADDR2_START_LSB, 899 PCIC_SYSMEM_ADDR2_START_MSB, 900 PCIC_SYSMEM_ADDR2_STOP_LSB, 901 PCIC_SYSMEM_ADDR2_STOP_MSB, 902 PCIC_CARDMEM_ADDR2_LSB, 903 PCIC_CARDMEM_ADDR2_MSB, 904 PCIC_ADDRWIN_ENABLE_MEM2, 905 }, 906 { 907 PCIC_SYSMEM_ADDR3_START_LSB, 908 PCIC_SYSMEM_ADDR3_START_MSB, 909 PCIC_SYSMEM_ADDR3_STOP_LSB, 910 PCIC_SYSMEM_ADDR3_STOP_MSB, 911 PCIC_CARDMEM_ADDR3_LSB, 912 PCIC_CARDMEM_ADDR3_MSB, 913 PCIC_ADDRWIN_ENABLE_MEM3, 914 }, 915 { 916 PCIC_SYSMEM_ADDR4_START_LSB, 917 PCIC_SYSMEM_ADDR4_START_MSB, 918 PCIC_SYSMEM_ADDR4_STOP_LSB, 919 PCIC_SYSMEM_ADDR4_STOP_MSB, 920 PCIC_CARDMEM_ADDR4_LSB, 921 PCIC_CARDMEM_ADDR4_MSB, 922 PCIC_ADDRWIN_ENABLE_MEM4, 923 }, 924 }; 925 926 void 927 pcic_chip_do_mem_map(h, win) 928 struct pcic_handle *h; 929 int win; 930 { 931 int reg; 932 int kind = h->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 933 int mem8 = 934 (h->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 935 || (kind == PCMCIA_MEM_ATTR); 936 937 DPRINTF(("mem8 %d\n", mem8)); 938 /* mem8 = 1; */ 939 940 pcic_write(h, mem_map_index[win].sysmem_start_lsb, 941 (h->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 942 pcic_write(h, mem_map_index[win].sysmem_start_msb, 943 ((h->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 944 PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK) | 945 (mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT)); 946 947 pcic_write(h, mem_map_index[win].sysmem_stop_lsb, 948 ((h->mem[win].addr + h->mem[win].size) >> 949 PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 950 pcic_write(h, mem_map_index[win].sysmem_stop_msb, 951 (((h->mem[win].addr + h->mem[win].size) >> 952 (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 953 PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) | 954 PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2); 955 956 pcic_write(h, mem_map_index[win].cardmem_lsb, 957 (h->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff); 958 pcic_write(h, mem_map_index[win].cardmem_msb, 959 ((h->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) & 960 PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) | 961 ((kind == PCMCIA_MEM_ATTR) ? 962 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0)); 963 964 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 965 reg |= (mem_map_index[win].memenable | PCIC_ADDRWIN_ENABLE_MEMCS16); 966 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 967 968 delay(100); 969 970 #ifdef PCICDEBUG 971 { 972 int r1, r2, r3, r4, r5, r6; 973 974 r1 = pcic_read(h, mem_map_index[win].sysmem_start_msb); 975 r2 = pcic_read(h, mem_map_index[win].sysmem_start_lsb); 976 r3 = pcic_read(h, mem_map_index[win].sysmem_stop_msb); 977 r4 = pcic_read(h, mem_map_index[win].sysmem_stop_lsb); 978 r5 = pcic_read(h, mem_map_index[win].cardmem_msb); 979 r6 = pcic_read(h, mem_map_index[win].cardmem_lsb); 980 981 DPRINTF(("pcic_chip_do_mem_map window %d: %02x%02x %02x%02x " 982 "%02x%02x\n", win, r1, r2, r3, r4, r5, r6)); 983 } 984 #endif 985 } 986 987 int 988 pcic_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 989 pcmcia_chipset_handle_t pch; 990 int kind; 991 bus_addr_t card_addr; 992 bus_size_t size; 993 struct pcmcia_mem_handle *pcmhp; 994 bus_size_t *offsetp; 995 int *windowp; 996 { 997 struct pcic_handle *h = (struct pcic_handle *) pch; 998 bus_addr_t busaddr; 999 long card_offset; 1000 int i, win; 1001 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 1002 1003 win = -1; 1004 for (i = 0; i < (sizeof(mem_map_index) / sizeof(mem_map_index[0])); 1005 i++) { 1006 if ((h->memalloc & (1 << i)) == 0) { 1007 win = i; 1008 h->memalloc |= (1 << i); 1009 break; 1010 } 1011 } 1012 1013 if (win == -1) 1014 return (1); 1015 1016 *windowp = win; 1017 1018 /* XXX this is pretty gross */ 1019 1020 if (sc->memt != pcmhp->memt) 1021 panic("pcic_chip_mem_map memt is bogus"); 1022 1023 busaddr = pcmhp->addr; 1024 1025 /* 1026 * compute the address offset to the pcmcia address space for the 1027 * pcic. this is intentionally signed. The masks and shifts below 1028 * will cause TRT to happen in the pcic registers. Deal with making 1029 * sure the address is aligned, and return the alignment offset. 1030 */ 1031 1032 *offsetp = card_addr % PCIC_MEM_ALIGN; 1033 card_addr -= *offsetp; 1034 1035 DPRINTF(("pcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 1036 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 1037 (u_long) card_addr)); 1038 1039 /* 1040 * include the offset in the size, and decrement size by one, since 1041 * the hw wants start/stop 1042 */ 1043 size += *offsetp - 1; 1044 1045 card_offset = (((long) card_addr) - ((long) busaddr)); 1046 1047 h->mem[win].addr = busaddr; 1048 h->mem[win].size = size; 1049 h->mem[win].offset = card_offset; 1050 h->mem[win].kind = kind; 1051 1052 pcic_chip_do_mem_map(h, win); 1053 1054 return (0); 1055 } 1056 1057 void 1058 pcic_chip_mem_unmap(pch, window) 1059 pcmcia_chipset_handle_t pch; 1060 int window; 1061 { 1062 struct pcic_handle *h = (struct pcic_handle *) pch; 1063 int reg; 1064 1065 if (window >= (sizeof(mem_map_index) / sizeof(mem_map_index[0]))) 1066 panic("pcic_chip_mem_unmap: window out of range"); 1067 1068 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1069 reg &= ~mem_map_index[window].memenable; 1070 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1071 1072 h->memalloc &= ~(1 << window); 1073 } 1074 1075 int 1076 pcic_chip_io_alloc(pch, start, size, align, pcihp) 1077 pcmcia_chipset_handle_t pch; 1078 bus_addr_t start; 1079 bus_size_t size; 1080 bus_size_t align; 1081 struct pcmcia_io_handle *pcihp; 1082 { 1083 struct pcic_handle *h = (struct pcic_handle *) pch; 1084 bus_space_tag_t iot; 1085 bus_space_handle_t ioh; 1086 bus_addr_t ioaddr; 1087 int flags = 0; 1088 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 1089 1090 /* 1091 * Allocate some arbitrary I/O space. 1092 */ 1093 1094 iot = sc->iot; 1095 1096 if (start) { 1097 ioaddr = start; 1098 if (bus_space_map(iot, start, size, 0, &ioh)) 1099 return (1); 1100 DPRINTF(("pcic_chip_io_alloc map port %lx+%lx\n", 1101 (u_long) ioaddr, (u_long) size)); 1102 } else { 1103 flags |= PCMCIA_IO_ALLOCATED; 1104 if (bus_space_alloc(iot, sc->iobase, 1105 sc->iobase + sc->iosize, size, align, 0, 0, 1106 &ioaddr, &ioh)) 1107 return (1); 1108 DPRINTF(("pcic_chip_io_alloc alloc port %lx+%lx\n", 1109 (u_long) ioaddr, (u_long) size)); 1110 } 1111 1112 pcihp->iot = iot; 1113 pcihp->ioh = ioh; 1114 pcihp->addr = ioaddr; 1115 pcihp->size = size; 1116 pcihp->flags = flags; 1117 1118 return (0); 1119 } 1120 1121 void 1122 pcic_chip_io_free(pcmcia_chipset_handle_t pch, 1123 struct pcmcia_io_handle *pcihp) 1124 { 1125 bus_space_tag_t iot = pcihp->iot; 1126 bus_space_handle_t ioh = pcihp->ioh; 1127 bus_size_t size = pcihp->size; 1128 1129 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1130 bus_space_free(iot, ioh, size); 1131 else 1132 bus_space_unmap(iot, ioh, size); 1133 } 1134 1135 1136 static const struct io_map_index_st { 1137 int start_lsb; 1138 int start_msb; 1139 int stop_lsb; 1140 int stop_msb; 1141 int ioenable; 1142 int ioctlmask; 1143 int ioctlbits[3]; /* indexed by PCMCIA_WIDTH_* */ 1144 } io_map_index[] = { 1145 { 1146 PCIC_IOADDR0_START_LSB, 1147 PCIC_IOADDR0_START_MSB, 1148 PCIC_IOADDR0_STOP_LSB, 1149 PCIC_IOADDR0_STOP_MSB, 1150 PCIC_ADDRWIN_ENABLE_IO0, 1151 PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1152 PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK, 1153 { 1154 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1155 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1156 PCIC_IOCTL_IO0_DATASIZE_8BIT, 1157 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1158 PCIC_IOCTL_IO0_DATASIZE_16BIT, 1159 }, 1160 }, 1161 { 1162 PCIC_IOADDR1_START_LSB, 1163 PCIC_IOADDR1_START_MSB, 1164 PCIC_IOADDR1_STOP_LSB, 1165 PCIC_IOADDR1_STOP_MSB, 1166 PCIC_ADDRWIN_ENABLE_IO1, 1167 PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1168 PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK, 1169 { 1170 PCIC_IOCTL_IO1_IOCS16SRC_CARD, 1171 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1172 PCIC_IOCTL_IO1_DATASIZE_8BIT, 1173 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1174 PCIC_IOCTL_IO1_DATASIZE_16BIT, 1175 }, 1176 }, 1177 }; 1178 1179 void 1180 pcic_chip_do_io_map(h, win) 1181 struct pcic_handle *h; 1182 int win; 1183 { 1184 int reg; 1185 1186 DPRINTF(("pcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 1187 win, (long) h->io[win].addr, (long) h->io[win].size, 1188 h->io[win].width * 8)); 1189 1190 pcic_write(h, io_map_index[win].start_lsb, h->io[win].addr & 0xff); 1191 pcic_write(h, io_map_index[win].start_msb, 1192 (h->io[win].addr >> 8) & 0xff); 1193 1194 pcic_write(h, io_map_index[win].stop_lsb, 1195 (h->io[win].addr + h->io[win].size - 1) & 0xff); 1196 pcic_write(h, io_map_index[win].stop_msb, 1197 ((h->io[win].addr + h->io[win].size - 1) >> 8) & 0xff); 1198 1199 reg = pcic_read(h, PCIC_IOCTL); 1200 reg &= ~io_map_index[win].ioctlmask; 1201 reg |= io_map_index[win].ioctlbits[h->io[win].width]; 1202 pcic_write(h, PCIC_IOCTL, reg); 1203 1204 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1205 reg |= io_map_index[win].ioenable; 1206 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1207 } 1208 1209 int 1210 pcic_chip_io_map(pch, width, offset, size, pcihp, windowp) 1211 pcmcia_chipset_handle_t pch; 1212 int width; 1213 bus_addr_t offset; 1214 bus_size_t size; 1215 struct pcmcia_io_handle *pcihp; 1216 int *windowp; 1217 { 1218 struct pcic_handle *h = (struct pcic_handle *) pch; 1219 bus_addr_t ioaddr = pcihp->addr + offset; 1220 int i, win; 1221 #ifdef PCICDEBUG 1222 static const char *width_names[] = { "auto", "io8", "io16" }; 1223 #endif 1224 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 1225 1226 /* XXX Sanity check offset/size. */ 1227 1228 win = -1; 1229 for (i = 0; i < (sizeof(io_map_index) / sizeof(io_map_index[0])); i++) { 1230 if ((h->ioalloc & (1 << i)) == 0) { 1231 win = i; 1232 h->ioalloc |= (1 << i); 1233 break; 1234 } 1235 } 1236 1237 if (win == -1) 1238 return (1); 1239 1240 *windowp = win; 1241 1242 /* XXX this is pretty gross */ 1243 1244 if (sc->iot != pcihp->iot) 1245 panic("pcic_chip_io_map iot is bogus"); 1246 1247 DPRINTF(("pcic_chip_io_map window %d %s port %lx+%lx\n", 1248 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1249 1250 /* XXX wtf is this doing here? */ 1251 1252 printf("%s: port 0x%lx", device_xname(&sc->dev), (u_long) ioaddr); 1253 if (size > 1) 1254 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1255 printf("\n"); 1256 1257 h->io[win].addr = ioaddr; 1258 h->io[win].size = size; 1259 h->io[win].width = width; 1260 1261 pcic_chip_do_io_map(h, win); 1262 1263 return (0); 1264 } 1265 1266 void 1267 pcic_chip_io_unmap(pch, window) 1268 pcmcia_chipset_handle_t pch; 1269 int window; 1270 { 1271 struct pcic_handle *h = (struct pcic_handle *) pch; 1272 int reg; 1273 1274 if (window >= (sizeof(io_map_index) / sizeof(io_map_index[0]))) 1275 panic("pcic_chip_io_unmap: window out of range"); 1276 1277 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1278 reg &= ~io_map_index[window].ioenable; 1279 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1280 1281 h->ioalloc &= ~(1 << window); 1282 } 1283 1284 static int 1285 pcic_wait_ready(h) 1286 struct pcic_handle *h; 1287 { 1288 u_int8_t stat; 1289 int i; 1290 1291 /* wait an initial 10ms for quick cards */ 1292 stat = pcic_read(h, PCIC_IF_STATUS); 1293 if (stat & PCIC_IF_STATUS_READY) 1294 return (0); 1295 pcic_delay(h, 10, "pccwr0"); 1296 for (i = 0; i < 50; i++) { 1297 stat = pcic_read(h, PCIC_IF_STATUS); 1298 if (stat & PCIC_IF_STATUS_READY) 1299 return (0); 1300 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 1301 PCIC_IF_STATUS_CARDDETECT_PRESENT) 1302 return (ENXIO); 1303 /* wait .1s (100ms) each iteration now */ 1304 pcic_delay(h, 100, "pccwr1"); 1305 } 1306 1307 printf("pcic_wait_ready: ready never happened, status=%02x\n", stat); 1308 return (EWOULDBLOCK); 1309 } 1310 1311 /* 1312 * Perform long (msec order) delay. 1313 */ 1314 static void 1315 pcic_delay(h, timo, wmesg) 1316 struct pcic_handle *h; 1317 int timo; /* in ms. must not be zero */ 1318 const char *wmesg; 1319 { 1320 1321 #ifdef DIAGNOSTIC 1322 if (timo <= 0) 1323 panic("pcic_delay: called with timeout %d", timo); 1324 if (!curlwp) 1325 panic("pcic_delay: called in interrupt context"); 1326 if (!h->event_thread) 1327 panic("pcic_delay: no event thread"); 1328 #endif 1329 DPRINTF(("pcic_delay: \"%s\" %p, sleep %d ms\n", 1330 wmesg, h->event_thread, timo)); 1331 tsleep(pcic_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 1332 } 1333 1334 void 1335 pcic_chip_socket_enable(pch) 1336 pcmcia_chipset_handle_t pch; 1337 { 1338 struct pcic_handle *h = (struct pcic_handle *) pch; 1339 int win; 1340 u_int8_t power, intr; 1341 #ifdef DIAGNOSTIC 1342 int reg; 1343 #endif 1344 1345 #ifdef DIAGNOSTIC 1346 if (h->flags & PCIC_FLAG_ENABLED) 1347 printf("pcic_chip_socket_enable: enabling twice\n"); 1348 #endif 1349 1350 /* disable interrupts; assert RESET */ 1351 intr = pcic_read(h, PCIC_INTR); 1352 intr &= PCIC_INTR_ENABLE; 1353 pcic_write(h, PCIC_INTR, intr); 1354 1355 /* zero out the address windows */ 1356 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1357 1358 /* power off; assert output enable bit */ 1359 power = PCIC_PWRCTL_OE; 1360 pcic_write(h, PCIC_PWRCTL, power); 1361 1362 /* 1363 * power hack for RICOH RF5C[23]96 1364 */ 1365 switch( h->vendor ) { 1366 case PCIC_VENDOR_RICOH_5C296: 1367 case PCIC_VENDOR_RICOH_5C396: 1368 { 1369 int regtmp; 1370 regtmp = pcic_read(h, PCIC_RICOH_REG_MCR2); 1371 #ifdef RICOH_POWER_HACK 1372 regtmp |= PCIC_RICOH_MCR2_VCC_DIRECT; 1373 #else 1374 regtmp &= ~(PCIC_RICOH_MCR2_VCC_DIRECT|PCIC_RICOH_MCR2_VCC_SEL_3V); 1375 #endif 1376 pcic_write(h, PCIC_RICOH_REG_MCR2, regtmp); 1377 } 1378 break; 1379 default: 1380 break; 1381 } 1382 1383 #ifdef VADEM_POWER_HACK 1384 bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x0e); 1385 bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x37); 1386 printf("prcr = %02x\n", pcic_read(h, 0x02)); 1387 printf("cvsr = %02x\n", pcic_read(h, 0x2f)); 1388 printf("DANGER WILL ROBINSON! Changing voltage select!\n"); 1389 pcic_write(h, 0x2f, pcic_read(h, 0x2f) & ~0x03); 1390 printf("cvsr = %02x\n", pcic_read(h, 0x2f)); 1391 #endif 1392 1393 /* power up the socket */ 1394 power |= PCIC_PWRCTL_PWR_ENABLE | PCIC_PWRCTL_VPP1_VCC; 1395 pcic_write(h, PCIC_PWRCTL, power); 1396 1397 /* 1398 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 1399 * Vcc Rising Time (Tpr) = 100ms 1400 * RESET Width (Th (Hi-z RESET)) = 1ms 1401 * RESET Width (Tw (RESET)) = 10us 1402 * 1403 * some machines require some more time to be settled 1404 * (100ms is added here). 1405 */ 1406 pcic_delay(h, 200 + 1, "pccen1"); 1407 1408 /* negate RESET */ 1409 intr |= PCIC_INTR_RESET; 1410 pcic_write(h, PCIC_INTR, intr); 1411 1412 /* 1413 * RESET Setup Time (Tsu (RESET)) = 20ms 1414 */ 1415 pcic_delay(h, 20, "pccen2"); 1416 1417 #ifdef DIAGNOSTIC 1418 reg = pcic_read(h, PCIC_IF_STATUS); 1419 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 1420 printf("pcic_chip_socket_enable: no power, status=%x\n", reg); 1421 #endif 1422 1423 /* wait for the chip to finish initializing */ 1424 if (pcic_wait_ready(h)) { 1425 /* XXX return a failure status?? */ 1426 pcic_write(h, PCIC_PWRCTL, 0); 1427 return; 1428 } 1429 1430 /* reinstall all the memory and io mappings */ 1431 for (win = 0; win < PCIC_MEM_WINS; win++) 1432 if (h->memalloc & (1 << win)) 1433 pcic_chip_do_mem_map(h, win); 1434 for (win = 0; win < PCIC_IO_WINS; win++) 1435 if (h->ioalloc & (1 << win)) 1436 pcic_chip_do_io_map(h, win); 1437 1438 h->flags |= PCIC_FLAG_ENABLED; 1439 } 1440 1441 void 1442 pcic_chip_socket_disable(pch) 1443 pcmcia_chipset_handle_t pch; 1444 { 1445 struct pcic_handle *h = (struct pcic_handle *) pch; 1446 u_int8_t intr; 1447 1448 DPRINTF(("pcic_chip_socket_disable\n")); 1449 1450 /* disable interrupts; assert RESET */ 1451 intr = pcic_read(h, PCIC_INTR); 1452 intr &= PCIC_INTR_ENABLE; 1453 pcic_write(h, PCIC_INTR, intr); 1454 1455 /* zero out the address windows */ 1456 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1457 1458 /* disable socket: negate output enable bit and power off */ 1459 pcic_write(h, PCIC_PWRCTL, 0); 1460 1461 /* 1462 * Vcc Falling Time (Tpf) = 300ms 1463 */ 1464 pcic_delay(h, 300, "pccwr1"); 1465 1466 h->flags &= ~PCIC_FLAG_ENABLED; 1467 } 1468 1469 void 1470 pcic_chip_socket_settype(pch, type) 1471 pcmcia_chipset_handle_t pch; 1472 int type; 1473 { 1474 struct pcic_handle *h = (struct pcic_handle *) pch; 1475 int intr; 1476 1477 intr = pcic_read(h, PCIC_INTR); 1478 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 1479 if (type == PCMCIA_IFTYPE_IO) { 1480 intr |= PCIC_INTR_CARDTYPE_IO; 1481 intr |= h->ih_irq << PCIC_INTR_IRQ_SHIFT; 1482 } else 1483 intr |= PCIC_INTR_CARDTYPE_MEM; 1484 pcic_write(h, PCIC_INTR, intr); 1485 1486 DPRINTF(("%s: pcic_chip_socket_settype %02x type %s %02x\n", 1487 device_xname(h->ph_parent), h->sock, 1488 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 1489 } 1490 1491 static u_int8_t 1492 st_pcic_read(h, idx) 1493 struct pcic_handle *h; 1494 int idx; 1495 { 1496 1497 if (idx != -1) 1498 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX, 1499 h->sock + idx); 1500 return (bus_space_read_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA)); 1501 } 1502 1503 static void 1504 st_pcic_write(h, idx, data) 1505 struct pcic_handle *h; 1506 int idx; 1507 u_int8_t data; 1508 { 1509 1510 if (idx != -1) 1511 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX, 1512 h->sock + idx); 1513 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA, data); 1514 }
Cache object: ab6620d00f33e1dd0282b62a18a6a842
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