FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/i8251.h
1 /*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 4. Neither the name of the University nor the names of its contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * $FreeBSD: releng/5.4/sys/dev/ic/i8251.h 128019 2004-04-07 20:46:16Z imp $
30 */
31
32 /*
33 * modified for PC9801 by M.Ishii
34 * Kyoto University Microcomputer Club (KMC)
35 */
36
37 /*
38 * modified for 8251(FIFO) by Seigo TANIMURA <tanimura@FreeBSD.org>
39 */
40
41 /* define command and status code */
42 #define CMD8251_TxEN 0x01 /* transmit enable */
43 #define CMD8251_DTR 0x02 /* assert DTR */
44 #define CMD8251_RxEN 0x04 /* receive enable */
45 #define CMD8251_SBRK 0x08 /* send break */
46 #define CMD8251_ER 0x10 /* error reset */
47 #define CMD8251_RTS 0x20 /* assert RTS */
48 #define CMD8251_RESET 0x40 /* internal reset */
49 #define CMD8251_EH 0x80 /* enter hunt mode (only synchronous mode)*/
50
51 #define STS8251_TxRDY 0x01 /* transmit READY */
52 #define STS8251_RxRDY 0x02 /* data exists in receive buffer */
53 #define STS8251_TxEMP 0x04 /* transmit buffer EMPTY */
54 #define STS8251_PE 0x08 /* perity error */
55 #define STS8251_OE 0x10 /* overrun error */
56 #define STS8251_FE 0x20 /* framing error */
57 #define STS8251_BD_SD 0x40 /* break detect (async) / sync detect (sync) */
58 #define STS8251_DSR 0x80 /* DSR is asserted */
59
60 #define STS8251F_TxEMP 0x01 /* transmit buffer EMPTY */
61 #define STS8251F_TxRDY 0x02 /* transmit READY */
62 #define STS8251F_RxRDY 0x04 /* data exists in receive buffer */
63 #define STS8251F_OE 0x10 /* overrun error */
64 #define STS8251F_PE 0x20 /* perity error */
65 #define STS8251F_BD_SD 0x80 /* break detect (async) / sync detect (sync) */
66
67 #define INTR8251F_DTCT 0x60 /* FIFO detection mask */
68 #define INTR8251F_INTRV 0x0e /* interrupt event */
69 #define INTR8251F_TO 0x0c /* receive timeout */
70 #define INTR8251F_LSTS 0x06 /* line status */
71 #define INTR8251F_RxRDY 0x04 /* receive READY */
72 #define INTR8251F_TxRDY 0x02 /* transmit READY */
73 #define INTR8251F_ISEV 0x01 /* event occured */
74 #define INTR8251F_MSTS 0x00 /* modem status */
75
76 #define CTRL8251F_ENABLE 0x01 /* enable FIFO */
77 #define CTRL8251F_RCV_RST 0x02 /* reset receive FIFO */
78 #define CTRL8251F_XMT_RST 0x04 /* reset transmit FIFO */
79
80 #define MOD8251_5BITS 0x00
81 #define MOD8251_6BITS 0x04
82 #define MOD8251_7BITS 0x08
83 #define MOD8251_8BITS 0x0c
84 #define MOD8251_PDISAB 0x00 /* parity disable */
85 #define MOD8251_PODD 0x10 /* parity odd */
86 #define MOD8251_PEVEN 0x30 /* parity even */
87 #define MOD8251_STOP1 0x40 /* stop bit len = 1bit */
88 #define MOD8251_STOP2 0xc0 /* stop bit len = 2bit */
89 #define MOD8251_CLKX16 0x02 /* x16 */
90 #define MOD8251_CLKX1 0x01 /* x1 */
91
92 #define CICSCD_CD 0x20 /* CD */
93 #define CICSCD_CS 0x40 /* CS */
94 #define CICSCD_CI 0x80 /* CI */
95
96 #define CICSCDF_CS 0x10 /* CS */
97 #define CICSCDF_DR 0x20 /* DR */
98 #define CICSCDF_CI 0x40 /* CI */
99 #define CICSCDF_CD 0x80 /* CD */
100
101 /* interrupt mask control */
102 #define IEN_Rx 0x01
103 #define IEN_TxEMP 0x02
104 #define IEN_Tx 0x04
Cache object: 6b56239ec58338dc28ee66b2da761b63
|