The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/i8251.h

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    1 /*-
    2  * Copyright (c) 1991 The Regents of the University of California.
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 4. Neither the name of the University nor the names of its contributors
   14  *    may be used to endorse or promote products derived from this software
   15  *    without specific prior written permission.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  *
   29  * $FreeBSD: releng/9.0/sys/dev/ic/i8251.h 182835 2008-09-07 04:35:04Z nyan $
   30  */
   31 
   32 /*
   33  * modified for PC9801 by M.Ishii 
   34  *                      Kyoto University Microcomputer Club (KMC)
   35  *
   36  * modified for 8251(FIFO) by Seigo TANIMURA <tanimura@FreeBSD.org>
   37  */
   38 
   39 /* i8251 mode register */
   40 #define MOD8251_5BITS   0x00
   41 #define MOD8251_6BITS   0x04
   42 #define MOD8251_7BITS   0x08
   43 #define MOD8251_8BITS   0x0c
   44 #define MOD8251_PENAB   0x10    /* parity enable */
   45 #define MOD8251_PEVEN   0x20    /* parity even */
   46 #define MOD8251_STOP1   0x40    /* 1 stop bit */
   47 #define MOD8251_STOP15  0x80    /* 1.5 stop bit */
   48 #define MOD8251_STOP2   0xc0    /* 2 stop bit */
   49 #define MOD8251_CLKx1   0x01    /* x1 */
   50 #define MOD8251_CLKx16  0x02    /* x16 */
   51 #define MOD8251_CLKx64  0x03    /* x64 */
   52 
   53 /* i8251 command register */
   54 #define CMD8251_TxEN    0x01    /* transmit enable */
   55 #define CMD8251_DTR     0x02    /* assert DTR */
   56 #define CMD8251_RxEN    0x04    /* receive enable */
   57 #define CMD8251_SBRK    0x08    /* send break */
   58 #define CMD8251_ER      0x10    /* error reset */
   59 #define CMD8251_RTS     0x20    /* assert RTS */
   60 #define CMD8251_RESET   0x40    /* internal reset */
   61 #define CMD8251_EH      0x80    /* enter hunt mode */
   62 
   63 /* i8251 status register */
   64 #define STS8251_TxRDY   0x01    /* transmit READY */
   65 #define STS8251_RxRDY   0x02    /* data exists in receive buffer */
   66 #define STS8251_TxEMP   0x04    /* transmit buffer EMPTY */
   67 #define STS8251_PE      0x08    /* perity error */
   68 #define STS8251_OE      0x10    /* overrun error */
   69 #define STS8251_FE      0x20    /* framing error */
   70 #define STS8251_BI      0x40    /* break detect */
   71 #define STS8251_DSR     0x80    /* DSR is asserted */
   72 
   73 /* i8251F line status register */
   74 #define FLSR_TxEMP      0x01    /* transmit buffer EMPTY */
   75 #define FLSR_TxRDY      0x02    /* transmit READY */
   76 #define FLSR_RxRDY      0x04    /* data exists in receive buffer */
   77 #define FLSR_OE         0x10    /* overrun error */
   78 #define FLSR_PE         0x20    /* perity error */
   79 #define FLSR_BI         0x80    /* break detect */
   80 
   81 /* i8251F modem status register */
   82 #define MSR_DCD         0x80    /* Current Data Carrier Detect */
   83 #define MSR_RI          0x40    /* Current Ring Indicator */
   84 #define MSR_DSR         0x20    /* Current Data Set Ready */
   85 #define MSR_CTS         0x10    /* Current Clear to Send */
   86 #define MSR_DDCD        0x08    /* DCD has changed state */
   87 #define MSR_TERI        0x04    /* RI has toggled low to high */
   88 #define MSR_DDSR        0x02    /* DSR has changed state */
   89 #define MSR_DCTS        0x01    /* CTS has changed state */
   90 
   91 /* i8251F interrupt identification register */
   92 #define IIR_FIFO_CK1    0x40
   93 #define IIR_FIFO_CK2    0x20
   94 #define IIR_IMASK       0x0f
   95 #define IIR_RXTOUT      0x0c    /* Receiver timeout */
   96 #define IIR_RLS         0x06    /* Line status change */
   97 #define IIR_RXRDY       0x04    /* Receiver ready */
   98 #define IIR_TXRDY       0x02    /* Transmitter ready */
   99 #define IIR_NOPEND      0x01    /* Transmitter ready */
  100 #define IIR_MLSC        0x00    /* Modem status */
  101 
  102 /* i8251F fifo control register */
  103 #define FIFO_ENABLE     0x01    /* Turn the FIFO on */
  104 #define FIFO_RCV_RST    0x02    /* Reset RX FIFO */
  105 #define FIFO_XMT_RST    0x04    /* Reset TX FIFO */
  106 #define FIFO_LSR_EN     0x08
  107 #define FIFO_MSR_EN     0x10
  108 #define FIFO_TRIGGER_1  0x00    /* Trigger RXRDY intr on 1 character */
  109 #define FIFO_TRIGGER_4  0x40    /* ibid 4 */
  110 #define FIFO_TRIGGER_8  0x80    /* ibid 8 */
  111 #define FIFO_TRIGGER_14 0xc0    /* ibid 14 */

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