FreeBSD/Linux Kernel Cross Reference
2 * Copyright (c) 1993 The Regents of the University of California.
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29 * from: Header: timerreg.h,v 1.2 93/02/28 15:08:58 mccanne Exp
30 * $FreeBSD: releng/6.2/sys/dev/ic/i8253reg.h 146215 2005-05-14 10:26:31Z nyan $
34 * Register definitions for the Intel 8253 Programmable Interval Timer.
36 * This chip has three independent 16-bit down counters that can be
37 * read on the fly. There are three mode registers and three countdown
38 * registers. The countdown registers are addressed directly, via the
39 * first three I/O ports. The three mode registers are accessed via
40 * the fourth I/O port, with two bits in the mode byte indicating the
41 * register. (Why are hardware interfaces always so braindead?).
43 * To write a value into the countdown register, the mode register
44 * is first programmed with a command indicating the which byte of
45 * the two byte register is to be modified. The three possibilities
46 * are load msb (TMR_MR_MSB), load lsb (TMR_MR_LSB), or load lsb then
47 * msb (TMR_MR_BOTH).
49 * To read the current value ("on the fly") from the countdown register,
50 * you write a "latch" command into the mode register, then read the stable
51 * value from the corresponding I/O port. For example, you write
52 * TMR_MR_LATCH into the corresponding mode register. Presumably,
53 * after doing this, a write operation to the I/O port would result
54 * in undefined behavior (but hopefully not fry the chip).
55 * Reading in this manner has no side effects.
59 * Macros for specifying values to be written into a mode register.
61 #define TIMER_REG_CNTR0 0 /* timer 0 counter port */
62 #define TIMER_REG_CNTR1 1 /* timer 1 counter port */
63 #define TIMER_REG_CNTR2 2 /* timer 2 counter port */
64 #define TIMER_REG_MODE 3 /* timer mode port */
65 #define TIMER_SEL0 0x00 /* select counter 0 */
66 #define TIMER_SEL1 0x40 /* select counter 1 */
67 #define TIMER_SEL2 0x80 /* select counter 2 */
68 #define TIMER_INTTC 0x00 /* mode 0, intr on terminal cnt */
69 #define TIMER_ONESHOT 0x02 /* mode 1, one shot */
70 #define TIMER_RATEGEN 0x04 /* mode 2, rate generator */
71 #define TIMER_SQWAVE 0x06 /* mode 3, square wave */
72 #define TIMER_SWSTROBE 0x08 /* mode 4, s/w triggered strobe */
73 #define TIMER_HWSTROBE 0x0a /* mode 5, h/w triggered strobe */
74 #define TIMER_LATCH 0x00 /* latch counter for reading */
75 #define TIMER_LSB 0x10 /* r/w counter LSB */
76 #define TIMER_MSB 0x20 /* r/w counter MSB */
77 #define TIMER_16BIT 0x30 /* r/w counter 16 bits, LSB first */
78 #define TIMER_BCD 0x01 /* count in BCD */
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