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sys/dev/ic/i82557.c
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1 /* $NetBSD: i82557.c,v 1.81.2.2 2004/04/28 07:04:42 tron Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice unmodified, this list of conditions, and the following 50 * disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 68 */ 69 70 /* 71 * Device driver for the Intel i82557 fast Ethernet controller, 72 * and its successors, the i82558 and i82559. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.81.2.2 2004/04/28 07:04:42 tron Exp $"); 77 78 #include "bpfilter.h" 79 #include "rnd.h" 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/callout.h> 84 #include <sys/mbuf.h> 85 #include <sys/malloc.h> 86 #include <sys/kernel.h> 87 #include <sys/socket.h> 88 #include <sys/ioctl.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 92 #include <machine/endian.h> 93 94 #include <uvm/uvm_extern.h> 95 96 #if NRND > 0 97 #include <sys/rnd.h> 98 #endif 99 100 #include <net/if.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 #include <net/if_ether.h> 104 105 #if NBPFILTER > 0 106 #include <net/bpf.h> 107 #endif 108 109 #include <machine/bus.h> 110 #include <machine/intr.h> 111 112 #include <dev/mii/miivar.h> 113 114 #include <dev/ic/i82557reg.h> 115 #include <dev/ic/i82557var.h> 116 117 #include <dev/microcode/i8255x/rcvbundl.h> 118 119 /* 120 * NOTE! On the Alpha, we have an alignment constraint. The 121 * card DMAs the packet immediately following the RFA. However, 122 * the first thing in the packet is a 14-byte Ethernet header. 123 * This means that the packet is misaligned. To compensate, 124 * we actually offset the RFA 2 bytes into the cluster. This 125 * alignes the packet after the Ethernet header at a 32-bit 126 * boundary. HOWEVER! This means that the RFA is misaligned! 127 */ 128 #define RFA_ALIGNMENT_FUDGE 2 129 130 /* 131 * The configuration byte map has several undefined fields which 132 * must be one or must be zero. Set up a template for these bits 133 * only (assuming an i82557 chip), leaving the actual configuration 134 * for fxp_init(). 135 * 136 * See the definition of struct fxp_cb_config for the bit definitions. 137 */ 138 const u_int8_t fxp_cb_config_template[] = { 139 0x0, 0x0, /* cb_status */ 140 0x0, 0x0, /* cb_command */ 141 0x0, 0x0, 0x0, 0x0, /* link_addr */ 142 0x0, /* 0 */ 143 0x0, /* 1 */ 144 0x0, /* 2 */ 145 0x0, /* 3 */ 146 0x0, /* 4 */ 147 0x0, /* 5 */ 148 0x32, /* 6 */ 149 0x0, /* 7 */ 150 0x0, /* 8 */ 151 0x0, /* 9 */ 152 0x6, /* 10 */ 153 0x0, /* 11 */ 154 0x0, /* 12 */ 155 0x0, /* 13 */ 156 0xf2, /* 14 */ 157 0x48, /* 15 */ 158 0x0, /* 16 */ 159 0x40, /* 17 */ 160 0xf0, /* 18 */ 161 0x0, /* 19 */ 162 0x3f, /* 20 */ 163 0x5, /* 21 */ 164 0x0, /* 22 */ 165 0x0, /* 23 */ 166 0x0, /* 24 */ 167 0x0, /* 25 */ 168 0x0, /* 26 */ 169 0x0, /* 27 */ 170 0x0, /* 28 */ 171 0x0, /* 29 */ 172 0x0, /* 30 */ 173 0x0, /* 31 */ 174 }; 175 176 void fxp_mii_initmedia(struct fxp_softc *); 177 int fxp_mii_mediachange(struct ifnet *); 178 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 179 180 void fxp_80c24_initmedia(struct fxp_softc *); 181 int fxp_80c24_mediachange(struct ifnet *); 182 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 183 184 void fxp_start(struct ifnet *); 185 int fxp_ioctl(struct ifnet *, u_long, caddr_t); 186 void fxp_watchdog(struct ifnet *); 187 int fxp_init(struct ifnet *); 188 void fxp_stop(struct ifnet *, int); 189 190 void fxp_txintr(struct fxp_softc *); 191 void fxp_rxintr(struct fxp_softc *); 192 193 int fxp_rx_hwcksum(struct mbuf *, const struct fxp_rfa *); 194 195 void fxp_rxdrain(struct fxp_softc *); 196 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 197 int fxp_mdi_read(struct device *, int, int); 198 void fxp_statchg(struct device *); 199 void fxp_mdi_write(struct device *, int, int, int); 200 void fxp_autosize_eeprom(struct fxp_softc*); 201 void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 202 void fxp_write_eeprom(struct fxp_softc *, u_int16_t *, int, int); 203 void fxp_eeprom_update_cksum(struct fxp_softc *); 204 void fxp_get_info(struct fxp_softc *, u_int8_t *); 205 void fxp_tick(void *); 206 void fxp_mc_setup(struct fxp_softc *); 207 void fxp_load_ucode(struct fxp_softc *); 208 209 void fxp_shutdown(void *); 210 void fxp_power(int, void *); 211 212 int fxp_copy_small = 0; 213 214 /* 215 * Variables for interrupt mitigating microcode. 216 */ 217 int fxp_int_delay = 1000; /* usec */ 218 int fxp_bundle_max = 6; /* packets */ 219 220 struct fxp_phytype { 221 int fp_phy; /* type of PHY, -1 for MII at the end. */ 222 void (*fp_init)(struct fxp_softc *); 223 } fxp_phytype_table[] = { 224 { FXP_PHY_80C24, fxp_80c24_initmedia }, 225 { -1, fxp_mii_initmedia }, 226 }; 227 228 /* 229 * Set initial transmit threshold at 64 (512 bytes). This is 230 * increased by 64 (512 bytes) at a time, to maximum of 192 231 * (1536 bytes), if an underrun occurs. 232 */ 233 static int tx_threshold = 64; 234 235 /* 236 * Wait for the previous command to be accepted (but not necessarily 237 * completed). 238 */ 239 static __inline void 240 fxp_scb_wait(struct fxp_softc *sc) 241 { 242 int i = 10000; 243 244 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 245 delay(2); 246 if (i == 0) 247 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 248 } 249 250 /* 251 * Submit a command to the i82557. 252 */ 253 static __inline void 254 fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 255 { 256 257 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 258 } 259 260 /* 261 * Finish attaching an i82557 interface. Called by bus-specific front-end. 262 */ 263 void 264 fxp_attach(struct fxp_softc *sc) 265 { 266 u_int8_t enaddr[ETHER_ADDR_LEN]; 267 struct ifnet *ifp; 268 bus_dma_segment_t seg; 269 int rseg, i, error; 270 struct fxp_phytype *fp; 271 272 callout_init(&sc->sc_callout); 273 274 /* 275 * Enable some good stuff on i82558 and later. 276 */ 277 if (sc->sc_rev >= FXP_REV_82558_A4) { 278 /* Enable the extended TxCB. */ 279 sc->sc_flags |= FXPF_EXT_TXCB; 280 } 281 282 /* 283 * Enable use of extended RFDs and TCBs for 82550 284 * and later chips. Note: we need extended TXCB support 285 * too, but that's already enabled by the code above. 286 * Be careful to do this only on the right devices. 287 */ 288 if (sc->sc_rev == FXP_REV_82550 || sc->sc_rev == FXP_REV_82550_C) { 289 sc->sc_flags |= FXPF_EXT_RFA | FXPF_IPCB; 290 sc->sc_txcmd = htole16(FXP_CB_COMMAND_IPCBXMIT); 291 } else { 292 sc->sc_txcmd = htole16(FXP_CB_COMMAND_XMIT); 293 } 294 295 sc->sc_rfa_size = 296 (sc->sc_flags & FXPF_EXT_RFA) ? RFA_EXT_SIZE : RFA_SIZE; 297 298 /* 299 * Allocate the control data structures, and create and load the 300 * DMA map for it. 301 */ 302 if ((error = bus_dmamem_alloc(sc->sc_dmat, 303 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 304 0)) != 0) { 305 aprint_error( 306 "%s: unable to allocate control data, error = %d\n", 307 sc->sc_dev.dv_xname, error); 308 goto fail_0; 309 } 310 311 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 312 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 313 BUS_DMA_COHERENT)) != 0) { 314 aprint_error("%s: unable to map control data, error = %d\n", 315 sc->sc_dev.dv_xname, error); 316 goto fail_1; 317 } 318 sc->sc_cdseg = seg; 319 sc->sc_cdnseg = rseg; 320 321 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 322 323 if ((error = bus_dmamap_create(sc->sc_dmat, 324 sizeof(struct fxp_control_data), 1, 325 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 326 aprint_error("%s: unable to create control data DMA map, " 327 "error = %d\n", sc->sc_dev.dv_xname, error); 328 goto fail_2; 329 } 330 331 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 332 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 333 0)) != 0) { 334 aprint_error( 335 "%s: can't load control data DMA map, error = %d\n", 336 sc->sc_dev.dv_xname, error); 337 goto fail_3; 338 } 339 340 /* 341 * Create the transmit buffer DMA maps. 342 */ 343 for (i = 0; i < FXP_NTXCB; i++) { 344 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 345 (sc->sc_flags & FXPF_IPCB) ? FXP_IPCB_NTXSEG : FXP_NTXSEG, 346 MCLBYTES, 0, 0, &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 347 aprint_error("%s: unable to create tx DMA map %d, " 348 "error = %d\n", sc->sc_dev.dv_xname, i, error); 349 goto fail_4; 350 } 351 } 352 353 /* 354 * Create the receive buffer DMA maps. 355 */ 356 for (i = 0; i < FXP_NRFABUFS; i++) { 357 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 358 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 359 aprint_error("%s: unable to create rx DMA map %d, " 360 "error = %d\n", sc->sc_dev.dv_xname, i, error); 361 goto fail_5; 362 } 363 } 364 365 /* Initialize MAC address and media structures. */ 366 fxp_get_info(sc, enaddr); 367 368 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 369 ether_sprintf(enaddr)); 370 371 ifp = &sc->sc_ethercom.ec_if; 372 373 /* 374 * Get info about our media interface, and initialize it. Note 375 * the table terminates itself with a phy of -1, indicating 376 * that we're using MII. 377 */ 378 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 379 if (fp->fp_phy == sc->phy_primary_device) 380 break; 381 (*fp->fp_init)(sc); 382 383 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 384 ifp->if_softc = sc; 385 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 386 ifp->if_ioctl = fxp_ioctl; 387 ifp->if_start = fxp_start; 388 ifp->if_watchdog = fxp_watchdog; 389 ifp->if_init = fxp_init; 390 ifp->if_stop = fxp_stop; 391 IFQ_SET_READY(&ifp->if_snd); 392 393 if (sc->sc_flags & FXPF_IPCB) { 394 KASSERT(sc->sc_flags & FXPF_EXT_RFA); /* we have both or none */ 395 /* 396 * IFCAP_CSUM_IPv4 seems to have a problem, 397 * at least, on i82550 rev.12. 398 * specifically, it doesn't calculate ipv4 checksum correctly 399 * when sending 20 byte ipv4 header + 1 or 2 byte data. 400 * FreeBSD driver has related comments. 401 * 402 * XXX we should have separate IFCAP flags 403 * for transmit and receive. 404 */ 405 ifp->if_capabilities = 406 /*IFCAP_CSUM_IPv4 |*/ IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 407 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 408 } 409 410 /* 411 * We can support 802.1Q VLAN-sized frames. 412 */ 413 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 414 415 /* 416 * Attach the interface. 417 */ 418 if_attach(ifp); 419 ether_ifattach(ifp, enaddr); 420 #if NRND > 0 421 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 422 RND_TYPE_NET, 0); 423 #endif 424 425 #ifdef FXP_EVENT_COUNTERS 426 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 427 NULL, sc->sc_dev.dv_xname, "txstall"); 428 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 429 NULL, sc->sc_dev.dv_xname, "txintr"); 430 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 431 NULL, sc->sc_dev.dv_xname, "rxintr"); 432 #endif /* FXP_EVENT_COUNTERS */ 433 434 /* 435 * Add shutdown hook so that DMA is disabled prior to reboot. Not 436 * doing do could allow DMA to corrupt kernel memory during the 437 * reboot before the driver initializes. 438 */ 439 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 440 if (sc->sc_sdhook == NULL) 441 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 442 sc->sc_dev.dv_xname); 443 /* 444 * Add suspend hook, for similar reasons.. 445 */ 446 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 447 if (sc->sc_powerhook == NULL) 448 aprint_error("%s: WARNING: unable to establish power hook\n", 449 sc->sc_dev.dv_xname); 450 451 /* The attach is successful. */ 452 sc->sc_flags |= FXPF_ATTACHED; 453 454 return; 455 456 /* 457 * Free any resources we've allocated during the failed attach 458 * attempt. Do this in reverse order and fall though. 459 */ 460 fail_5: 461 for (i = 0; i < FXP_NRFABUFS; i++) { 462 if (sc->sc_rxmaps[i] != NULL) 463 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 464 } 465 fail_4: 466 for (i = 0; i < FXP_NTXCB; i++) { 467 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 468 bus_dmamap_destroy(sc->sc_dmat, 469 FXP_DSTX(sc, i)->txs_dmamap); 470 } 471 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 472 fail_3: 473 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 474 fail_2: 475 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 476 sizeof(struct fxp_control_data)); 477 fail_1: 478 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 479 fail_0: 480 return; 481 } 482 483 void 484 fxp_mii_initmedia(struct fxp_softc *sc) 485 { 486 int flags; 487 488 sc->sc_flags |= FXPF_MII; 489 490 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 491 sc->sc_mii.mii_readreg = fxp_mdi_read; 492 sc->sc_mii.mii_writereg = fxp_mdi_write; 493 sc->sc_mii.mii_statchg = fxp_statchg; 494 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, fxp_mii_mediachange, 495 fxp_mii_mediastatus); 496 497 flags = MIIF_NOISOLATE; 498 if (sc->sc_rev >= FXP_REV_82558_A4) 499 flags |= MIIF_DOPAUSE; 500 /* 501 * The i82557 wedges if all of its PHYs are isolated! 502 */ 503 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 504 MII_OFFSET_ANY, flags); 505 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 506 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 507 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 508 } else 509 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 510 } 511 512 void 513 fxp_80c24_initmedia(struct fxp_softc *sc) 514 { 515 516 /* 517 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 518 * doesn't have a programming interface of any sort. The 519 * media is sensed automatically based on how the link partner 520 * is configured. This is, in essence, manual configuration. 521 */ 522 aprint_normal("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 523 sc->sc_dev.dv_xname); 524 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 525 fxp_80c24_mediastatus); 526 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 527 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 528 } 529 530 /* 531 * Device shutdown routine. Called at system shutdown after sync. The 532 * main purpose of this routine is to shut off receiver DMA so that 533 * kernel memory doesn't get clobbered during warmboot. 534 */ 535 void 536 fxp_shutdown(void *arg) 537 { 538 struct fxp_softc *sc = arg; 539 540 /* 541 * Since the system's going to halt shortly, don't bother 542 * freeing mbufs. 543 */ 544 fxp_stop(&sc->sc_ethercom.ec_if, 0); 545 } 546 /* 547 * Power handler routine. Called when the system is transitioning 548 * into/out of power save modes. As with fxp_shutdown, the main 549 * purpose of this routine is to shut off receiver DMA so it doesn't 550 * clobber kernel memory at the wrong time. 551 */ 552 void 553 fxp_power(int why, void *arg) 554 { 555 struct fxp_softc *sc = arg; 556 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 557 int s; 558 559 s = splnet(); 560 switch (why) { 561 case PWR_SUSPEND: 562 case PWR_STANDBY: 563 fxp_stop(ifp, 0); 564 break; 565 case PWR_RESUME: 566 if (ifp->if_flags & IFF_UP) 567 fxp_init(ifp); 568 break; 569 case PWR_SOFTSUSPEND: 570 case PWR_SOFTSTANDBY: 571 case PWR_SOFTRESUME: 572 break; 573 } 574 splx(s); 575 } 576 577 /* 578 * Initialize the interface media. 579 */ 580 void 581 fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 582 { 583 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 584 585 /* 586 * Reset to a stable state. 587 */ 588 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 589 DELAY(100); 590 591 sc->sc_eeprom_size = 0; 592 fxp_autosize_eeprom(sc); 593 if (sc->sc_eeprom_size == 0) { 594 aprint_error("%s: failed to detect EEPROM size\n", 595 sc->sc_dev.dv_xname); 596 sc->sc_eeprom_size = 6; /* XXX panic here? */ 597 } 598 #ifdef DEBUG 599 aprint_debug("%s: detected %d word EEPROM\n", 600 sc->sc_dev.dv_xname, 1 << sc->sc_eeprom_size); 601 #endif 602 603 /* 604 * Get info about the primary PHY 605 */ 606 fxp_read_eeprom(sc, &data, 6, 1); 607 sc->phy_primary_device = 608 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 609 610 /* 611 * Read MAC address. 612 */ 613 fxp_read_eeprom(sc, myea, 0, 3); 614 enaddr[0] = myea[0] & 0xff; 615 enaddr[1] = myea[0] >> 8; 616 enaddr[2] = myea[1] & 0xff; 617 enaddr[3] = myea[1] >> 8; 618 enaddr[4] = myea[2] & 0xff; 619 enaddr[5] = myea[2] >> 8; 620 621 /* 622 * Systems based on the ICH2/ICH2-M chip from Intel, as well 623 * as some i82559 designs, have a defect where the chip can 624 * cause a PCI protocol violation if it receives a CU_RESUME 625 * command when it is entering the IDLE state. 626 * 627 * The work-around is to disable Dynamic Standby Mode, so that 628 * the chip never deasserts #CLKRUN, and always remains in the 629 * active state. 630 * 631 * Unfortunately, the only way to disable Dynamic Standby is 632 * to frob an EEPROM setting and reboot (the EEPROM setting 633 * is only consulted when the PCI bus comes out of reset). 634 * 635 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 636 */ 637 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 638 fxp_read_eeprom(sc, &data, 10, 1); 639 if (data & 0x02) { /* STB enable */ 640 aprint_error("%s: WARNING: " 641 "Disabling dynamic standby mode in EEPROM " 642 "to work around a\n", 643 sc->sc_dev.dv_xname); 644 aprint_normal( 645 "%s: WARNING: hardware bug. You must reset " 646 "the system before using this\n", 647 sc->sc_dev.dv_xname); 648 aprint_normal("%s: WARNING: interface.\n", 649 sc->sc_dev.dv_xname); 650 data &= ~0x02; 651 fxp_write_eeprom(sc, &data, 10, 1); 652 aprint_normal("%s: new EEPROM ID: 0x%04x\n", 653 sc->sc_dev.dv_xname, data); 654 fxp_eeprom_update_cksum(sc); 655 } 656 } 657 } 658 659 static void 660 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 661 { 662 uint16_t reg; 663 int x; 664 665 for (x = 1 << (len - 1); x != 0; x >>= 1) { 666 DELAY(40); 667 if (data & x) 668 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 669 else 670 reg = FXP_EEPROM_EECS; 671 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 672 DELAY(40); 673 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 674 reg | FXP_EEPROM_EESK); 675 DELAY(40); 676 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 677 } 678 DELAY(40); 679 } 680 681 /* 682 * Figure out EEPROM size. 683 * 684 * 559's can have either 64-word or 256-word EEPROMs, the 558 685 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 686 * talks about the existence of 16 to 256 word EEPROMs. 687 * 688 * The only known sizes are 64 and 256, where the 256 version is used 689 * by CardBus cards to store CIS information. 690 * 691 * The address is shifted in msb-to-lsb, and after the last 692 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 693 * after which follows the actual data. We try to detect this zero, by 694 * probing the data-out bit in the EEPROM control register just after 695 * having shifted in a bit. If the bit is zero, we assume we've 696 * shifted enough address bits. The data-out should be tri-state, 697 * before this, which should translate to a logical one. 698 * 699 * Other ways to do this would be to try to read a register with known 700 * contents with a varying number of address bits, but no such 701 * register seem to be available. The high bits of register 10 are 01 702 * on the 558 and 559, but apparently not on the 557. 703 * 704 * The Linux driver computes a checksum on the EEPROM data, but the 705 * value of this checksum is not very well documented. 706 */ 707 708 void 709 fxp_autosize_eeprom(struct fxp_softc *sc) 710 { 711 int x; 712 713 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 714 DELAY(40); 715 716 /* Shift in read opcode. */ 717 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 718 719 /* 720 * Shift in address, wait for the dummy zero following a correct 721 * address shift. 722 */ 723 for (x = 1; x <= 8; x++) { 724 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 725 DELAY(40); 726 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 727 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 728 DELAY(40); 729 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 730 FXP_EEPROM_EEDO) == 0) 731 break; 732 DELAY(40); 733 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 734 DELAY(40); 735 } 736 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 737 DELAY(40); 738 if (x != 6 && x != 8) { 739 #ifdef DEBUG 740 printf("%s: strange EEPROM size (%d)\n", 741 sc->sc_dev.dv_xname, 1 << x); 742 #endif 743 } else 744 sc->sc_eeprom_size = x; 745 } 746 747 /* 748 * Read from the serial EEPROM. Basically, you manually shift in 749 * the read opcode (one bit at a time) and then shift in the address, 750 * and then you shift out the data (all of this one bit at a time). 751 * The word size is 16 bits, so you have to provide the address for 752 * every 16 bits of data. 753 */ 754 void 755 fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 756 { 757 u_int16_t reg; 758 int i, x; 759 760 for (i = 0; i < words; i++) { 761 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 762 763 /* Shift in read opcode. */ 764 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 765 766 /* Shift in address. */ 767 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 768 769 reg = FXP_EEPROM_EECS; 770 data[i] = 0; 771 772 /* Shift out data. */ 773 for (x = 16; x > 0; x--) { 774 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 775 reg | FXP_EEPROM_EESK); 776 DELAY(40); 777 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 778 FXP_EEPROM_EEDO) 779 data[i] |= (1 << (x - 1)); 780 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 781 DELAY(40); 782 } 783 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 784 DELAY(40); 785 } 786 } 787 788 /* 789 * Write data to the serial EEPROM. 790 */ 791 void 792 fxp_write_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 793 { 794 int i, j; 795 796 for (i = 0; i < words; i++) { 797 /* Erase/write enable. */ 798 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 799 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 800 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 801 sc->sc_eeprom_size); 802 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 803 DELAY(4); 804 805 /* Shift in write opcode, address, data. */ 806 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 807 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 808 fxp_eeprom_shiftin(sc, offset, sc->sc_eeprom_size); 809 fxp_eeprom_shiftin(sc, data[i], 16); 810 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 811 DELAY(4); 812 813 /* Wait for the EEPROM to finish up. */ 814 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 815 DELAY(4); 816 for (j = 0; j < 1000; j++) { 817 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 818 FXP_EEPROM_EEDO) 819 break; 820 DELAY(50); 821 } 822 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 823 DELAY(4); 824 825 /* Erase/write disable. */ 826 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 827 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 828 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 829 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 830 DELAY(4); 831 } 832 } 833 834 /* 835 * Update the checksum of the EEPROM. 836 */ 837 void 838 fxp_eeprom_update_cksum(struct fxp_softc *sc) 839 { 840 int i; 841 uint16_t data, cksum; 842 843 cksum = 0; 844 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 845 fxp_read_eeprom(sc, &data, i, 1); 846 cksum += data; 847 } 848 i = (1 << sc->sc_eeprom_size) - 1; 849 cksum = 0xbaba - cksum; 850 fxp_read_eeprom(sc, &data, i, 1); 851 fxp_write_eeprom(sc, &cksum, i, 1); 852 printf("%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 853 sc->sc_dev.dv_xname, i, data, cksum); 854 } 855 856 /* 857 * Start packet transmission on the interface. 858 */ 859 void 860 fxp_start(struct ifnet *ifp) 861 { 862 struct fxp_softc *sc = ifp->if_softc; 863 struct mbuf *m0, *m; 864 struct fxp_txdesc *txd; 865 struct fxp_txsoft *txs; 866 bus_dmamap_t dmamap; 867 int error, lasttx, nexttx, opending, seg; 868 869 /* 870 * If we want a re-init, bail out now. 871 */ 872 if (sc->sc_flags & FXPF_WANTINIT) { 873 ifp->if_flags |= IFF_OACTIVE; 874 return; 875 } 876 877 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 878 return; 879 880 /* 881 * Remember the previous txpending and the current lasttx. 882 */ 883 opending = sc->sc_txpending; 884 lasttx = sc->sc_txlast; 885 886 /* 887 * Loop through the send queue, setting up transmit descriptors 888 * until we drain the queue, or use up all available transmit 889 * descriptors. 890 */ 891 for (;;) { 892 struct fxp_tbd *tbdp; 893 int csum_flags; 894 895 /* 896 * Grab a packet off the queue. 897 */ 898 IFQ_POLL(&ifp->if_snd, m0); 899 if (m0 == NULL) 900 break; 901 m = NULL; 902 903 if (sc->sc_txpending == FXP_NTXCB) { 904 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 905 break; 906 } 907 908 /* 909 * Get the next available transmit descriptor. 910 */ 911 nexttx = FXP_NEXTTX(sc->sc_txlast); 912 txd = FXP_CDTX(sc, nexttx); 913 txs = FXP_DSTX(sc, nexttx); 914 dmamap = txs->txs_dmamap; 915 916 /* 917 * Load the DMA map. If this fails, the packet either 918 * didn't fit in the allotted number of frags, or we were 919 * short on resources. In this case, we'll copy and try 920 * again. 921 */ 922 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 923 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 924 MGETHDR(m, M_DONTWAIT, MT_DATA); 925 if (m == NULL) { 926 printf("%s: unable to allocate Tx mbuf\n", 927 sc->sc_dev.dv_xname); 928 break; 929 } 930 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 931 if (m0->m_pkthdr.len > MHLEN) { 932 MCLGET(m, M_DONTWAIT); 933 if ((m->m_flags & M_EXT) == 0) { 934 printf("%s: unable to allocate Tx " 935 "cluster\n", sc->sc_dev.dv_xname); 936 m_freem(m); 937 break; 938 } 939 } 940 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 941 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 942 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 943 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 944 if (error) { 945 printf("%s: unable to load Tx buffer, " 946 "error = %d\n", sc->sc_dev.dv_xname, error); 947 break; 948 } 949 } 950 951 IFQ_DEQUEUE(&ifp->if_snd, m0); 952 csum_flags = m0->m_pkthdr.csum_flags; 953 if (m != NULL) { 954 m_freem(m0); 955 m0 = m; 956 } 957 958 /* Initialize the fraglist. */ 959 tbdp = txd->txd_tbd; 960 if (sc->sc_flags & FXPF_IPCB) 961 tbdp++; 962 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 963 tbdp[seg].tb_addr = 964 htole32(dmamap->dm_segs[seg].ds_addr); 965 tbdp[seg].tb_size = 966 htole32(dmamap->dm_segs[seg].ds_len); 967 } 968 969 /* Sync the DMA map. */ 970 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 971 BUS_DMASYNC_PREWRITE); 972 973 /* 974 * Store a pointer to the packet so we can free it later. 975 */ 976 txs->txs_mbuf = m0; 977 978 /* 979 * Initialize the transmit descriptor. 980 */ 981 /* BIG_ENDIAN: no need to swap to store 0 */ 982 txd->txd_txcb.cb_status = 0; 983 txd->txd_txcb.cb_command = 984 sc->sc_txcmd | htole16(FXP_CB_COMMAND_SF); 985 txd->txd_txcb.tx_threshold = tx_threshold; 986 txd->txd_txcb.tbd_number = dmamap->dm_nsegs; 987 988 KASSERT((csum_flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) == 0); 989 if (sc->sc_flags & FXPF_IPCB) { 990 struct fxp_ipcb *ipcb; 991 /* 992 * Deal with TCP/IP checksum offload. Note that 993 * in order for TCP checksum offload to work, 994 * the pseudo header checksum must have already 995 * been computed and stored in the checksum field 996 * in the TCP header. The stack should have 997 * already done this for us. 998 */ 999 ipcb = &txd->txd_u.txdu_ipcb; 1000 memset(ipcb, 0, sizeof(*ipcb)); 1001 /* 1002 * always do hardware parsing. 1003 */ 1004 ipcb->ipcb_ip_activation_high = 1005 FXP_IPCB_HARDWAREPARSING_ENABLE; 1006 /* 1007 * ip checksum offloading. 1008 */ 1009 if (csum_flags & M_CSUM_IPv4) { 1010 ipcb->ipcb_ip_schedule |= 1011 FXP_IPCB_IP_CHECKSUM_ENABLE; 1012 } 1013 /* 1014 * TCP/UDP checksum offloading. 1015 */ 1016 if (csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1017 ipcb->ipcb_ip_schedule |= 1018 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1019 } 1020 1021 /* 1022 * request VLAN tag insertion if needed. 1023 */ 1024 if (sc->sc_ethercom.ec_nvlans != 0) { 1025 struct m_tag *vtag; 1026 1027 vtag = m_tag_find(m0, PACKET_TAG_VLAN, NULL); 1028 if (vtag) { 1029 ipcb->ipcb_vlan_id = 1030 htobe16(*(u_int *)(vtag + 1)); 1031 ipcb->ipcb_ip_activation_high |= 1032 FXP_IPCB_INSERTVLAN_ENABLE; 1033 } 1034 } 1035 } else { 1036 KASSERT((csum_flags & 1037 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) == 0); 1038 } 1039 1040 FXP_CDTXSYNC(sc, nexttx, 1041 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1042 1043 /* Advance the tx pointer. */ 1044 sc->sc_txpending++; 1045 sc->sc_txlast = nexttx; 1046 1047 #if NBPFILTER > 0 1048 /* 1049 * Pass packet to bpf if there is a listener. 1050 */ 1051 if (ifp->if_bpf) 1052 bpf_mtap(ifp->if_bpf, m0); 1053 #endif 1054 } 1055 1056 if (sc->sc_txpending == FXP_NTXCB) { 1057 /* No more slots; notify upper layer. */ 1058 ifp->if_flags |= IFF_OACTIVE; 1059 } 1060 1061 if (sc->sc_txpending != opending) { 1062 /* 1063 * We enqueued packets. If the transmitter was idle, 1064 * reset the txdirty pointer. 1065 */ 1066 if (opending == 0) 1067 sc->sc_txdirty = FXP_NEXTTX(lasttx); 1068 1069 /* 1070 * Cause the chip to interrupt and suspend command 1071 * processing once the last packet we've enqueued 1072 * has been transmitted. 1073 */ 1074 FXP_CDTX(sc, sc->sc_txlast)->txd_txcb.cb_command |= 1075 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 1076 FXP_CDTXSYNC(sc, sc->sc_txlast, 1077 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1078 1079 /* 1080 * The entire packet chain is set up. Clear the suspend bit 1081 * on the command prior to the first packet we set up. 1082 */ 1083 FXP_CDTXSYNC(sc, lasttx, 1084 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1085 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 1086 htole16(~FXP_CB_COMMAND_S); 1087 FXP_CDTXSYNC(sc, lasttx, 1088 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1089 1090 /* 1091 * Issue a Resume command in case the chip was suspended. 1092 */ 1093 fxp_scb_wait(sc); 1094 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1095 1096 /* Set a watchdog timer in case the chip flakes out. */ 1097 ifp->if_timer = 5; 1098 } 1099 } 1100 1101 /* 1102 * Process interface interrupts. 1103 */ 1104 int 1105 fxp_intr(void *arg) 1106 { 1107 struct fxp_softc *sc = arg; 1108 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1109 bus_dmamap_t rxmap; 1110 int claimed = 0; 1111 u_int8_t statack; 1112 1113 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0 || sc->sc_enabled == 0) 1114 return (0); 1115 /* 1116 * If the interface isn't running, don't try to 1117 * service the interrupt.. just ack it and bail. 1118 */ 1119 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1120 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1121 if (statack) { 1122 claimed = 1; 1123 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1124 } 1125 return (claimed); 1126 } 1127 1128 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1129 claimed = 1; 1130 1131 /* 1132 * First ACK all the interrupts in this pass. 1133 */ 1134 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1135 1136 /* 1137 * Process receiver interrupts. If a no-resource (RNR) 1138 * condition exists, get whatever packets we can and 1139 * re-start the receiver. 1140 */ 1141 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1142 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1143 fxp_rxintr(sc); 1144 } 1145 1146 if (statack & FXP_SCB_STATACK_RNR) { 1147 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1148 fxp_scb_wait(sc); 1149 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1150 rxmap->dm_segs[0].ds_addr + 1151 RFA_ALIGNMENT_FUDGE); 1152 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1153 } 1154 1155 /* 1156 * Free any finished transmit mbuf chains. 1157 */ 1158 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1159 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1160 fxp_txintr(sc); 1161 1162 /* 1163 * Try to get more packets going. 1164 */ 1165 fxp_start(ifp); 1166 1167 if (sc->sc_txpending == 0) { 1168 /* 1169 * If we want a re-init, do that now. 1170 */ 1171 if (sc->sc_flags & FXPF_WANTINIT) 1172 (void) fxp_init(ifp); 1173 } 1174 } 1175 } 1176 1177 #if NRND > 0 1178 if (claimed) 1179 rnd_add_uint32(&sc->rnd_source, statack); 1180 #endif 1181 return (claimed); 1182 } 1183 1184 /* 1185 * Handle transmit completion interrupts. 1186 */ 1187 void 1188 fxp_txintr(struct fxp_softc *sc) 1189 { 1190 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1191 struct fxp_txdesc *txd; 1192 struct fxp_txsoft *txs; 1193 int i; 1194 u_int16_t txstat; 1195 1196 ifp->if_flags &= ~IFF_OACTIVE; 1197 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1198 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1199 txd = FXP_CDTX(sc, i); 1200 txs = FXP_DSTX(sc, i); 1201 1202 FXP_CDTXSYNC(sc, i, 1203 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1204 1205 txstat = le16toh(txd->txd_txcb.cb_status); 1206 1207 if ((txstat & FXP_CB_STATUS_C) == 0) 1208 break; 1209 1210 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1211 0, txs->txs_dmamap->dm_mapsize, 1212 BUS_DMASYNC_POSTWRITE); 1213 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1214 m_freem(txs->txs_mbuf); 1215 txs->txs_mbuf = NULL; 1216 } 1217 1218 /* Update the dirty transmit buffer pointer. */ 1219 sc->sc_txdirty = i; 1220 1221 /* 1222 * Cancel the watchdog timer if there are no pending 1223 * transmissions. 1224 */ 1225 if (sc->sc_txpending == 0) 1226 ifp->if_timer = 0; 1227 } 1228 1229 /* 1230 * fxp_rx_hwcksum: check status of H/W offloading for received packets. 1231 */ 1232 1233 int 1234 fxp_rx_hwcksum(struct mbuf *m, const struct fxp_rfa *rfa) 1235 { 1236 u_int16_t rxparsestat; 1237 u_int16_t csum_stat; 1238 u_int32_t csum_data; 1239 int csum_flags; 1240 1241 /* 1242 * check VLAN tag stripping. 1243 */ 1244 1245 if (rfa->rfa_status & htole16(FXP_RFA_STATUS_VLAN)) { 1246 struct m_tag *vtag; 1247 1248 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), M_NOWAIT); 1249 if (vtag == NULL) 1250 return ENOMEM; 1251 *(u_int *)(vtag + 1) = be16toh(rfa->vlan_id); 1252 m_tag_prepend(m, vtag); 1253 } 1254 1255 /* 1256 * check H/W Checksumming. 1257 */ 1258 1259 csum_stat = le16toh(rfa->cksum_stat); 1260 rxparsestat = le16toh(rfa->rx_parse_stat); 1261 if (!(rfa->rfa_status & htole16(FXP_RFA_STATUS_PARSE))) 1262 return 0; 1263 1264 csum_flags = 0; 1265 csum_data = 0; 1266 1267 if (csum_stat & FXP_RFDX_CS_IP_CSUM_BIT_VALID) { 1268 csum_flags = M_CSUM_IPv4; 1269 if (!(csum_stat & FXP_RFDX_CS_IP_CSUM_VALID)) 1270 csum_flags |= M_CSUM_IPv4_BAD; 1271 } 1272 1273 if (csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) { 1274 csum_flags |= (M_CSUM_TCPv4|M_CSUM_UDPv4); /* XXX */ 1275 if (!(csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) 1276 csum_flags |= M_CSUM_TCP_UDP_BAD; 1277 } 1278 1279 m->m_pkthdr.csum_flags = csum_flags; 1280 m->m_pkthdr.csum_data = csum_data; 1281 1282 return 0; 1283 } 1284 1285 /* 1286 * Handle receive interrupts. 1287 */ 1288 void 1289 fxp_rxintr(struct fxp_softc *sc) 1290 { 1291 struct ethercom *ec = &sc->sc_ethercom; 1292 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1293 struct mbuf *m, *m0; 1294 bus_dmamap_t rxmap; 1295 struct fxp_rfa *rfa; 1296 u_int16_t len, rxstat; 1297 1298 for (;;) { 1299 m = sc->sc_rxq.ifq_head; 1300 rfa = FXP_MTORFA(m); 1301 rxmap = M_GETCTX(m, bus_dmamap_t); 1302 1303 FXP_RFASYNC(sc, m, 1304 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1305 1306 rxstat = le16toh(rfa->rfa_status); 1307 1308 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1309 /* 1310 * We have processed all of the 1311 * receive buffers. 1312 */ 1313 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1314 return; 1315 } 1316 1317 IF_DEQUEUE(&sc->sc_rxq, m); 1318 1319 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1320 1321 len = le16toh(rfa->actual_size) & 1322 (m->m_ext.ext_size - 1); 1323 1324 if (len < sizeof(struct ether_header)) { 1325 /* 1326 * Runt packet; drop it now. 1327 */ 1328 FXP_INIT_RFABUF(sc, m); 1329 continue; 1330 } 1331 1332 /* 1333 * If support for 802.1Q VLAN sized frames is 1334 * enabled, we need to do some additional error 1335 * checking (as we are saving bad frames, in 1336 * order to receive the larger ones). 1337 */ 1338 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1339 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1340 FXP_RFA_STATUS_RNR| 1341 FXP_RFA_STATUS_ALIGN| 1342 FXP_RFA_STATUS_CRC)) != 0) { 1343 FXP_INIT_RFABUF(sc, m); 1344 continue; 1345 } 1346 1347 /* Do checksum checking. */ 1348 m->m_pkthdr.csum_flags = 0; 1349 if (sc->sc_flags & FXPF_EXT_RFA) 1350 if (fxp_rx_hwcksum(m, rfa)) 1351 goto dropit; 1352 1353 /* 1354 * If the packet is small enough to fit in a 1355 * single header mbuf, allocate one and copy 1356 * the data into it. This greatly reduces 1357 * memory consumption when we receive lots 1358 * of small packets. 1359 * 1360 * Otherwise, we add a new buffer to the receive 1361 * chain. If this fails, we drop the packet and 1362 * recycle the old buffer. 1363 */ 1364 if (fxp_copy_small != 0 && len <= MHLEN) { 1365 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1366 if (m0 == NULL) 1367 goto dropit; 1368 MCLAIM(m0, &sc->sc_ethercom.ec_rx_mowner); 1369 memcpy(mtod(m0, caddr_t), 1370 mtod(m, caddr_t), len); 1371 m0->m_pkthdr.csum_flags = m->m_pkthdr.csum_flags; 1372 m0->m_pkthdr.csum_data = m->m_pkthdr.csum_data; 1373 FXP_INIT_RFABUF(sc, m); 1374 m = m0; 1375 } else { 1376 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1377 dropit: 1378 ifp->if_ierrors++; 1379 FXP_INIT_RFABUF(sc, m); 1380 continue; 1381 } 1382 } 1383 1384 m->m_pkthdr.rcvif = ifp; 1385 m->m_pkthdr.len = m->m_len = len; 1386 1387 #if NBPFILTER > 0 1388 /* 1389 * Pass this up to any BPF listeners, but only 1390 * pass it up the stack it its for us. 1391 */ 1392 if (ifp->if_bpf) 1393 bpf_mtap(ifp->if_bpf, m); 1394 #endif 1395 1396 /* Pass it on. */ 1397 (*ifp->if_input)(ifp, m); 1398 } 1399 } 1400 1401 /* 1402 * Update packet in/out/collision statistics. The i82557 doesn't 1403 * allow you to access these counters without doing a fairly 1404 * expensive DMA to get _all_ of the statistics it maintains, so 1405 * we do this operation here only once per second. The statistics 1406 * counters in the kernel are updated from the previous dump-stats 1407 * DMA and then a new dump-stats DMA is started. The on-chip 1408 * counters are zeroed when the DMA completes. If we can't start 1409 * the DMA immediately, we don't wait - we just prepare to read 1410 * them again next time. 1411 */ 1412 void 1413 fxp_tick(void *arg) 1414 { 1415 struct fxp_softc *sc = arg; 1416 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1417 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1418 int s; 1419 1420 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1421 return; 1422 1423 s = splnet(); 1424 1425 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1426 1427 ifp->if_opackets += le32toh(sp->tx_good); 1428 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1429 if (sp->rx_good) { 1430 ifp->if_ipackets += le32toh(sp->rx_good); 1431 sc->sc_rxidle = 0; 1432 } else { 1433 sc->sc_rxidle++; 1434 } 1435 ifp->if_ierrors += 1436 le32toh(sp->rx_crc_errors) + 1437 le32toh(sp->rx_alignment_errors) + 1438 le32toh(sp->rx_rnr_errors) + 1439 le32toh(sp->rx_overrun_errors); 1440 /* 1441 * If any transmit underruns occurred, bump up the transmit 1442 * threshold by another 512 bytes (64 * 8). 1443 */ 1444 if (sp->tx_underruns) { 1445 ifp->if_oerrors += le32toh(sp->tx_underruns); 1446 if (tx_threshold < 192) 1447 tx_threshold += 64; 1448 } 1449 1450 /* 1451 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1452 * then assume the receiver has locked up and attempt to clear 1453 * the condition by reprogramming the multicast filter (actually, 1454 * resetting the interface). This is a work-around for a bug in 1455 * the 82557 where the receiver locks up if it gets certain types 1456 * of garbage in the synchronization bits prior to the packet header. 1457 * This bug is supposed to only occur in 10Mbps mode, but has been 1458 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1459 * speed transition). 1460 */ 1461 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1462 (void) fxp_init(ifp); 1463 splx(s); 1464 return; 1465 } 1466 /* 1467 * If there is no pending command, start another stats 1468 * dump. Otherwise punt for now. 1469 */ 1470 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1471 /* 1472 * Start another stats dump. 1473 */ 1474 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1475 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1476 } else { 1477 /* 1478 * A previous command is still waiting to be accepted. 1479 * Just zero our copy of the stats and wait for the 1480 * next timer event to update them. 1481 */ 1482 /* BIG_ENDIAN: no swap required to store 0 */ 1483 sp->tx_good = 0; 1484 sp->tx_underruns = 0; 1485 sp->tx_total_collisions = 0; 1486 1487 sp->rx_good = 0; 1488 sp->rx_crc_errors = 0; 1489 sp->rx_alignment_errors = 0; 1490 sp->rx_rnr_errors = 0; 1491 sp->rx_overrun_errors = 0; 1492 } 1493 1494 if (sc->sc_flags & FXPF_MII) { 1495 /* Tick the MII clock. */ 1496 mii_tick(&sc->sc_mii); 1497 } 1498 1499 splx(s); 1500 1501 /* 1502 * Schedule another timeout one second from now. 1503 */ 1504 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1505 } 1506 1507 /* 1508 * Drain the receive queue. 1509 */ 1510 void 1511 fxp_rxdrain(struct fxp_softc *sc) 1512 { 1513 bus_dmamap_t rxmap; 1514 struct mbuf *m; 1515 1516 for (;;) { 1517 IF_DEQUEUE(&sc->sc_rxq, m); 1518 if (m == NULL) 1519 break; 1520 rxmap = M_GETCTX(m, bus_dmamap_t); 1521 bus_dmamap_unload(sc->sc_dmat, rxmap); 1522 FXP_RXMAP_PUT(sc, rxmap); 1523 m_freem(m); 1524 } 1525 } 1526 1527 /* 1528 * Stop the interface. Cancels the statistics updater and resets 1529 * the interface. 1530 */ 1531 void 1532 fxp_stop(struct ifnet *ifp, int disable) 1533 { 1534 struct fxp_softc *sc = ifp->if_softc; 1535 struct fxp_txsoft *txs; 1536 int i; 1537 1538 /* 1539 * Turn down interface (done early to avoid bad interactions 1540 * between panics, shutdown hooks, and the watchdog timer) 1541 */ 1542 ifp->if_timer = 0; 1543 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1544 1545 /* 1546 * Cancel stats updater. 1547 */ 1548 callout_stop(&sc->sc_callout); 1549 if (sc->sc_flags & FXPF_MII) { 1550 /* Down the MII. */ 1551 mii_down(&sc->sc_mii); 1552 } 1553 1554 /* 1555 * Issue software reset. This unloads any microcode that 1556 * might already be loaded. 1557 */ 1558 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1559 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1560 DELAY(50); 1561 1562 /* 1563 * Release any xmit buffers. 1564 */ 1565 for (i = 0; i < FXP_NTXCB; i++) { 1566 txs = FXP_DSTX(sc, i); 1567 if (txs->txs_mbuf != NULL) { 1568 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1569 m_freem(txs->txs_mbuf); 1570 txs->txs_mbuf = NULL; 1571 } 1572 } 1573 sc->sc_txpending = 0; 1574 1575 if (disable) { 1576 fxp_rxdrain(sc); 1577 fxp_disable(sc); 1578 } 1579 1580 } 1581 1582 /* 1583 * Watchdog/transmission transmit timeout handler. Called when a 1584 * transmission is started on the interface, but no interrupt is 1585 * received before the timeout. This usually indicates that the 1586 * card has wedged for some reason. 1587 */ 1588 void 1589 fxp_watchdog(struct ifnet *ifp) 1590 { 1591 struct fxp_softc *sc = ifp->if_softc; 1592 1593 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1594 ifp->if_oerrors++; 1595 1596 (void) fxp_init(ifp); 1597 } 1598 1599 /* 1600 * Initialize the interface. Must be called at splnet(). 1601 */ 1602 int 1603 fxp_init(struct ifnet *ifp) 1604 { 1605 struct fxp_softc *sc = ifp->if_softc; 1606 struct fxp_cb_config *cbp; 1607 struct fxp_cb_ias *cb_ias; 1608 struct fxp_txdesc *txd; 1609 bus_dmamap_t rxmap; 1610 int i, prm, save_bf, lrxen, vlan_drop, allm, error = 0; 1611 1612 if ((error = fxp_enable(sc)) != 0) 1613 goto out; 1614 1615 /* 1616 * Cancel any pending I/O 1617 */ 1618 fxp_stop(ifp, 0); 1619 1620 /* 1621 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1622 * flag, and this prevents the MII from detaching resulting in 1623 * a panic. The flags field should perhaps be split in runtime 1624 * flags and more static information. For now, just clear the 1625 * only other flag set. 1626 */ 1627 1628 sc->sc_flags &= ~FXPF_WANTINIT; 1629 1630 /* 1631 * Initialize base of CBL and RFA memory. Loading with zero 1632 * sets it up for regular linear addressing. 1633 */ 1634 fxp_scb_wait(sc); 1635 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1636 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1637 1638 fxp_scb_wait(sc); 1639 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1640 1641 /* 1642 * Initialize the multicast filter. Do this now, since we might 1643 * have to setup the config block differently. 1644 */ 1645 fxp_mc_setup(sc); 1646 1647 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1648 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1649 1650 /* 1651 * In order to support receiving 802.1Q VLAN frames, we have to 1652 * enable "save bad frames", since they are 4 bytes larger than 1653 * the normal Ethernet maximum frame length. On i82558 and later, 1654 * we have a better mechanism for this. 1655 */ 1656 save_bf = 0; 1657 lrxen = 0; 1658 vlan_drop = 0; 1659 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1660 if (sc->sc_rev < FXP_REV_82558_A4) 1661 save_bf = 1; 1662 else 1663 lrxen = 1; 1664 if (sc->sc_rev >= FXP_REV_82550) 1665 vlan_drop = 1; 1666 } 1667 1668 /* 1669 * Initialize base of dump-stats buffer. 1670 */ 1671 fxp_scb_wait(sc); 1672 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1673 sc->sc_cddma + FXP_CDSTATSOFF); 1674 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1675 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1676 1677 cbp = &sc->sc_control_data->fcd_configcb; 1678 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1679 1680 /* 1681 * Load microcode for this controller. 1682 */ 1683 fxp_load_ucode(sc); 1684 1685 /* 1686 * This copy is kind of disgusting, but there are a bunch of must be 1687 * zero and must be one bits in this structure and this is the easiest 1688 * way to initialize them all to proper values. 1689 */ 1690 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1691 1692 /* BIG_ENDIAN: no need to swap to store 0 */ 1693 cbp->cb_status = 0; 1694 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1695 FXP_CB_COMMAND_EL); 1696 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1697 cbp->link_addr = 0xffffffff; /* (no) next command */ 1698 /* bytes in config block */ 1699 cbp->byte_count = (sc->sc_flags & FXPF_EXT_RFA) ? 1700 FXP_EXT_CONFIG_LEN : FXP_CONFIG_LEN; 1701 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1702 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1703 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1704 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1705 cbp->type_enable = 0; /* actually reserved */ 1706 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1707 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1708 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1709 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1710 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1711 cbp->late_scb = 0; /* (don't) defer SCB update */ 1712 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1713 cbp->ci_int = 1; /* interrupt on CU idle */ 1714 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1715 cbp->ext_stats_dis = 1; /* disable extended counters */ 1716 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1717 cbp->save_bf = save_bf;/* save bad frames */ 1718 cbp->disc_short_rx = !prm; /* discard short packets */ 1719 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1720 cbp->ext_rfa = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1721 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1722 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1723 /* interface mode */ 1724 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1725 cbp->csma_dis = 0; /* (don't) disable link */ 1726 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1727 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1728 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1729 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1730 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1731 cbp->nsai = 1; /* (don't) disable source addr insert */ 1732 cbp->preamble_length = 2; /* (7 byte) preamble */ 1733 cbp->loopback = 0; /* (don't) loopback */ 1734 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1735 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1736 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1737 cbp->promiscuous = prm; /* promiscuous mode */ 1738 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1739 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1740 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1741 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1742 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1743 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1744 cbp->padding = 1; /* (do) pad short tx packets */ 1745 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1746 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1747 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1748 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1749 /* must set wake_en in PMCSR also */ 1750 cbp->force_fdx = 0; /* (don't) force full duplex */ 1751 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1752 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1753 cbp->mc_all = allm; /* accept all multicasts */ 1754 cbp->ext_rx_mode = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1755 cbp->vlan_drop_en = vlan_drop; 1756 1757 if (sc->sc_rev < FXP_REV_82558_A4) { 1758 /* 1759 * The i82557 has no hardware flow control, the values 1760 * here are the defaults for the chip. 1761 */ 1762 cbp->fc_delay_lsb = 0; 1763 cbp->fc_delay_msb = 0x40; 1764 cbp->pri_fc_thresh = 3; 1765 cbp->tx_fc_dis = 0; 1766 cbp->rx_fc_restop = 0; 1767 cbp->rx_fc_restart = 0; 1768 cbp->fc_filter = 0; 1769 cbp->pri_fc_loc = 1; 1770 } else { 1771 cbp->fc_delay_lsb = 0x1f; 1772 cbp->fc_delay_msb = 0x01; 1773 cbp->pri_fc_thresh = 3; 1774 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1775 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1776 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1777 cbp->fc_filter = !prm; /* drop FC frames to host */ 1778 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1779 } 1780 1781 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1782 1783 /* 1784 * Start the config command/DMA. 1785 */ 1786 fxp_scb_wait(sc); 1787 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1788 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1789 /* ...and wait for it to complete. */ 1790 i = 1000; 1791 do { 1792 FXP_CDCONFIGSYNC(sc, 1793 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1794 DELAY(1); 1795 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1796 if (i == 0) { 1797 printf("%s at line %d: dmasync timeout\n", 1798 sc->sc_dev.dv_xname, __LINE__); 1799 return (ETIMEDOUT); 1800 } 1801 1802 /* 1803 * Initialize the station address. 1804 */ 1805 cb_ias = &sc->sc_control_data->fcd_iascb; 1806 /* BIG_ENDIAN: no need to swap to store 0 */ 1807 cb_ias->cb_status = 0; 1808 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1809 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1810 cb_ias->link_addr = 0xffffffff; 1811 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1812 1813 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1814 1815 /* 1816 * Start the IAS (Individual Address Setup) command/DMA. 1817 */ 1818 fxp_scb_wait(sc); 1819 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1820 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1821 /* ...and wait for it to complete. */ 1822 i = 1000; 1823 do { 1824 FXP_CDIASSYNC(sc, 1825 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1826 DELAY(1); 1827 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1828 if (i == 0) { 1829 printf("%s at line %d: dmasync timeout\n", 1830 sc->sc_dev.dv_xname, __LINE__); 1831 return (ETIMEDOUT); 1832 } 1833 1834 /* 1835 * Initialize the transmit descriptor ring. txlast is initialized 1836 * to the end of the list so that it will wrap around to the first 1837 * descriptor when the first packet is transmitted. 1838 */ 1839 for (i = 0; i < FXP_NTXCB; i++) { 1840 txd = FXP_CDTX(sc, i); 1841 memset(txd, 0, sizeof(*txd)); 1842 txd->txd_txcb.cb_command = 1843 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1844 txd->txd_txcb.link_addr = 1845 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1846 if (sc->sc_flags & FXPF_EXT_TXCB) 1847 txd->txd_txcb.tbd_array_addr = 1848 htole32(FXP_CDTBDADDR(sc, i) + 1849 (2 * sizeof(struct fxp_tbd))); 1850 else 1851 txd->txd_txcb.tbd_array_addr = 1852 htole32(FXP_CDTBDADDR(sc, i)); 1853 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1854 } 1855 sc->sc_txpending = 0; 1856 sc->sc_txdirty = 0; 1857 sc->sc_txlast = FXP_NTXCB - 1; 1858 1859 /* 1860 * Initialize the receive buffer list. 1861 */ 1862 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1863 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1864 rxmap = FXP_RXMAP_GET(sc); 1865 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1866 printf("%s: unable to allocate or map rx " 1867 "buffer %d, error = %d\n", 1868 sc->sc_dev.dv_xname, 1869 sc->sc_rxq.ifq_len, error); 1870 /* 1871 * XXX Should attempt to run with fewer receive 1872 * XXX buffers instead of just failing. 1873 */ 1874 FXP_RXMAP_PUT(sc, rxmap); 1875 fxp_rxdrain(sc); 1876 goto out; 1877 } 1878 } 1879 sc->sc_rxidle = 0; 1880 1881 /* 1882 * Give the transmit ring to the chip. We do this by pointing 1883 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1884 * issuing a start command. It will execute the NOP and then 1885 * suspend, pointing at the first descriptor. 1886 */ 1887 fxp_scb_wait(sc); 1888 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1889 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1890 1891 /* 1892 * Initialize receiver buffer area - RFA. 1893 */ 1894 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1895 fxp_scb_wait(sc); 1896 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1897 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1898 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1899 1900 if (sc->sc_flags & FXPF_MII) { 1901 /* 1902 * Set current media. 1903 */ 1904 mii_mediachg(&sc->sc_mii); 1905 } 1906 1907 /* 1908 * ...all done! 1909 */ 1910 ifp->if_flags |= IFF_RUNNING; 1911 ifp->if_flags &= ~IFF_OACTIVE; 1912 1913 /* 1914 * Start the one second timer. 1915 */ 1916 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1917 1918 /* 1919 * Attempt to start output on the interface. 1920 */ 1921 fxp_start(ifp); 1922 1923 out: 1924 if (error) { 1925 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1926 ifp->if_timer = 0; 1927 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1928 } 1929 return (error); 1930 } 1931 1932 /* 1933 * Change media according to request. 1934 */ 1935 int 1936 fxp_mii_mediachange(struct ifnet *ifp) 1937 { 1938 struct fxp_softc *sc = ifp->if_softc; 1939 1940 if (ifp->if_flags & IFF_UP) 1941 mii_mediachg(&sc->sc_mii); 1942 return (0); 1943 } 1944 1945 /* 1946 * Notify the world which media we're using. 1947 */ 1948 void 1949 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1950 { 1951 struct fxp_softc *sc = ifp->if_softc; 1952 1953 if (sc->sc_enabled == 0) { 1954 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1955 ifmr->ifm_status = 0; 1956 return; 1957 } 1958 1959 mii_pollstat(&sc->sc_mii); 1960 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1961 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1962 } 1963 1964 int 1965 fxp_80c24_mediachange(struct ifnet *ifp) 1966 { 1967 1968 /* Nothing to do here. */ 1969 return (0); 1970 } 1971 1972 void 1973 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1974 { 1975 struct fxp_softc *sc = ifp->if_softc; 1976 1977 /* 1978 * Media is currently-selected media. We cannot determine 1979 * the link status. 1980 */ 1981 ifmr->ifm_status = 0; 1982 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1983 } 1984 1985 /* 1986 * Add a buffer to the end of the RFA buffer list. 1987 * Return 0 if successful, error code on failure. 1988 * 1989 * The RFA struct is stuck at the beginning of mbuf cluster and the 1990 * data pointer is fixed up to point just past it. 1991 */ 1992 int 1993 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 1994 { 1995 struct mbuf *m; 1996 int error; 1997 1998 MGETHDR(m, M_DONTWAIT, MT_DATA); 1999 if (m == NULL) 2000 return (ENOBUFS); 2001 2002 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2003 MCLGET(m, M_DONTWAIT); 2004 if ((m->m_flags & M_EXT) == 0) { 2005 m_freem(m); 2006 return (ENOBUFS); 2007 } 2008 2009 if (unload) 2010 bus_dmamap_unload(sc->sc_dmat, rxmap); 2011 2012 M_SETCTX(m, rxmap); 2013 2014 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2015 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, 2016 BUS_DMA_READ|BUS_DMA_NOWAIT); 2017 if (error) { 2018 printf("%s: can't load rx DMA map %d, error = %d\n", 2019 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 2020 panic("fxp_add_rfabuf"); /* XXX */ 2021 } 2022 2023 FXP_INIT_RFABUF(sc, m); 2024 2025 return (0); 2026 } 2027 2028 int 2029 fxp_mdi_read(struct device *self, int phy, int reg) 2030 { 2031 struct fxp_softc *sc = (struct fxp_softc *)self; 2032 int count = 10000; 2033 int value; 2034 2035 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2036 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2037 2038 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 2039 0x10000000) == 0 && count--) 2040 DELAY(10); 2041 2042 if (count <= 0) 2043 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 2044 2045 return (value & 0xffff); 2046 } 2047 2048 void 2049 fxp_statchg(struct device *self) 2050 { 2051 2052 /* Nothing to do. */ 2053 } 2054 2055 void 2056 fxp_mdi_write(struct device *self, int phy, int reg, int value) 2057 { 2058 struct fxp_softc *sc = (struct fxp_softc *)self; 2059 int count = 10000; 2060 2061 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2062 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2063 (value & 0xffff)); 2064 2065 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2066 count--) 2067 DELAY(10); 2068 2069 if (count <= 0) 2070 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 2071 } 2072 2073 int 2074 fxp_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2075 { 2076 struct fxp_softc *sc = ifp->if_softc; 2077 struct ifreq *ifr = (struct ifreq *)data; 2078 int s, error; 2079 2080 s = splnet(); 2081 2082 switch (cmd) { 2083 case SIOCSIFMEDIA: 2084 case SIOCGIFMEDIA: 2085 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2086 break; 2087 2088 default: 2089 error = ether_ioctl(ifp, cmd, data); 2090 if (error == ENETRESET) { 2091 if (sc->sc_enabled) { 2092 /* 2093 * Multicast list has changed; set the 2094 * hardware filter accordingly. 2095 */ 2096 if (sc->sc_txpending) { 2097 sc->sc_flags |= FXPF_WANTINIT; 2098 error = 0; 2099 } else 2100 error = fxp_init(ifp); 2101 } else 2102 error = 0; 2103 } 2104 break; 2105 } 2106 2107 /* Try to get more packets going. */ 2108 if (sc->sc_enabled) 2109 fxp_start(ifp); 2110 2111 splx(s); 2112 return (error); 2113 } 2114 2115 /* 2116 * Program the multicast filter. 2117 * 2118 * This function must be called at splnet(). 2119 */ 2120 void 2121 fxp_mc_setup(struct fxp_softc *sc) 2122 { 2123 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 2124 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2125 struct ethercom *ec = &sc->sc_ethercom; 2126 struct ether_multi *enm; 2127 struct ether_multistep step; 2128 int count, nmcasts; 2129 2130 #ifdef DIAGNOSTIC 2131 if (sc->sc_txpending) 2132 panic("fxp_mc_setup: pending transmissions"); 2133 #endif 2134 2135 ifp->if_flags &= ~IFF_ALLMULTI; 2136 2137 /* 2138 * Initialize multicast setup descriptor. 2139 */ 2140 nmcasts = 0; 2141 ETHER_FIRST_MULTI(step, ec, enm); 2142 while (enm != NULL) { 2143 /* 2144 * Check for too many multicast addresses or if we're 2145 * listening to a range. Either way, we simply have 2146 * to accept all multicasts. 2147 */ 2148 if (nmcasts >= MAXMCADDR || 2149 memcmp(enm->enm_addrlo, enm->enm_addrhi, 2150 ETHER_ADDR_LEN) != 0) { 2151 /* 2152 * Callers of this function must do the 2153 * right thing with this. If we're called 2154 * from outside fxp_init(), the caller must 2155 * detect if the state if IFF_ALLMULTI changes. 2156 * If it does, the caller must then call 2157 * fxp_init(), since allmulti is handled by 2158 * the config block. 2159 */ 2160 ifp->if_flags |= IFF_ALLMULTI; 2161 return; 2162 } 2163 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 2164 ETHER_ADDR_LEN); 2165 nmcasts++; 2166 ETHER_NEXT_MULTI(step, enm); 2167 } 2168 2169 /* BIG_ENDIAN: no need to swap to store 0 */ 2170 mcsp->cb_status = 0; 2171 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2172 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2173 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2174 2175 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2176 2177 /* 2178 * Wait until the command unit is not active. This should never 2179 * happen since nothing is queued, but make sure anyway. 2180 */ 2181 count = 100; 2182 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2183 FXP_SCB_CUS_ACTIVE && --count) 2184 DELAY(1); 2185 if (count == 0) { 2186 printf("%s at line %d: command queue timeout\n", 2187 sc->sc_dev.dv_xname, __LINE__); 2188 return; 2189 } 2190 2191 /* 2192 * Start the multicast setup command/DMA. 2193 */ 2194 fxp_scb_wait(sc); 2195 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2196 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2197 2198 /* ...and wait for it to complete. */ 2199 count = 1000; 2200 do { 2201 FXP_CDMCSSYNC(sc, 2202 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2203 DELAY(1); 2204 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2205 if (count == 0) { 2206 printf("%s at line %d: dmasync timeout\n", 2207 sc->sc_dev.dv_xname, __LINE__); 2208 return; 2209 } 2210 } 2211 2212 static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2213 static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2214 static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2215 static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2216 static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2217 static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2218 2219 #define UCODE(x) x, sizeof(x) 2220 2221 static const struct ucode { 2222 int32_t revision; 2223 const uint32_t *ucode; 2224 size_t length; 2225 uint16_t int_delay_offset; 2226 uint16_t bundle_max_offset; 2227 } ucode_table[] = { 2228 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2229 D101_CPUSAVER_DWORD, 0 }, 2230 2231 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2232 D101_CPUSAVER_DWORD, 0 }, 2233 2234 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2235 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2236 2237 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2238 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2239 2240 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2241 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2242 2243 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2244 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2245 2246 { 0, NULL, 0, 0, 0 } 2247 }; 2248 2249 void 2250 fxp_load_ucode(struct fxp_softc *sc) 2251 { 2252 const struct ucode *uc; 2253 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2254 int count; 2255 2256 if (sc->sc_flags & FXPF_UCODE_LOADED) 2257 return; 2258 2259 /* 2260 * Only load the uCode if the user has requested that 2261 * we do so. 2262 */ 2263 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2264 sc->sc_int_delay = 0; 2265 sc->sc_bundle_max = 0; 2266 return; 2267 } 2268 2269 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2270 if (sc->sc_rev == uc->revision) 2271 break; 2272 } 2273 if (uc->ucode == NULL) 2274 return; 2275 2276 /* BIG ENDIAN: no need to swap to store 0 */ 2277 cbp->cb_status = 0; 2278 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2279 cbp->link_addr = 0xffffffff; /* (no) next command */ 2280 memcpy((void *) cbp->ucode, uc->ucode, uc->length); 2281 2282 if (uc->int_delay_offset) 2283 *(uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2284 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2285 2286 if (uc->bundle_max_offset) 2287 *(uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2288 htole16(fxp_bundle_max); 2289 2290 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2291 2292 /* 2293 * Download the uCode to the chip. 2294 */ 2295 fxp_scb_wait(sc); 2296 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2297 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2298 2299 /* ...and wait for it to complete. */ 2300 count = 10000; 2301 do { 2302 FXP_CDUCODESYNC(sc, 2303 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2304 DELAY(2); 2305 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2306 if (count == 0) { 2307 sc->sc_int_delay = 0; 2308 sc->sc_bundle_max = 0; 2309 printf("%s: timeout loading microcode\n", 2310 sc->sc_dev.dv_xname); 2311 return; 2312 } 2313 2314 if (sc->sc_int_delay != fxp_int_delay || 2315 sc->sc_bundle_max != fxp_bundle_max) { 2316 sc->sc_int_delay = fxp_int_delay; 2317 sc->sc_bundle_max = fxp_bundle_max; 2318 printf("%s: Microcode loaded: int delay: %d usec, " 2319 "max bundle: %d\n", sc->sc_dev.dv_xname, 2320 sc->sc_int_delay, 2321 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2322 } 2323 2324 sc->sc_flags |= FXPF_UCODE_LOADED; 2325 } 2326 2327 int 2328 fxp_enable(struct fxp_softc *sc) 2329 { 2330 2331 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2332 if ((*sc->sc_enable)(sc) != 0) { 2333 printf("%s: device enable failed\n", 2334 sc->sc_dev.dv_xname); 2335 return (EIO); 2336 } 2337 } 2338 2339 sc->sc_enabled = 1; 2340 return (0); 2341 } 2342 2343 void 2344 fxp_disable(struct fxp_softc *sc) 2345 { 2346 2347 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2348 (*sc->sc_disable)(sc); 2349 sc->sc_enabled = 0; 2350 } 2351 } 2352 2353 /* 2354 * fxp_activate: 2355 * 2356 * Handle device activation/deactivation requests. 2357 */ 2358 int 2359 fxp_activate(struct device *self, enum devact act) 2360 { 2361 struct fxp_softc *sc = (void *) self; 2362 int s, error = 0; 2363 2364 s = splnet(); 2365 switch (act) { 2366 case DVACT_ACTIVATE: 2367 error = EOPNOTSUPP; 2368 break; 2369 2370 case DVACT_DEACTIVATE: 2371 if (sc->sc_flags & FXPF_MII) 2372 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 2373 MII_OFFSET_ANY); 2374 if_deactivate(&sc->sc_ethercom.ec_if); 2375 break; 2376 } 2377 splx(s); 2378 2379 return (error); 2380 } 2381 2382 /* 2383 * fxp_detach: 2384 * 2385 * Detach an i82557 interface. 2386 */ 2387 int 2388 fxp_detach(struct fxp_softc *sc) 2389 { 2390 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2391 int i; 2392 2393 /* Succeed now if there's no work to do. */ 2394 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2395 return (0); 2396 2397 /* Unhook our tick handler. */ 2398 callout_stop(&sc->sc_callout); 2399 2400 if (sc->sc_flags & FXPF_MII) { 2401 /* Detach all PHYs */ 2402 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2403 } 2404 2405 /* Delete all remaining media. */ 2406 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2407 2408 #if NRND > 0 2409 rnd_detach_source(&sc->rnd_source); 2410 #endif 2411 ether_ifdetach(ifp); 2412 if_detach(ifp); 2413 2414 for (i = 0; i < FXP_NRFABUFS; i++) { 2415 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2416 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2417 } 2418 2419 for (i = 0; i < FXP_NTXCB; i++) { 2420 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2421 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2422 } 2423 2424 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2425 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2426 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2427 sizeof(struct fxp_control_data)); 2428 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2429 2430 shutdownhook_disestablish(sc->sc_sdhook); 2431 powerhook_disestablish(sc->sc_powerhook); 2432 2433 return (0); 2434 }
Cache object: 3c11606b119988bda7c0737415bbaecd
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