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sys/dev/ic/i82557.c
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1 /* $NetBSD: i82557.c,v 1.89.10.2 2005/10/15 16:39:17 riz Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice unmodified, this list of conditions, and the following 50 * disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 68 */ 69 70 /* 71 * Device driver for the Intel i82557 fast Ethernet controller, 72 * and its successors, the i82558 and i82559. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.89.10.2 2005/10/15 16:39:17 riz Exp $"); 77 78 #include "bpfilter.h" 79 #include "rnd.h" 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/callout.h> 84 #include <sys/mbuf.h> 85 #include <sys/malloc.h> 86 #include <sys/kernel.h> 87 #include <sys/socket.h> 88 #include <sys/ioctl.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 #include <sys/syslog.h> 92 93 #include <machine/endian.h> 94 95 #include <uvm/uvm_extern.h> 96 97 #if NRND > 0 98 #include <sys/rnd.h> 99 #endif 100 101 #include <net/if.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 #include <net/if_ether.h> 105 106 #if NBPFILTER > 0 107 #include <net/bpf.h> 108 #endif 109 110 #include <machine/bus.h> 111 #include <machine/intr.h> 112 113 #include <dev/mii/miivar.h> 114 115 #include <dev/ic/i82557reg.h> 116 #include <dev/ic/i82557var.h> 117 118 #include <dev/microcode/i8255x/rcvbundl.h> 119 120 /* 121 * NOTE! On the Alpha, we have an alignment constraint. The 122 * card DMAs the packet immediately following the RFA. However, 123 * the first thing in the packet is a 14-byte Ethernet header. 124 * This means that the packet is misaligned. To compensate, 125 * we actually offset the RFA 2 bytes into the cluster. This 126 * alignes the packet after the Ethernet header at a 32-bit 127 * boundary. HOWEVER! This means that the RFA is misaligned! 128 */ 129 #define RFA_ALIGNMENT_FUDGE 2 130 131 /* 132 * The configuration byte map has several undefined fields which 133 * must be one or must be zero. Set up a template for these bits 134 * only (assuming an i82557 chip), leaving the actual configuration 135 * for fxp_init(). 136 * 137 * See the definition of struct fxp_cb_config for the bit definitions. 138 */ 139 const u_int8_t fxp_cb_config_template[] = { 140 0x0, 0x0, /* cb_status */ 141 0x0, 0x0, /* cb_command */ 142 0x0, 0x0, 0x0, 0x0, /* link_addr */ 143 0x0, /* 0 */ 144 0x0, /* 1 */ 145 0x0, /* 2 */ 146 0x0, /* 3 */ 147 0x0, /* 4 */ 148 0x0, /* 5 */ 149 0x32, /* 6 */ 150 0x0, /* 7 */ 151 0x0, /* 8 */ 152 0x0, /* 9 */ 153 0x6, /* 10 */ 154 0x0, /* 11 */ 155 0x0, /* 12 */ 156 0x0, /* 13 */ 157 0xf2, /* 14 */ 158 0x48, /* 15 */ 159 0x0, /* 16 */ 160 0x40, /* 17 */ 161 0xf0, /* 18 */ 162 0x0, /* 19 */ 163 0x3f, /* 20 */ 164 0x5, /* 21 */ 165 0x0, /* 22 */ 166 0x0, /* 23 */ 167 0x0, /* 24 */ 168 0x0, /* 25 */ 169 0x0, /* 26 */ 170 0x0, /* 27 */ 171 0x0, /* 28 */ 172 0x0, /* 29 */ 173 0x0, /* 30 */ 174 0x0, /* 31 */ 175 }; 176 177 void fxp_mii_initmedia(struct fxp_softc *); 178 int fxp_mii_mediachange(struct ifnet *); 179 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 180 181 void fxp_80c24_initmedia(struct fxp_softc *); 182 int fxp_80c24_mediachange(struct ifnet *); 183 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 184 185 void fxp_start(struct ifnet *); 186 int fxp_ioctl(struct ifnet *, u_long, caddr_t); 187 void fxp_watchdog(struct ifnet *); 188 int fxp_init(struct ifnet *); 189 void fxp_stop(struct ifnet *, int); 190 191 void fxp_txintr(struct fxp_softc *); 192 void fxp_rxintr(struct fxp_softc *); 193 194 int fxp_rx_hwcksum(struct mbuf *, const struct fxp_rfa *); 195 196 void fxp_rxdrain(struct fxp_softc *); 197 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 198 int fxp_mdi_read(struct device *, int, int); 199 void fxp_statchg(struct device *); 200 void fxp_mdi_write(struct device *, int, int, int); 201 void fxp_autosize_eeprom(struct fxp_softc*); 202 void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 203 void fxp_write_eeprom(struct fxp_softc *, u_int16_t *, int, int); 204 void fxp_eeprom_update_cksum(struct fxp_softc *); 205 void fxp_get_info(struct fxp_softc *, u_int8_t *); 206 void fxp_tick(void *); 207 void fxp_mc_setup(struct fxp_softc *); 208 void fxp_load_ucode(struct fxp_softc *); 209 210 void fxp_shutdown(void *); 211 void fxp_power(int, void *); 212 213 int fxp_copy_small = 0; 214 215 /* 216 * Variables for interrupt mitigating microcode. 217 */ 218 int fxp_int_delay = 1000; /* usec */ 219 int fxp_bundle_max = 6; /* packets */ 220 221 struct fxp_phytype { 222 int fp_phy; /* type of PHY, -1 for MII at the end. */ 223 void (*fp_init)(struct fxp_softc *); 224 } fxp_phytype_table[] = { 225 { FXP_PHY_80C24, fxp_80c24_initmedia }, 226 { -1, fxp_mii_initmedia }, 227 }; 228 229 /* 230 * Set initial transmit threshold at 64 (512 bytes). This is 231 * increased by 64 (512 bytes) at a time, to maximum of 192 232 * (1536 bytes), if an underrun occurs. 233 */ 234 static int tx_threshold = 64; 235 236 /* 237 * Wait for the previous command to be accepted (but not necessarily 238 * completed). 239 */ 240 static __inline void 241 fxp_scb_wait(struct fxp_softc *sc) 242 { 243 int i = 10000; 244 245 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 246 delay(2); 247 if (i == 0) 248 log(LOG_WARNING, 249 "%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 250 } 251 252 /* 253 * Submit a command to the i82557. 254 */ 255 static __inline void 256 fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 257 { 258 259 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 260 } 261 262 /* 263 * Finish attaching an i82557 interface. Called by bus-specific front-end. 264 */ 265 void 266 fxp_attach(struct fxp_softc *sc) 267 { 268 u_int8_t enaddr[ETHER_ADDR_LEN]; 269 struct ifnet *ifp; 270 bus_dma_segment_t seg; 271 int rseg, i, error; 272 struct fxp_phytype *fp; 273 274 callout_init(&sc->sc_callout); 275 276 /* 277 * Enable some good stuff on i82558 and later. 278 */ 279 if (sc->sc_rev >= FXP_REV_82558_A4) { 280 /* Enable the extended TxCB. */ 281 sc->sc_flags |= FXPF_EXT_TXCB; 282 } 283 284 /* 285 * Enable use of extended RFDs and TCBs for 82550 286 * and later chips. Note: we need extended TXCB support 287 * too, but that's already enabled by the code above. 288 * Be careful to do this only on the right devices. 289 */ 290 if (sc->sc_rev == FXP_REV_82550 || sc->sc_rev == FXP_REV_82550_C) { 291 sc->sc_flags |= FXPF_EXT_RFA | FXPF_IPCB; 292 sc->sc_txcmd = htole16(FXP_CB_COMMAND_IPCBXMIT); 293 } else { 294 sc->sc_txcmd = htole16(FXP_CB_COMMAND_XMIT); 295 } 296 297 sc->sc_rfa_size = 298 (sc->sc_flags & FXPF_EXT_RFA) ? RFA_EXT_SIZE : RFA_SIZE; 299 300 /* 301 * Allocate the control data structures, and create and load the 302 * DMA map for it. 303 */ 304 if ((error = bus_dmamem_alloc(sc->sc_dmat, 305 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 306 0)) != 0) { 307 aprint_error( 308 "%s: unable to allocate control data, error = %d\n", 309 sc->sc_dev.dv_xname, error); 310 goto fail_0; 311 } 312 313 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 314 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 315 BUS_DMA_COHERENT)) != 0) { 316 aprint_error("%s: unable to map control data, error = %d\n", 317 sc->sc_dev.dv_xname, error); 318 goto fail_1; 319 } 320 sc->sc_cdseg = seg; 321 sc->sc_cdnseg = rseg; 322 323 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 324 325 if ((error = bus_dmamap_create(sc->sc_dmat, 326 sizeof(struct fxp_control_data), 1, 327 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 328 aprint_error("%s: unable to create control data DMA map, " 329 "error = %d\n", sc->sc_dev.dv_xname, error); 330 goto fail_2; 331 } 332 333 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 334 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 335 0)) != 0) { 336 aprint_error( 337 "%s: can't load control data DMA map, error = %d\n", 338 sc->sc_dev.dv_xname, error); 339 goto fail_3; 340 } 341 342 /* 343 * Create the transmit buffer DMA maps. 344 */ 345 for (i = 0; i < FXP_NTXCB; i++) { 346 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 347 (sc->sc_flags & FXPF_IPCB) ? FXP_IPCB_NTXSEG : FXP_NTXSEG, 348 MCLBYTES, 0, 0, &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 349 aprint_error("%s: unable to create tx DMA map %d, " 350 "error = %d\n", sc->sc_dev.dv_xname, i, error); 351 goto fail_4; 352 } 353 } 354 355 /* 356 * Create the receive buffer DMA maps. 357 */ 358 for (i = 0; i < FXP_NRFABUFS; i++) { 359 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 360 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 361 aprint_error("%s: unable to create rx DMA map %d, " 362 "error = %d\n", sc->sc_dev.dv_xname, i, error); 363 goto fail_5; 364 } 365 } 366 367 /* Initialize MAC address and media structures. */ 368 fxp_get_info(sc, enaddr); 369 370 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 371 ether_sprintf(enaddr)); 372 373 ifp = &sc->sc_ethercom.ec_if; 374 375 /* 376 * Get info about our media interface, and initialize it. Note 377 * the table terminates itself with a phy of -1, indicating 378 * that we're using MII. 379 */ 380 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 381 if (fp->fp_phy == sc->phy_primary_device) 382 break; 383 (*fp->fp_init)(sc); 384 385 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 386 ifp->if_softc = sc; 387 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 388 ifp->if_ioctl = fxp_ioctl; 389 ifp->if_start = fxp_start; 390 ifp->if_watchdog = fxp_watchdog; 391 ifp->if_init = fxp_init; 392 ifp->if_stop = fxp_stop; 393 IFQ_SET_READY(&ifp->if_snd); 394 395 if (sc->sc_flags & FXPF_IPCB) { 396 KASSERT(sc->sc_flags & FXPF_EXT_RFA); /* we have both or none */ 397 /* 398 * IFCAP_CSUM_IPv4 seems to have a problem, 399 * at least, on i82550 rev.12. 400 * specifically, it doesn't calculate ipv4 checksum correctly 401 * when sending 20 byte ipv4 header + 1 or 2 byte data. 402 * FreeBSD driver has related comments. 403 * 404 * XXX we should have separate IFCAP flags 405 * for transmit and receive. 406 */ 407 ifp->if_capabilities = 408 /*IFCAP_CSUM_IPv4 |*/ IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 409 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 410 } 411 412 /* 413 * We can support 802.1Q VLAN-sized frames. 414 */ 415 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 416 417 /* 418 * Attach the interface. 419 */ 420 if_attach(ifp); 421 ether_ifattach(ifp, enaddr); 422 #if NRND > 0 423 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 424 RND_TYPE_NET, 0); 425 #endif 426 427 #ifdef FXP_EVENT_COUNTERS 428 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 429 NULL, sc->sc_dev.dv_xname, "txstall"); 430 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 431 NULL, sc->sc_dev.dv_xname, "txintr"); 432 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 433 NULL, sc->sc_dev.dv_xname, "rxintr"); 434 if (sc->sc_rev >= FXP_REV_82558_A4) { 435 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 436 NULL, sc->sc_dev.dv_xname, "txpause"); 437 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 438 NULL, sc->sc_dev.dv_xname, "rxpause"); 439 } 440 #endif /* FXP_EVENT_COUNTERS */ 441 442 /* 443 * Add shutdown hook so that DMA is disabled prior to reboot. Not 444 * doing do could allow DMA to corrupt kernel memory during the 445 * reboot before the driver initializes. 446 */ 447 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 448 if (sc->sc_sdhook == NULL) 449 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 450 sc->sc_dev.dv_xname); 451 /* 452 * Add suspend hook, for similar reasons.. 453 */ 454 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 455 if (sc->sc_powerhook == NULL) 456 aprint_error("%s: WARNING: unable to establish power hook\n", 457 sc->sc_dev.dv_xname); 458 459 /* The attach is successful. */ 460 sc->sc_flags |= FXPF_ATTACHED; 461 462 return; 463 464 /* 465 * Free any resources we've allocated during the failed attach 466 * attempt. Do this in reverse order and fall though. 467 */ 468 fail_5: 469 for (i = 0; i < FXP_NRFABUFS; i++) { 470 if (sc->sc_rxmaps[i] != NULL) 471 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 472 } 473 fail_4: 474 for (i = 0; i < FXP_NTXCB; i++) { 475 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 476 bus_dmamap_destroy(sc->sc_dmat, 477 FXP_DSTX(sc, i)->txs_dmamap); 478 } 479 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 480 fail_3: 481 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 482 fail_2: 483 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 484 sizeof(struct fxp_control_data)); 485 fail_1: 486 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 487 fail_0: 488 return; 489 } 490 491 void 492 fxp_mii_initmedia(struct fxp_softc *sc) 493 { 494 int flags; 495 496 sc->sc_flags |= FXPF_MII; 497 498 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 499 sc->sc_mii.mii_readreg = fxp_mdi_read; 500 sc->sc_mii.mii_writereg = fxp_mdi_write; 501 sc->sc_mii.mii_statchg = fxp_statchg; 502 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, fxp_mii_mediachange, 503 fxp_mii_mediastatus); 504 505 flags = MIIF_NOISOLATE; 506 if (sc->sc_rev >= FXP_REV_82558_A4) 507 flags |= MIIF_DOPAUSE; 508 /* 509 * The i82557 wedges if all of its PHYs are isolated! 510 */ 511 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 512 MII_OFFSET_ANY, flags); 513 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 514 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 515 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 516 } else 517 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 518 } 519 520 void 521 fxp_80c24_initmedia(struct fxp_softc *sc) 522 { 523 524 /* 525 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 526 * doesn't have a programming interface of any sort. The 527 * media is sensed automatically based on how the link partner 528 * is configured. This is, in essence, manual configuration. 529 */ 530 aprint_normal("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 531 sc->sc_dev.dv_xname); 532 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 533 fxp_80c24_mediastatus); 534 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 535 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 536 } 537 538 /* 539 * Device shutdown routine. Called at system shutdown after sync. The 540 * main purpose of this routine is to shut off receiver DMA so that 541 * kernel memory doesn't get clobbered during warmboot. 542 */ 543 void 544 fxp_shutdown(void *arg) 545 { 546 struct fxp_softc *sc = arg; 547 548 /* 549 * Since the system's going to halt shortly, don't bother 550 * freeing mbufs. 551 */ 552 fxp_stop(&sc->sc_ethercom.ec_if, 0); 553 } 554 /* 555 * Power handler routine. Called when the system is transitioning 556 * into/out of power save modes. As with fxp_shutdown, the main 557 * purpose of this routine is to shut off receiver DMA so it doesn't 558 * clobber kernel memory at the wrong time. 559 */ 560 void 561 fxp_power(int why, void *arg) 562 { 563 struct fxp_softc *sc = arg; 564 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 565 int s; 566 567 s = splnet(); 568 switch (why) { 569 case PWR_SUSPEND: 570 case PWR_STANDBY: 571 fxp_stop(ifp, 0); 572 break; 573 case PWR_RESUME: 574 if (ifp->if_flags & IFF_UP) 575 fxp_init(ifp); 576 break; 577 case PWR_SOFTSUSPEND: 578 case PWR_SOFTSTANDBY: 579 case PWR_SOFTRESUME: 580 break; 581 } 582 splx(s); 583 } 584 585 /* 586 * Initialize the interface media. 587 */ 588 void 589 fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 590 { 591 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 592 593 /* 594 * Reset to a stable state. 595 */ 596 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 597 DELAY(100); 598 599 sc->sc_eeprom_size = 0; 600 fxp_autosize_eeprom(sc); 601 if (sc->sc_eeprom_size == 0) { 602 aprint_error("%s: failed to detect EEPROM size\n", 603 sc->sc_dev.dv_xname); 604 sc->sc_eeprom_size = 6; /* XXX panic here? */ 605 } 606 #ifdef DEBUG 607 aprint_debug("%s: detected %d word EEPROM\n", 608 sc->sc_dev.dv_xname, 1 << sc->sc_eeprom_size); 609 #endif 610 611 /* 612 * Get info about the primary PHY 613 */ 614 fxp_read_eeprom(sc, &data, 6, 1); 615 sc->phy_primary_device = 616 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 617 618 /* 619 * Read MAC address. 620 */ 621 fxp_read_eeprom(sc, myea, 0, 3); 622 enaddr[0] = myea[0] & 0xff; 623 enaddr[1] = myea[0] >> 8; 624 enaddr[2] = myea[1] & 0xff; 625 enaddr[3] = myea[1] >> 8; 626 enaddr[4] = myea[2] & 0xff; 627 enaddr[5] = myea[2] >> 8; 628 629 /* 630 * Systems based on the ICH2/ICH2-M chip from Intel, as well 631 * as some i82559 designs, have a defect where the chip can 632 * cause a PCI protocol violation if it receives a CU_RESUME 633 * command when it is entering the IDLE state. 634 * 635 * The work-around is to disable Dynamic Standby Mode, so that 636 * the chip never deasserts #CLKRUN, and always remains in the 637 * active state. 638 * 639 * Unfortunately, the only way to disable Dynamic Standby is 640 * to frob an EEPROM setting and reboot (the EEPROM setting 641 * is only consulted when the PCI bus comes out of reset). 642 * 643 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 644 */ 645 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 646 fxp_read_eeprom(sc, &data, 10, 1); 647 if (data & 0x02) { /* STB enable */ 648 aprint_error("%s: WARNING: " 649 "Disabling dynamic standby mode in EEPROM " 650 "to work around a\n", 651 sc->sc_dev.dv_xname); 652 aprint_normal( 653 "%s: WARNING: hardware bug. You must reset " 654 "the system before using this\n", 655 sc->sc_dev.dv_xname); 656 aprint_normal("%s: WARNING: interface.\n", 657 sc->sc_dev.dv_xname); 658 data &= ~0x02; 659 fxp_write_eeprom(sc, &data, 10, 1); 660 aprint_normal("%s: new EEPROM ID: 0x%04x\n", 661 sc->sc_dev.dv_xname, data); 662 fxp_eeprom_update_cksum(sc); 663 } 664 } 665 666 /* Receiver lock-up workaround detection. (FXPF_RECV_WORKAROUND) */ 667 /* Due to false positives we make it conditional on setting link1 */ 668 fxp_read_eeprom(sc, &data, 3, 1); 669 if ((data & 0x03) != 0x03) { 670 aprint_verbose("%s: May need receiver lock-up workaround\n", 671 sc->sc_dev.dv_xname); 672 } 673 } 674 675 static void 676 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 677 { 678 uint16_t reg; 679 int x; 680 681 for (x = 1 << (len - 1); x != 0; x >>= 1) { 682 DELAY(40); 683 if (data & x) 684 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 685 else 686 reg = FXP_EEPROM_EECS; 687 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 688 DELAY(40); 689 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 690 reg | FXP_EEPROM_EESK); 691 DELAY(40); 692 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 693 } 694 DELAY(40); 695 } 696 697 /* 698 * Figure out EEPROM size. 699 * 700 * 559's can have either 64-word or 256-word EEPROMs, the 558 701 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 702 * talks about the existence of 16 to 256 word EEPROMs. 703 * 704 * The only known sizes are 64 and 256, where the 256 version is used 705 * by CardBus cards to store CIS information. 706 * 707 * The address is shifted in msb-to-lsb, and after the last 708 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 709 * after which follows the actual data. We try to detect this zero, by 710 * probing the data-out bit in the EEPROM control register just after 711 * having shifted in a bit. If the bit is zero, we assume we've 712 * shifted enough address bits. The data-out should be tri-state, 713 * before this, which should translate to a logical one. 714 * 715 * Other ways to do this would be to try to read a register with known 716 * contents with a varying number of address bits, but no such 717 * register seem to be available. The high bits of register 10 are 01 718 * on the 558 and 559, but apparently not on the 557. 719 * 720 * The Linux driver computes a checksum on the EEPROM data, but the 721 * value of this checksum is not very well documented. 722 */ 723 724 void 725 fxp_autosize_eeprom(struct fxp_softc *sc) 726 { 727 int x; 728 729 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 730 DELAY(40); 731 732 /* Shift in read opcode. */ 733 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 734 735 /* 736 * Shift in address, wait for the dummy zero following a correct 737 * address shift. 738 */ 739 for (x = 1; x <= 8; x++) { 740 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 741 DELAY(40); 742 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 743 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 744 DELAY(40); 745 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 746 FXP_EEPROM_EEDO) == 0) 747 break; 748 DELAY(40); 749 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 750 DELAY(40); 751 } 752 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 753 DELAY(40); 754 if (x != 6 && x != 8) { 755 #ifdef DEBUG 756 printf("%s: strange EEPROM size (%d)\n", 757 sc->sc_dev.dv_xname, 1 << x); 758 #endif 759 } else 760 sc->sc_eeprom_size = x; 761 } 762 763 /* 764 * Read from the serial EEPROM. Basically, you manually shift in 765 * the read opcode (one bit at a time) and then shift in the address, 766 * and then you shift out the data (all of this one bit at a time). 767 * The word size is 16 bits, so you have to provide the address for 768 * every 16 bits of data. 769 */ 770 void 771 fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 772 { 773 u_int16_t reg; 774 int i, x; 775 776 for (i = 0; i < words; i++) { 777 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 778 779 /* Shift in read opcode. */ 780 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 781 782 /* Shift in address. */ 783 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 784 785 reg = FXP_EEPROM_EECS; 786 data[i] = 0; 787 788 /* Shift out data. */ 789 for (x = 16; x > 0; x--) { 790 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 791 reg | FXP_EEPROM_EESK); 792 DELAY(40); 793 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 794 FXP_EEPROM_EEDO) 795 data[i] |= (1 << (x - 1)); 796 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 797 DELAY(40); 798 } 799 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 800 DELAY(40); 801 } 802 } 803 804 /* 805 * Write data to the serial EEPROM. 806 */ 807 void 808 fxp_write_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 809 { 810 int i, j; 811 812 for (i = 0; i < words; i++) { 813 /* Erase/write enable. */ 814 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 815 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 816 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 817 sc->sc_eeprom_size); 818 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 819 DELAY(4); 820 821 /* Shift in write opcode, address, data. */ 822 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 823 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 824 fxp_eeprom_shiftin(sc, offset, sc->sc_eeprom_size); 825 fxp_eeprom_shiftin(sc, data[i], 16); 826 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 827 DELAY(4); 828 829 /* Wait for the EEPROM to finish up. */ 830 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 831 DELAY(4); 832 for (j = 0; j < 1000; j++) { 833 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 834 FXP_EEPROM_EEDO) 835 break; 836 DELAY(50); 837 } 838 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 839 DELAY(4); 840 841 /* Erase/write disable. */ 842 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 843 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 844 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 845 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 846 DELAY(4); 847 } 848 } 849 850 /* 851 * Update the checksum of the EEPROM. 852 */ 853 void 854 fxp_eeprom_update_cksum(struct fxp_softc *sc) 855 { 856 int i; 857 uint16_t data, cksum; 858 859 cksum = 0; 860 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 861 fxp_read_eeprom(sc, &data, i, 1); 862 cksum += data; 863 } 864 i = (1 << sc->sc_eeprom_size) - 1; 865 cksum = 0xbaba - cksum; 866 fxp_read_eeprom(sc, &data, i, 1); 867 fxp_write_eeprom(sc, &cksum, i, 1); 868 log(LOG_INFO, "%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 869 sc->sc_dev.dv_xname, i, data, cksum); 870 } 871 872 /* 873 * Start packet transmission on the interface. 874 */ 875 void 876 fxp_start(struct ifnet *ifp) 877 { 878 struct fxp_softc *sc = ifp->if_softc; 879 struct mbuf *m0, *m; 880 struct fxp_txdesc *txd; 881 struct fxp_txsoft *txs; 882 bus_dmamap_t dmamap; 883 int error, lasttx, nexttx, opending, seg; 884 885 /* 886 * If we want a re-init, bail out now. 887 */ 888 if (sc->sc_flags & FXPF_WANTINIT) { 889 ifp->if_flags |= IFF_OACTIVE; 890 return; 891 } 892 893 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 894 return; 895 896 /* 897 * Remember the previous txpending and the current lasttx. 898 */ 899 opending = sc->sc_txpending; 900 lasttx = sc->sc_txlast; 901 902 /* 903 * Loop through the send queue, setting up transmit descriptors 904 * until we drain the queue, or use up all available transmit 905 * descriptors. 906 */ 907 for (;;) { 908 struct fxp_tbd *tbdp; 909 int csum_flags; 910 911 /* 912 * Grab a packet off the queue. 913 */ 914 IFQ_POLL(&ifp->if_snd, m0); 915 if (m0 == NULL) 916 break; 917 m = NULL; 918 919 if (sc->sc_txpending == FXP_NTXCB) { 920 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 921 break; 922 } 923 924 /* 925 * Get the next available transmit descriptor. 926 */ 927 nexttx = FXP_NEXTTX(sc->sc_txlast); 928 txd = FXP_CDTX(sc, nexttx); 929 txs = FXP_DSTX(sc, nexttx); 930 dmamap = txs->txs_dmamap; 931 932 /* 933 * Load the DMA map. If this fails, the packet either 934 * didn't fit in the allotted number of frags, or we were 935 * short on resources. In this case, we'll copy and try 936 * again. 937 */ 938 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 939 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 940 MGETHDR(m, M_DONTWAIT, MT_DATA); 941 if (m == NULL) { 942 log(LOG_ERR, "%s: unable to allocate Tx mbuf\n", 943 sc->sc_dev.dv_xname); 944 break; 945 } 946 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 947 if (m0->m_pkthdr.len > MHLEN) { 948 MCLGET(m, M_DONTWAIT); 949 if ((m->m_flags & M_EXT) == 0) { 950 log(LOG_ERR, 951 "%s: unable to allocate Tx " 952 "cluster\n", sc->sc_dev.dv_xname); 953 m_freem(m); 954 break; 955 } 956 } 957 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 958 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 959 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 960 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 961 if (error) { 962 log(LOG_ERR, "%s: unable to load Tx buffer, " 963 "error = %d\n", sc->sc_dev.dv_xname, error); 964 break; 965 } 966 } 967 968 IFQ_DEQUEUE(&ifp->if_snd, m0); 969 csum_flags = m0->m_pkthdr.csum_flags; 970 if (m != NULL) { 971 m_freem(m0); 972 m0 = m; 973 } 974 975 /* Initialize the fraglist. */ 976 tbdp = txd->txd_tbd; 977 if (sc->sc_flags & FXPF_IPCB) 978 tbdp++; 979 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 980 tbdp[seg].tb_addr = 981 htole32(dmamap->dm_segs[seg].ds_addr); 982 tbdp[seg].tb_size = 983 htole32(dmamap->dm_segs[seg].ds_len); 984 } 985 986 /* Sync the DMA map. */ 987 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 988 BUS_DMASYNC_PREWRITE); 989 990 /* 991 * Store a pointer to the packet so we can free it later. 992 */ 993 txs->txs_mbuf = m0; 994 995 /* 996 * Initialize the transmit descriptor. 997 */ 998 /* BIG_ENDIAN: no need to swap to store 0 */ 999 txd->txd_txcb.cb_status = 0; 1000 txd->txd_txcb.cb_command = 1001 sc->sc_txcmd | htole16(FXP_CB_COMMAND_SF); 1002 txd->txd_txcb.tx_threshold = tx_threshold; 1003 txd->txd_txcb.tbd_number = dmamap->dm_nsegs; 1004 1005 KASSERT((csum_flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) == 0); 1006 if (sc->sc_flags & FXPF_IPCB) { 1007 struct fxp_ipcb *ipcb; 1008 /* 1009 * Deal with TCP/IP checksum offload. Note that 1010 * in order for TCP checksum offload to work, 1011 * the pseudo header checksum must have already 1012 * been computed and stored in the checksum field 1013 * in the TCP header. The stack should have 1014 * already done this for us. 1015 */ 1016 ipcb = &txd->txd_u.txdu_ipcb; 1017 memset(ipcb, 0, sizeof(*ipcb)); 1018 /* 1019 * always do hardware parsing. 1020 */ 1021 ipcb->ipcb_ip_activation_high = 1022 FXP_IPCB_HARDWAREPARSING_ENABLE; 1023 /* 1024 * ip checksum offloading. 1025 */ 1026 if (csum_flags & M_CSUM_IPv4) { 1027 ipcb->ipcb_ip_schedule |= 1028 FXP_IPCB_IP_CHECKSUM_ENABLE; 1029 } 1030 /* 1031 * TCP/UDP checksum offloading. 1032 */ 1033 if (csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1034 ipcb->ipcb_ip_schedule |= 1035 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1036 } 1037 1038 /* 1039 * request VLAN tag insertion if needed. 1040 */ 1041 if (sc->sc_ethercom.ec_nvlans != 0) { 1042 struct m_tag *vtag; 1043 1044 vtag = m_tag_find(m0, PACKET_TAG_VLAN, NULL); 1045 if (vtag) { 1046 ipcb->ipcb_vlan_id = 1047 htobe16(*(u_int *)(vtag + 1)); 1048 ipcb->ipcb_ip_activation_high |= 1049 FXP_IPCB_INSERTVLAN_ENABLE; 1050 } 1051 } 1052 } else { 1053 KASSERT((csum_flags & 1054 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) == 0); 1055 } 1056 1057 FXP_CDTXSYNC(sc, nexttx, 1058 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1059 1060 /* Advance the tx pointer. */ 1061 sc->sc_txpending++; 1062 sc->sc_txlast = nexttx; 1063 1064 #if NBPFILTER > 0 1065 /* 1066 * Pass packet to bpf if there is a listener. 1067 */ 1068 if (ifp->if_bpf) 1069 bpf_mtap(ifp->if_bpf, m0); 1070 #endif 1071 } 1072 1073 if (sc->sc_txpending == FXP_NTXCB) { 1074 /* No more slots; notify upper layer. */ 1075 ifp->if_flags |= IFF_OACTIVE; 1076 } 1077 1078 if (sc->sc_txpending != opending) { 1079 /* 1080 * We enqueued packets. If the transmitter was idle, 1081 * reset the txdirty pointer. 1082 */ 1083 if (opending == 0) 1084 sc->sc_txdirty = FXP_NEXTTX(lasttx); 1085 1086 /* 1087 * Cause the chip to interrupt and suspend command 1088 * processing once the last packet we've enqueued 1089 * has been transmitted. 1090 */ 1091 FXP_CDTX(sc, sc->sc_txlast)->txd_txcb.cb_command |= 1092 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 1093 FXP_CDTXSYNC(sc, sc->sc_txlast, 1094 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1095 1096 /* 1097 * The entire packet chain is set up. Clear the suspend bit 1098 * on the command prior to the first packet we set up. 1099 */ 1100 FXP_CDTXSYNC(sc, lasttx, 1101 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1102 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 1103 htole16(~FXP_CB_COMMAND_S); 1104 FXP_CDTXSYNC(sc, lasttx, 1105 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1106 1107 /* 1108 * Issue a Resume command in case the chip was suspended. 1109 */ 1110 fxp_scb_wait(sc); 1111 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1112 1113 /* Set a watchdog timer in case the chip flakes out. */ 1114 ifp->if_timer = 5; 1115 } 1116 } 1117 1118 /* 1119 * Process interface interrupts. 1120 */ 1121 int 1122 fxp_intr(void *arg) 1123 { 1124 struct fxp_softc *sc = arg; 1125 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1126 bus_dmamap_t rxmap; 1127 int claimed = 0; 1128 u_int8_t statack; 1129 1130 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0 || sc->sc_enabled == 0) 1131 return (0); 1132 /* 1133 * If the interface isn't running, don't try to 1134 * service the interrupt.. just ack it and bail. 1135 */ 1136 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1137 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1138 if (statack) { 1139 claimed = 1; 1140 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1141 } 1142 return (claimed); 1143 } 1144 1145 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1146 claimed = 1; 1147 1148 /* 1149 * First ACK all the interrupts in this pass. 1150 */ 1151 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1152 1153 /* 1154 * Process receiver interrupts. If a no-resource (RNR) 1155 * condition exists, get whatever packets we can and 1156 * re-start the receiver. 1157 */ 1158 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1159 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1160 fxp_rxintr(sc); 1161 } 1162 1163 if (statack & FXP_SCB_STATACK_RNR) { 1164 fxp_scb_wait(sc); 1165 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_ABORT); 1166 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1167 fxp_scb_wait(sc); 1168 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1169 rxmap->dm_segs[0].ds_addr + 1170 RFA_ALIGNMENT_FUDGE); 1171 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1172 } 1173 1174 /* 1175 * Free any finished transmit mbuf chains. 1176 */ 1177 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1178 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1179 fxp_txintr(sc); 1180 1181 /* 1182 * Try to get more packets going. 1183 */ 1184 fxp_start(ifp); 1185 1186 if (sc->sc_txpending == 0) { 1187 /* 1188 * If we want a re-init, do that now. 1189 */ 1190 if (sc->sc_flags & FXPF_WANTINIT) 1191 (void) fxp_init(ifp); 1192 } 1193 } 1194 } 1195 1196 #if NRND > 0 1197 if (claimed) 1198 rnd_add_uint32(&sc->rnd_source, statack); 1199 #endif 1200 return (claimed); 1201 } 1202 1203 /* 1204 * Handle transmit completion interrupts. 1205 */ 1206 void 1207 fxp_txintr(struct fxp_softc *sc) 1208 { 1209 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1210 struct fxp_txdesc *txd; 1211 struct fxp_txsoft *txs; 1212 int i; 1213 u_int16_t txstat; 1214 1215 ifp->if_flags &= ~IFF_OACTIVE; 1216 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1217 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1218 txd = FXP_CDTX(sc, i); 1219 txs = FXP_DSTX(sc, i); 1220 1221 FXP_CDTXSYNC(sc, i, 1222 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1223 1224 txstat = le16toh(txd->txd_txcb.cb_status); 1225 1226 if ((txstat & FXP_CB_STATUS_C) == 0) 1227 break; 1228 1229 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1230 0, txs->txs_dmamap->dm_mapsize, 1231 BUS_DMASYNC_POSTWRITE); 1232 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1233 m_freem(txs->txs_mbuf); 1234 txs->txs_mbuf = NULL; 1235 } 1236 1237 /* Update the dirty transmit buffer pointer. */ 1238 sc->sc_txdirty = i; 1239 1240 /* 1241 * Cancel the watchdog timer if there are no pending 1242 * transmissions. 1243 */ 1244 if (sc->sc_txpending == 0) 1245 ifp->if_timer = 0; 1246 } 1247 1248 /* 1249 * fxp_rx_hwcksum: check status of H/W offloading for received packets. 1250 */ 1251 1252 int 1253 fxp_rx_hwcksum(struct mbuf *m, const struct fxp_rfa *rfa) 1254 { 1255 u_int16_t rxparsestat; 1256 u_int16_t csum_stat; 1257 u_int32_t csum_data; 1258 int csum_flags; 1259 1260 /* 1261 * check VLAN tag stripping. 1262 */ 1263 1264 if (rfa->rfa_status & htole16(FXP_RFA_STATUS_VLAN)) { 1265 struct m_tag *vtag; 1266 1267 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), M_NOWAIT); 1268 if (vtag == NULL) 1269 return ENOMEM; 1270 *(u_int *)(vtag + 1) = be16toh(rfa->vlan_id); 1271 m_tag_prepend(m, vtag); 1272 } 1273 1274 /* 1275 * check H/W Checksumming. 1276 */ 1277 1278 csum_stat = le16toh(rfa->cksum_stat); 1279 rxparsestat = le16toh(rfa->rx_parse_stat); 1280 if (!(rfa->rfa_status & htole16(FXP_RFA_STATUS_PARSE))) 1281 return 0; 1282 1283 csum_flags = 0; 1284 csum_data = 0; 1285 1286 if (csum_stat & FXP_RFDX_CS_IP_CSUM_BIT_VALID) { 1287 csum_flags = M_CSUM_IPv4; 1288 if (!(csum_stat & FXP_RFDX_CS_IP_CSUM_VALID)) 1289 csum_flags |= M_CSUM_IPv4_BAD; 1290 } 1291 1292 if (csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) { 1293 csum_flags |= (M_CSUM_TCPv4|M_CSUM_UDPv4); /* XXX */ 1294 if (!(csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) 1295 csum_flags |= M_CSUM_TCP_UDP_BAD; 1296 } 1297 1298 m->m_pkthdr.csum_flags = csum_flags; 1299 m->m_pkthdr.csum_data = csum_data; 1300 1301 return 0; 1302 } 1303 1304 /* 1305 * Handle receive interrupts. 1306 */ 1307 void 1308 fxp_rxintr(struct fxp_softc *sc) 1309 { 1310 struct ethercom *ec = &sc->sc_ethercom; 1311 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1312 struct mbuf *m, *m0; 1313 bus_dmamap_t rxmap; 1314 struct fxp_rfa *rfa; 1315 u_int16_t len, rxstat; 1316 1317 for (;;) { 1318 m = sc->sc_rxq.ifq_head; 1319 rfa = FXP_MTORFA(m); 1320 rxmap = M_GETCTX(m, bus_dmamap_t); 1321 1322 FXP_RFASYNC(sc, m, 1323 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1324 1325 rxstat = le16toh(rfa->rfa_status); 1326 1327 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1328 /* 1329 * We have processed all of the 1330 * receive buffers. 1331 */ 1332 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1333 return; 1334 } 1335 1336 IF_DEQUEUE(&sc->sc_rxq, m); 1337 1338 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1339 1340 len = le16toh(rfa->actual_size) & 1341 (m->m_ext.ext_size - 1); 1342 1343 if (len < sizeof(struct ether_header)) { 1344 /* 1345 * Runt packet; drop it now. 1346 */ 1347 FXP_INIT_RFABUF(sc, m); 1348 continue; 1349 } 1350 1351 /* 1352 * If support for 802.1Q VLAN sized frames is 1353 * enabled, we need to do some additional error 1354 * checking (as we are saving bad frames, in 1355 * order to receive the larger ones). 1356 */ 1357 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1358 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1359 FXP_RFA_STATUS_RNR| 1360 FXP_RFA_STATUS_ALIGN| 1361 FXP_RFA_STATUS_CRC)) != 0) { 1362 FXP_INIT_RFABUF(sc, m); 1363 continue; 1364 } 1365 1366 /* Do checksum checking. */ 1367 m->m_pkthdr.csum_flags = 0; 1368 if (sc->sc_flags & FXPF_EXT_RFA) 1369 if (fxp_rx_hwcksum(m, rfa)) 1370 goto dropit; 1371 1372 /* 1373 * If the packet is small enough to fit in a 1374 * single header mbuf, allocate one and copy 1375 * the data into it. This greatly reduces 1376 * memory consumption when we receive lots 1377 * of small packets. 1378 * 1379 * Otherwise, we add a new buffer to the receive 1380 * chain. If this fails, we drop the packet and 1381 * recycle the old buffer. 1382 */ 1383 if (fxp_copy_small != 0 && len <= MHLEN) { 1384 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1385 if (m0 == NULL) 1386 goto dropit; 1387 MCLAIM(m0, &sc->sc_ethercom.ec_rx_mowner); 1388 memcpy(mtod(m0, caddr_t), 1389 mtod(m, caddr_t), len); 1390 m0->m_pkthdr.csum_flags = m->m_pkthdr.csum_flags; 1391 m0->m_pkthdr.csum_data = m->m_pkthdr.csum_data; 1392 FXP_INIT_RFABUF(sc, m); 1393 m = m0; 1394 } else { 1395 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1396 dropit: 1397 ifp->if_ierrors++; 1398 FXP_INIT_RFABUF(sc, m); 1399 continue; 1400 } 1401 } 1402 1403 m->m_pkthdr.rcvif = ifp; 1404 m->m_pkthdr.len = m->m_len = len; 1405 1406 #if NBPFILTER > 0 1407 /* 1408 * Pass this up to any BPF listeners, but only 1409 * pass it up the stack it its for us. 1410 */ 1411 if (ifp->if_bpf) 1412 bpf_mtap(ifp->if_bpf, m); 1413 #endif 1414 1415 /* Pass it on. */ 1416 (*ifp->if_input)(ifp, m); 1417 } 1418 } 1419 1420 /* 1421 * Update packet in/out/collision statistics. The i82557 doesn't 1422 * allow you to access these counters without doing a fairly 1423 * expensive DMA to get _all_ of the statistics it maintains, so 1424 * we do this operation here only once per second. The statistics 1425 * counters in the kernel are updated from the previous dump-stats 1426 * DMA and then a new dump-stats DMA is started. The on-chip 1427 * counters are zeroed when the DMA completes. If we can't start 1428 * the DMA immediately, we don't wait - we just prepare to read 1429 * them again next time. 1430 */ 1431 void 1432 fxp_tick(void *arg) 1433 { 1434 struct fxp_softc *sc = arg; 1435 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1436 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1437 int s; 1438 1439 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1440 return; 1441 1442 s = splnet(); 1443 1444 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1445 1446 ifp->if_opackets += le32toh(sp->tx_good); 1447 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1448 if (sp->rx_good) { 1449 ifp->if_ipackets += le32toh(sp->rx_good); 1450 sc->sc_rxidle = 0; 1451 } else if (sc->sc_flags & FXPF_RECV_WORKAROUND) { 1452 sc->sc_rxidle++; 1453 } 1454 ifp->if_ierrors += 1455 le32toh(sp->rx_crc_errors) + 1456 le32toh(sp->rx_alignment_errors) + 1457 le32toh(sp->rx_rnr_errors) + 1458 le32toh(sp->rx_overrun_errors); 1459 /* 1460 * If any transmit underruns occurred, bump up the transmit 1461 * threshold by another 512 bytes (64 * 8). 1462 */ 1463 if (sp->tx_underruns) { 1464 ifp->if_oerrors += le32toh(sp->tx_underruns); 1465 if (tx_threshold < 192) 1466 tx_threshold += 64; 1467 } 1468 #ifdef FXP_EVENT_COUNTERS 1469 if (sc->sc_rev >= FXP_REV_82558_A4) { 1470 sc->sc_ev_txpause.ev_count += sp->tx_pauseframes; 1471 sc->sc_ev_rxpause.ev_count += sp->rx_pauseframes; 1472 } 1473 #endif 1474 1475 /* 1476 * If we haven't received any packets in FXP_MAX_RX_IDLE seconds, 1477 * then assume the receiver has locked up and attempt to clear 1478 * the condition by reprogramming the multicast filter (actually, 1479 * resetting the interface). This is a work-around for a bug in 1480 * the 82557 where the receiver locks up if it gets certain types 1481 * of garbage in the synchronization bits prior to the packet header. 1482 * This bug is supposed to only occur in 10Mbps mode, but has been 1483 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1484 * speed transition). 1485 */ 1486 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1487 (void) fxp_init(ifp); 1488 splx(s); 1489 return; 1490 } 1491 /* 1492 * If there is no pending command, start another stats 1493 * dump. Otherwise punt for now. 1494 */ 1495 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1496 /* 1497 * Start another stats dump. 1498 */ 1499 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1500 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1501 } else { 1502 /* 1503 * A previous command is still waiting to be accepted. 1504 * Just zero our copy of the stats and wait for the 1505 * next timer event to update them. 1506 */ 1507 /* BIG_ENDIAN: no swap required to store 0 */ 1508 sp->tx_good = 0; 1509 sp->tx_underruns = 0; 1510 sp->tx_total_collisions = 0; 1511 1512 sp->rx_good = 0; 1513 sp->rx_crc_errors = 0; 1514 sp->rx_alignment_errors = 0; 1515 sp->rx_rnr_errors = 0; 1516 sp->rx_overrun_errors = 0; 1517 if (sc->sc_rev >= FXP_REV_82558_A4) { 1518 sp->tx_pauseframes = 0; 1519 sp->rx_pauseframes = 0; 1520 } 1521 } 1522 1523 if (sc->sc_flags & FXPF_MII) { 1524 /* Tick the MII clock. */ 1525 mii_tick(&sc->sc_mii); 1526 } 1527 1528 splx(s); 1529 1530 /* 1531 * Schedule another timeout one second from now. 1532 */ 1533 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1534 } 1535 1536 /* 1537 * Drain the receive queue. 1538 */ 1539 void 1540 fxp_rxdrain(struct fxp_softc *sc) 1541 { 1542 bus_dmamap_t rxmap; 1543 struct mbuf *m; 1544 1545 for (;;) { 1546 IF_DEQUEUE(&sc->sc_rxq, m); 1547 if (m == NULL) 1548 break; 1549 rxmap = M_GETCTX(m, bus_dmamap_t); 1550 bus_dmamap_unload(sc->sc_dmat, rxmap); 1551 FXP_RXMAP_PUT(sc, rxmap); 1552 m_freem(m); 1553 } 1554 } 1555 1556 /* 1557 * Stop the interface. Cancels the statistics updater and resets 1558 * the interface. 1559 */ 1560 void 1561 fxp_stop(struct ifnet *ifp, int disable) 1562 { 1563 struct fxp_softc *sc = ifp->if_softc; 1564 struct fxp_txsoft *txs; 1565 int i; 1566 1567 /* 1568 * Turn down interface (done early to avoid bad interactions 1569 * between panics, shutdown hooks, and the watchdog timer) 1570 */ 1571 ifp->if_timer = 0; 1572 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1573 1574 /* 1575 * Cancel stats updater. 1576 */ 1577 callout_stop(&sc->sc_callout); 1578 if (sc->sc_flags & FXPF_MII) { 1579 /* Down the MII. */ 1580 mii_down(&sc->sc_mii); 1581 } 1582 1583 /* 1584 * Issue software reset. This unloads any microcode that 1585 * might already be loaded. 1586 */ 1587 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1588 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1589 DELAY(50); 1590 1591 /* 1592 * Release any xmit buffers. 1593 */ 1594 for (i = 0; i < FXP_NTXCB; i++) { 1595 txs = FXP_DSTX(sc, i); 1596 if (txs->txs_mbuf != NULL) { 1597 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1598 m_freem(txs->txs_mbuf); 1599 txs->txs_mbuf = NULL; 1600 } 1601 } 1602 sc->sc_txpending = 0; 1603 1604 if (disable) { 1605 fxp_rxdrain(sc); 1606 fxp_disable(sc); 1607 } 1608 1609 } 1610 1611 /* 1612 * Watchdog/transmission transmit timeout handler. Called when a 1613 * transmission is started on the interface, but no interrupt is 1614 * received before the timeout. This usually indicates that the 1615 * card has wedged for some reason. 1616 */ 1617 void 1618 fxp_watchdog(struct ifnet *ifp) 1619 { 1620 struct fxp_softc *sc = ifp->if_softc; 1621 1622 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1623 ifp->if_oerrors++; 1624 1625 (void) fxp_init(ifp); 1626 } 1627 1628 /* 1629 * Initialize the interface. Must be called at splnet(). 1630 */ 1631 int 1632 fxp_init(struct ifnet *ifp) 1633 { 1634 struct fxp_softc *sc = ifp->if_softc; 1635 struct fxp_cb_config *cbp; 1636 struct fxp_cb_ias *cb_ias; 1637 struct fxp_txdesc *txd; 1638 bus_dmamap_t rxmap; 1639 int i, prm, save_bf, lrxen, vlan_drop, allm, error = 0; 1640 1641 if ((error = fxp_enable(sc)) != 0) 1642 goto out; 1643 1644 /* 1645 * Cancel any pending I/O 1646 */ 1647 fxp_stop(ifp, 0); 1648 1649 /* 1650 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1651 * flag, and this prevents the MII from detaching resulting in 1652 * a panic. The flags field should perhaps be split in runtime 1653 * flags and more static information. For now, just clear the 1654 * only other flag set. 1655 */ 1656 1657 sc->sc_flags &= ~FXPF_WANTINIT; 1658 1659 /* 1660 * Initialize base of CBL and RFA memory. Loading with zero 1661 * sets it up for regular linear addressing. 1662 */ 1663 fxp_scb_wait(sc); 1664 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1665 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1666 1667 fxp_scb_wait(sc); 1668 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1669 1670 /* 1671 * Initialize the multicast filter. Do this now, since we might 1672 * have to setup the config block differently. 1673 */ 1674 fxp_mc_setup(sc); 1675 1676 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1677 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1678 1679 /* 1680 * In order to support receiving 802.1Q VLAN frames, we have to 1681 * enable "save bad frames", since they are 4 bytes larger than 1682 * the normal Ethernet maximum frame length. On i82558 and later, 1683 * we have a better mechanism for this. 1684 */ 1685 save_bf = 0; 1686 lrxen = 0; 1687 vlan_drop = 0; 1688 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1689 if (sc->sc_rev < FXP_REV_82558_A4) 1690 save_bf = 1; 1691 else 1692 lrxen = 1; 1693 if (sc->sc_rev >= FXP_REV_82550) 1694 vlan_drop = 1; 1695 } 1696 1697 /* 1698 * Initialize base of dump-stats buffer. 1699 */ 1700 fxp_scb_wait(sc); 1701 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1702 sc->sc_cddma + FXP_CDSTATSOFF); 1703 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1704 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1705 1706 cbp = &sc->sc_control_data->fcd_configcb; 1707 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1708 1709 /* 1710 * Load microcode for this controller. 1711 */ 1712 fxp_load_ucode(sc); 1713 1714 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK1)) 1715 sc->sc_flags |= FXPF_RECV_WORKAROUND; 1716 else 1717 sc->sc_flags &= ~FXPF_RECV_WORKAROUND; 1718 1719 /* 1720 * This copy is kind of disgusting, but there are a bunch of must be 1721 * zero and must be one bits in this structure and this is the easiest 1722 * way to initialize them all to proper values. 1723 */ 1724 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1725 1726 /* BIG_ENDIAN: no need to swap to store 0 */ 1727 cbp->cb_status = 0; 1728 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1729 FXP_CB_COMMAND_EL); 1730 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1731 cbp->link_addr = 0xffffffff; /* (no) next command */ 1732 /* bytes in config block */ 1733 cbp->byte_count = (sc->sc_flags & FXPF_EXT_RFA) ? 1734 FXP_EXT_CONFIG_LEN : FXP_CONFIG_LEN; 1735 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1736 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1737 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1738 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1739 cbp->type_enable = 0; /* actually reserved */ 1740 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1741 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1742 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1743 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1744 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1745 cbp->late_scb = 0; /* (don't) defer SCB update */ 1746 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1747 cbp->ci_int = 1; /* interrupt on CU idle */ 1748 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1749 cbp->ext_stats_dis = 1; /* disable extended counters */ 1750 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1751 cbp->save_bf = save_bf;/* save bad frames */ 1752 cbp->disc_short_rx = !prm; /* discard short packets */ 1753 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1754 cbp->ext_rfa = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1755 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1756 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1757 /* interface mode */ 1758 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1759 cbp->csma_dis = 0; /* (don't) disable link */ 1760 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1761 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1762 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1763 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1764 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1765 cbp->nsai = 1; /* (don't) disable source addr insert */ 1766 cbp->preamble_length = 2; /* (7 byte) preamble */ 1767 cbp->loopback = 0; /* (don't) loopback */ 1768 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1769 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1770 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1771 cbp->promiscuous = prm; /* promiscuous mode */ 1772 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1773 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1774 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1775 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1776 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1777 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1778 cbp->padding = 1; /* (do) pad short tx packets */ 1779 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1780 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1781 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1782 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1783 /* must set wake_en in PMCSR also */ 1784 cbp->force_fdx = 0; /* (don't) force full duplex */ 1785 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1786 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1787 cbp->mc_all = allm; /* accept all multicasts */ 1788 cbp->ext_rx_mode = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1789 cbp->vlan_drop_en = vlan_drop; 1790 1791 if (sc->sc_rev < FXP_REV_82558_A4) { 1792 /* 1793 * The i82557 has no hardware flow control, the values 1794 * here are the defaults for the chip. 1795 */ 1796 cbp->fc_delay_lsb = 0; 1797 cbp->fc_delay_msb = 0x40; 1798 cbp->pri_fc_thresh = 3; 1799 cbp->tx_fc_dis = 0; 1800 cbp->rx_fc_restop = 0; 1801 cbp->rx_fc_restart = 0; 1802 cbp->fc_filter = 0; 1803 cbp->pri_fc_loc = 1; 1804 } else { 1805 cbp->fc_delay_lsb = 0x1f; 1806 cbp->fc_delay_msb = 0x01; 1807 cbp->pri_fc_thresh = 3; 1808 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1809 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1810 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1811 cbp->fc_filter = !prm; /* drop FC frames to host */ 1812 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1813 cbp->ext_stats_dis = 0; /* enable extended stats */ 1814 } 1815 1816 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1817 1818 /* 1819 * Start the config command/DMA. 1820 */ 1821 fxp_scb_wait(sc); 1822 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1823 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1824 /* ...and wait for it to complete. */ 1825 i = 1000; 1826 do { 1827 FXP_CDCONFIGSYNC(sc, 1828 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1829 DELAY(1); 1830 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1831 if (i == 0) { 1832 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1833 sc->sc_dev.dv_xname, __LINE__); 1834 return (ETIMEDOUT); 1835 } 1836 1837 /* 1838 * Initialize the station address. 1839 */ 1840 cb_ias = &sc->sc_control_data->fcd_iascb; 1841 /* BIG_ENDIAN: no need to swap to store 0 */ 1842 cb_ias->cb_status = 0; 1843 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1844 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1845 cb_ias->link_addr = 0xffffffff; 1846 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1847 1848 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1849 1850 /* 1851 * Start the IAS (Individual Address Setup) command/DMA. 1852 */ 1853 fxp_scb_wait(sc); 1854 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1855 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1856 /* ...and wait for it to complete. */ 1857 i = 1000; 1858 do { 1859 FXP_CDIASSYNC(sc, 1860 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1861 DELAY(1); 1862 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1863 if (i == 0) { 1864 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1865 sc->sc_dev.dv_xname, __LINE__); 1866 return (ETIMEDOUT); 1867 } 1868 1869 /* 1870 * Initialize the transmit descriptor ring. txlast is initialized 1871 * to the end of the list so that it will wrap around to the first 1872 * descriptor when the first packet is transmitted. 1873 */ 1874 for (i = 0; i < FXP_NTXCB; i++) { 1875 txd = FXP_CDTX(sc, i); 1876 memset(txd, 0, sizeof(*txd)); 1877 txd->txd_txcb.cb_command = 1878 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1879 txd->txd_txcb.link_addr = 1880 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1881 if (sc->sc_flags & FXPF_EXT_TXCB) 1882 txd->txd_txcb.tbd_array_addr = 1883 htole32(FXP_CDTBDADDR(sc, i) + 1884 (2 * sizeof(struct fxp_tbd))); 1885 else 1886 txd->txd_txcb.tbd_array_addr = 1887 htole32(FXP_CDTBDADDR(sc, i)); 1888 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1889 } 1890 sc->sc_txpending = 0; 1891 sc->sc_txdirty = 0; 1892 sc->sc_txlast = FXP_NTXCB - 1; 1893 1894 /* 1895 * Initialize the receive buffer list. 1896 */ 1897 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1898 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1899 rxmap = FXP_RXMAP_GET(sc); 1900 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1901 log(LOG_ERR, "%s: unable to allocate or map rx " 1902 "buffer %d, error = %d\n", 1903 sc->sc_dev.dv_xname, 1904 sc->sc_rxq.ifq_len, error); 1905 /* 1906 * XXX Should attempt to run with fewer receive 1907 * XXX buffers instead of just failing. 1908 */ 1909 FXP_RXMAP_PUT(sc, rxmap); 1910 fxp_rxdrain(sc); 1911 goto out; 1912 } 1913 } 1914 sc->sc_rxidle = 0; 1915 1916 /* 1917 * Give the transmit ring to the chip. We do this by pointing 1918 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1919 * issuing a start command. It will execute the NOP and then 1920 * suspend, pointing at the first descriptor. 1921 */ 1922 fxp_scb_wait(sc); 1923 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1924 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1925 1926 /* 1927 * Initialize receiver buffer area - RFA. 1928 */ 1929 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1930 fxp_scb_wait(sc); 1931 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1932 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1933 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1934 1935 if (sc->sc_flags & FXPF_MII) { 1936 /* 1937 * Set current media. 1938 */ 1939 mii_mediachg(&sc->sc_mii); 1940 } 1941 1942 /* 1943 * ...all done! 1944 */ 1945 ifp->if_flags |= IFF_RUNNING; 1946 ifp->if_flags &= ~IFF_OACTIVE; 1947 1948 /* 1949 * Start the one second timer. 1950 */ 1951 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1952 1953 /* 1954 * Attempt to start output on the interface. 1955 */ 1956 fxp_start(ifp); 1957 1958 out: 1959 if (error) { 1960 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1961 ifp->if_timer = 0; 1962 log(LOG_ERR, "%s: interface not running\n", 1963 sc->sc_dev.dv_xname); 1964 } 1965 return (error); 1966 } 1967 1968 /* 1969 * Change media according to request. 1970 */ 1971 int 1972 fxp_mii_mediachange(struct ifnet *ifp) 1973 { 1974 struct fxp_softc *sc = ifp->if_softc; 1975 1976 if (ifp->if_flags & IFF_UP) 1977 mii_mediachg(&sc->sc_mii); 1978 return (0); 1979 } 1980 1981 /* 1982 * Notify the world which media we're using. 1983 */ 1984 void 1985 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1986 { 1987 struct fxp_softc *sc = ifp->if_softc; 1988 1989 if (sc->sc_enabled == 0) { 1990 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1991 ifmr->ifm_status = 0; 1992 return; 1993 } 1994 1995 mii_pollstat(&sc->sc_mii); 1996 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1997 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1998 1999 /* 2000 * XXX Flow control is always turned on if the chip supports 2001 * XXX it; we can't easily control it dynamically, since it 2002 * XXX requires sending a setup packet. 2003 */ 2004 if (sc->sc_rev >= FXP_REV_82558_A4) 2005 ifmr->ifm_active |= IFM_FLOW|IFM_ETH_TXPAUSE|IFM_ETH_RXPAUSE; 2006 } 2007 2008 int 2009 fxp_80c24_mediachange(struct ifnet *ifp) 2010 { 2011 2012 /* Nothing to do here. */ 2013 return (0); 2014 } 2015 2016 void 2017 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2018 { 2019 struct fxp_softc *sc = ifp->if_softc; 2020 2021 /* 2022 * Media is currently-selected media. We cannot determine 2023 * the link status. 2024 */ 2025 ifmr->ifm_status = 0; 2026 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 2027 } 2028 2029 /* 2030 * Add a buffer to the end of the RFA buffer list. 2031 * Return 0 if successful, error code on failure. 2032 * 2033 * The RFA struct is stuck at the beginning of mbuf cluster and the 2034 * data pointer is fixed up to point just past it. 2035 */ 2036 int 2037 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 2038 { 2039 struct mbuf *m; 2040 int error; 2041 2042 MGETHDR(m, M_DONTWAIT, MT_DATA); 2043 if (m == NULL) 2044 return (ENOBUFS); 2045 2046 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2047 MCLGET(m, M_DONTWAIT); 2048 if ((m->m_flags & M_EXT) == 0) { 2049 m_freem(m); 2050 return (ENOBUFS); 2051 } 2052 2053 if (unload) 2054 bus_dmamap_unload(sc->sc_dmat, rxmap); 2055 2056 M_SETCTX(m, rxmap); 2057 2058 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2059 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, 2060 BUS_DMA_READ|BUS_DMA_NOWAIT); 2061 if (error) { 2062 /* XXX XXX XXX */ 2063 printf("%s: can't load rx DMA map %d, error = %d\n", 2064 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 2065 panic("fxp_add_rfabuf"); 2066 } 2067 2068 FXP_INIT_RFABUF(sc, m); 2069 2070 return (0); 2071 } 2072 2073 int 2074 fxp_mdi_read(struct device *self, int phy, int reg) 2075 { 2076 struct fxp_softc *sc = (struct fxp_softc *)self; 2077 int count = 10000; 2078 int value; 2079 2080 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2081 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2082 2083 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 2084 0x10000000) == 0 && count--) 2085 DELAY(10); 2086 2087 if (count <= 0) 2088 log(LOG_WARNING, 2089 "%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 2090 2091 return (value & 0xffff); 2092 } 2093 2094 void 2095 fxp_statchg(struct device *self) 2096 { 2097 2098 /* Nothing to do. */ 2099 } 2100 2101 void 2102 fxp_mdi_write(struct device *self, int phy, int reg, int value) 2103 { 2104 struct fxp_softc *sc = (struct fxp_softc *)self; 2105 int count = 10000; 2106 2107 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2108 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2109 (value & 0xffff)); 2110 2111 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2112 count--) 2113 DELAY(10); 2114 2115 if (count <= 0) 2116 log(LOG_WARNING, 2117 "%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 2118 } 2119 2120 int 2121 fxp_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2122 { 2123 struct fxp_softc *sc = ifp->if_softc; 2124 struct ifreq *ifr = (struct ifreq *)data; 2125 int s, error; 2126 2127 s = splnet(); 2128 2129 switch (cmd) { 2130 case SIOCSIFMEDIA: 2131 case SIOCGIFMEDIA: 2132 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2133 break; 2134 2135 default: 2136 error = ether_ioctl(ifp, cmd, data); 2137 if (error == ENETRESET) { 2138 if (ifp->if_flags & IFF_RUNNING) { 2139 /* 2140 * Multicast list has changed; set the 2141 * hardware filter accordingly. 2142 */ 2143 if (sc->sc_txpending) { 2144 sc->sc_flags |= FXPF_WANTINIT; 2145 error = 0; 2146 } else 2147 error = fxp_init(ifp); 2148 } else 2149 error = 0; 2150 } 2151 break; 2152 } 2153 2154 /* Try to get more packets going. */ 2155 if (sc->sc_enabled) 2156 fxp_start(ifp); 2157 2158 splx(s); 2159 return (error); 2160 } 2161 2162 /* 2163 * Program the multicast filter. 2164 * 2165 * This function must be called at splnet(). 2166 */ 2167 void 2168 fxp_mc_setup(struct fxp_softc *sc) 2169 { 2170 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 2171 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2172 struct ethercom *ec = &sc->sc_ethercom; 2173 struct ether_multi *enm; 2174 struct ether_multistep step; 2175 int count, nmcasts; 2176 2177 #ifdef DIAGNOSTIC 2178 if (sc->sc_txpending) 2179 panic("fxp_mc_setup: pending transmissions"); 2180 #endif 2181 2182 ifp->if_flags &= ~IFF_ALLMULTI; 2183 2184 /* 2185 * Initialize multicast setup descriptor. 2186 */ 2187 nmcasts = 0; 2188 ETHER_FIRST_MULTI(step, ec, enm); 2189 while (enm != NULL) { 2190 /* 2191 * Check for too many multicast addresses or if we're 2192 * listening to a range. Either way, we simply have 2193 * to accept all multicasts. 2194 */ 2195 if (nmcasts >= MAXMCADDR || 2196 memcmp(enm->enm_addrlo, enm->enm_addrhi, 2197 ETHER_ADDR_LEN) != 0) { 2198 /* 2199 * Callers of this function must do the 2200 * right thing with this. If we're called 2201 * from outside fxp_init(), the caller must 2202 * detect if the state if IFF_ALLMULTI changes. 2203 * If it does, the caller must then call 2204 * fxp_init(), since allmulti is handled by 2205 * the config block. 2206 */ 2207 ifp->if_flags |= IFF_ALLMULTI; 2208 return; 2209 } 2210 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 2211 ETHER_ADDR_LEN); 2212 nmcasts++; 2213 ETHER_NEXT_MULTI(step, enm); 2214 } 2215 2216 /* BIG_ENDIAN: no need to swap to store 0 */ 2217 mcsp->cb_status = 0; 2218 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2219 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2220 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2221 2222 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2223 2224 /* 2225 * Wait until the command unit is not active. This should never 2226 * happen since nothing is queued, but make sure anyway. 2227 */ 2228 count = 100; 2229 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2230 FXP_SCB_CUS_ACTIVE && --count) 2231 DELAY(1); 2232 if (count == 0) { 2233 log(LOG_WARNING, "%s: line %d: command queue timeout\n", 2234 sc->sc_dev.dv_xname, __LINE__); 2235 return; 2236 } 2237 2238 /* 2239 * Start the multicast setup command/DMA. 2240 */ 2241 fxp_scb_wait(sc); 2242 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2243 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2244 2245 /* ...and wait for it to complete. */ 2246 count = 1000; 2247 do { 2248 FXP_CDMCSSYNC(sc, 2249 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2250 DELAY(1); 2251 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2252 if (count == 0) { 2253 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 2254 sc->sc_dev.dv_xname, __LINE__); 2255 return; 2256 } 2257 } 2258 2259 static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2260 static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2261 static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2262 static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2263 static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2264 static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2265 2266 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2267 2268 static const struct ucode { 2269 int32_t revision; 2270 const uint32_t *ucode; 2271 size_t length; 2272 uint16_t int_delay_offset; 2273 uint16_t bundle_max_offset; 2274 } ucode_table[] = { 2275 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2276 D101_CPUSAVER_DWORD, 0 }, 2277 2278 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2279 D101_CPUSAVER_DWORD, 0 }, 2280 2281 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2282 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2283 2284 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2285 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2286 2287 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2288 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2289 2290 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2291 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2292 2293 { 0, NULL, 0, 0, 0 } 2294 }; 2295 2296 void 2297 fxp_load_ucode(struct fxp_softc *sc) 2298 { 2299 const struct ucode *uc; 2300 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2301 int count, i; 2302 2303 if (sc->sc_flags & FXPF_UCODE_LOADED) 2304 return; 2305 2306 /* 2307 * Only load the uCode if the user has requested that 2308 * we do so. 2309 */ 2310 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2311 sc->sc_int_delay = 0; 2312 sc->sc_bundle_max = 0; 2313 return; 2314 } 2315 2316 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2317 if (sc->sc_rev == uc->revision) 2318 break; 2319 } 2320 if (uc->ucode == NULL) 2321 return; 2322 2323 /* BIG ENDIAN: no need to swap to store 0 */ 2324 cbp->cb_status = 0; 2325 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2326 cbp->link_addr = 0xffffffff; /* (no) next command */ 2327 for (i = 0; i < uc->length; i++) 2328 cbp->ucode[i] = htole32(uc->ucode[i]); 2329 2330 if (uc->int_delay_offset) 2331 *(uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2332 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2333 2334 if (uc->bundle_max_offset) 2335 *(uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2336 htole16(fxp_bundle_max); 2337 2338 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2339 2340 /* 2341 * Download the uCode to the chip. 2342 */ 2343 fxp_scb_wait(sc); 2344 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2345 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2346 2347 /* ...and wait for it to complete. */ 2348 count = 10000; 2349 do { 2350 FXP_CDUCODESYNC(sc, 2351 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2352 DELAY(2); 2353 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2354 if (count == 0) { 2355 sc->sc_int_delay = 0; 2356 sc->sc_bundle_max = 0; 2357 log(LOG_WARNING, "%s: timeout loading microcode\n", 2358 sc->sc_dev.dv_xname); 2359 return; 2360 } 2361 2362 if (sc->sc_int_delay != fxp_int_delay || 2363 sc->sc_bundle_max != fxp_bundle_max) { 2364 sc->sc_int_delay = fxp_int_delay; 2365 sc->sc_bundle_max = fxp_bundle_max; 2366 log(LOG_INFO, "%s: Microcode loaded: int delay: %d usec, " 2367 "max bundle: %d\n", sc->sc_dev.dv_xname, 2368 sc->sc_int_delay, 2369 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2370 } 2371 2372 sc->sc_flags |= FXPF_UCODE_LOADED; 2373 } 2374 2375 int 2376 fxp_enable(struct fxp_softc *sc) 2377 { 2378 2379 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2380 if ((*sc->sc_enable)(sc) != 0) { 2381 log(LOG_ERR, "%s: device enable failed\n", 2382 sc->sc_dev.dv_xname); 2383 return (EIO); 2384 } 2385 } 2386 2387 sc->sc_enabled = 1; 2388 return (0); 2389 } 2390 2391 void 2392 fxp_disable(struct fxp_softc *sc) 2393 { 2394 2395 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2396 (*sc->sc_disable)(sc); 2397 sc->sc_enabled = 0; 2398 } 2399 } 2400 2401 /* 2402 * fxp_activate: 2403 * 2404 * Handle device activation/deactivation requests. 2405 */ 2406 int 2407 fxp_activate(struct device *self, enum devact act) 2408 { 2409 struct fxp_softc *sc = (void *) self; 2410 int s, error = 0; 2411 2412 s = splnet(); 2413 switch (act) { 2414 case DVACT_ACTIVATE: 2415 error = EOPNOTSUPP; 2416 break; 2417 2418 case DVACT_DEACTIVATE: 2419 if (sc->sc_flags & FXPF_MII) 2420 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 2421 MII_OFFSET_ANY); 2422 if_deactivate(&sc->sc_ethercom.ec_if); 2423 break; 2424 } 2425 splx(s); 2426 2427 return (error); 2428 } 2429 2430 /* 2431 * fxp_detach: 2432 * 2433 * Detach an i82557 interface. 2434 */ 2435 int 2436 fxp_detach(struct fxp_softc *sc) 2437 { 2438 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2439 int i; 2440 2441 /* Succeed now if there's no work to do. */ 2442 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2443 return (0); 2444 2445 /* Unhook our tick handler. */ 2446 callout_stop(&sc->sc_callout); 2447 2448 if (sc->sc_flags & FXPF_MII) { 2449 /* Detach all PHYs */ 2450 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2451 } 2452 2453 /* Delete all remaining media. */ 2454 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2455 2456 #if NRND > 0 2457 rnd_detach_source(&sc->rnd_source); 2458 #endif 2459 ether_ifdetach(ifp); 2460 if_detach(ifp); 2461 2462 for (i = 0; i < FXP_NRFABUFS; i++) { 2463 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2464 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2465 } 2466 2467 for (i = 0; i < FXP_NTXCB; i++) { 2468 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2469 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2470 } 2471 2472 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2473 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2474 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2475 sizeof(struct fxp_control_data)); 2476 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2477 2478 shutdownhook_disestablish(sc->sc_sdhook); 2479 powerhook_disestablish(sc->sc_powerhook); 2480 2481 return (0); 2482 }
Cache object: a157a2d9d97f0821f7c408e36b4e5d53
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