Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/i82557.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /* $NetBSD: i82557.c,v 1.115.4.1 2008/12/14 11:52:40 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1995, David Greenman 35 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice unmodified, this list of conditions, and the following 43 * disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 61 */ 62 63 /* 64 * Device driver for the Intel i82557 fast Ethernet controller, 65 * and its successors, the i82558 and i82559. 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.115.4.1 2008/12/14 11:52:40 bouyer Exp $"); 70 71 #include "bpfilter.h" 72 #include "rnd.h" 73 74 #include <sys/param.h> 75 #include <sys/systm.h> 76 #include <sys/callout.h> 77 #include <sys/mbuf.h> 78 #include <sys/malloc.h> 79 #include <sys/kernel.h> 80 #include <sys/socket.h> 81 #include <sys/ioctl.h> 82 #include <sys/errno.h> 83 #include <sys/device.h> 84 #include <sys/syslog.h> 85 86 #include <machine/endian.h> 87 88 #include <uvm/uvm_extern.h> 89 90 #if NRND > 0 91 #include <sys/rnd.h> 92 #endif 93 94 #include <net/if.h> 95 #include <net/if_dl.h> 96 #include <net/if_media.h> 97 #include <net/if_ether.h> 98 99 #if NBPFILTER > 0 100 #include <net/bpf.h> 101 #endif 102 103 #include <sys/bus.h> 104 #include <sys/intr.h> 105 106 #include <dev/mii/miivar.h> 107 108 #include <dev/ic/i82557reg.h> 109 #include <dev/ic/i82557var.h> 110 111 #include <dev/microcode/i8255x/rcvbundl.h> 112 113 /* 114 * NOTE! On the Alpha, we have an alignment constraint. The 115 * card DMAs the packet immediately following the RFA. However, 116 * the first thing in the packet is a 14-byte Ethernet header. 117 * This means that the packet is misaligned. To compensate, 118 * we actually offset the RFA 2 bytes into the cluster. This 119 * alignes the packet after the Ethernet header at a 32-bit 120 * boundary. HOWEVER! This means that the RFA is misaligned! 121 */ 122 #define RFA_ALIGNMENT_FUDGE 2 123 124 /* 125 * The configuration byte map has several undefined fields which 126 * must be one or must be zero. Set up a template for these bits 127 * only (assuming an i82557 chip), leaving the actual configuration 128 * for fxp_init(). 129 * 130 * See the definition of struct fxp_cb_config for the bit definitions. 131 */ 132 const u_int8_t fxp_cb_config_template[] = { 133 0x0, 0x0, /* cb_status */ 134 0x0, 0x0, /* cb_command */ 135 0x0, 0x0, 0x0, 0x0, /* link_addr */ 136 0x0, /* 0 */ 137 0x0, /* 1 */ 138 0x0, /* 2 */ 139 0x0, /* 3 */ 140 0x0, /* 4 */ 141 0x0, /* 5 */ 142 0x32, /* 6 */ 143 0x0, /* 7 */ 144 0x0, /* 8 */ 145 0x0, /* 9 */ 146 0x6, /* 10 */ 147 0x0, /* 11 */ 148 0x0, /* 12 */ 149 0x0, /* 13 */ 150 0xf2, /* 14 */ 151 0x48, /* 15 */ 152 0x0, /* 16 */ 153 0x40, /* 17 */ 154 0xf0, /* 18 */ 155 0x0, /* 19 */ 156 0x3f, /* 20 */ 157 0x5, /* 21 */ 158 0x0, /* 22 */ 159 0x0, /* 23 */ 160 0x0, /* 24 */ 161 0x0, /* 25 */ 162 0x0, /* 26 */ 163 0x0, /* 27 */ 164 0x0, /* 28 */ 165 0x0, /* 29 */ 166 0x0, /* 30 */ 167 0x0, /* 31 */ 168 }; 169 170 void fxp_mii_initmedia(struct fxp_softc *); 171 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 172 173 void fxp_80c24_initmedia(struct fxp_softc *); 174 int fxp_80c24_mediachange(struct ifnet *); 175 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 176 177 void fxp_start(struct ifnet *); 178 int fxp_ioctl(struct ifnet *, u_long, void *); 179 void fxp_watchdog(struct ifnet *); 180 int fxp_init(struct ifnet *); 181 void fxp_stop(struct ifnet *, int); 182 183 void fxp_txintr(struct fxp_softc *); 184 int fxp_rxintr(struct fxp_softc *); 185 186 int fxp_rx_hwcksum(struct mbuf *, const struct fxp_rfa *); 187 188 void fxp_rxdrain(struct fxp_softc *); 189 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 190 int fxp_mdi_read(device_t, int, int); 191 void fxp_statchg(device_t); 192 void fxp_mdi_write(device_t, int, int, int); 193 void fxp_autosize_eeprom(struct fxp_softc*); 194 void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 195 void fxp_write_eeprom(struct fxp_softc *, u_int16_t *, int, int); 196 void fxp_eeprom_update_cksum(struct fxp_softc *); 197 void fxp_get_info(struct fxp_softc *, u_int8_t *); 198 void fxp_tick(void *); 199 void fxp_mc_setup(struct fxp_softc *); 200 void fxp_load_ucode(struct fxp_softc *); 201 202 int fxp_copy_small = 0; 203 204 /* 205 * Variables for interrupt mitigating microcode. 206 */ 207 int fxp_int_delay = 1000; /* usec */ 208 int fxp_bundle_max = 6; /* packets */ 209 210 struct fxp_phytype { 211 int fp_phy; /* type of PHY, -1 for MII at the end. */ 212 void (*fp_init)(struct fxp_softc *); 213 } fxp_phytype_table[] = { 214 { FXP_PHY_80C24, fxp_80c24_initmedia }, 215 { -1, fxp_mii_initmedia }, 216 }; 217 218 /* 219 * Set initial transmit threshold at 64 (512 bytes). This is 220 * increased by 64 (512 bytes) at a time, to maximum of 192 221 * (1536 bytes), if an underrun occurs. 222 */ 223 static int tx_threshold = 64; 224 225 /* 226 * Wait for the previous command to be accepted (but not necessarily 227 * completed). 228 */ 229 static inline void 230 fxp_scb_wait(struct fxp_softc *sc) 231 { 232 int i = 10000; 233 234 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 235 delay(2); 236 if (i == 0) 237 log(LOG_WARNING, 238 "%s: WARNING: SCB timed out!\n", device_xname(sc->sc_dev)); 239 } 240 241 /* 242 * Submit a command to the i82557. 243 */ 244 static inline void 245 fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 246 { 247 248 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 249 } 250 251 /* 252 * Finish attaching an i82557 interface. Called by bus-specific front-end. 253 */ 254 void 255 fxp_attach(struct fxp_softc *sc) 256 { 257 u_int8_t enaddr[ETHER_ADDR_LEN]; 258 struct ifnet *ifp; 259 bus_dma_segment_t seg; 260 int rseg, i, error; 261 struct fxp_phytype *fp; 262 263 callout_init(&sc->sc_callout, 0); 264 265 /* 266 * Enable some good stuff on i82558 and later. 267 */ 268 if (sc->sc_rev >= FXP_REV_82558_A4) { 269 /* Enable the extended TxCB. */ 270 sc->sc_flags |= FXPF_EXT_TXCB; 271 } 272 273 /* 274 * Enable use of extended RFDs and TCBs for 82550 275 * and later chips. Note: we need extended TXCB support 276 * too, but that's already enabled by the code above. 277 * Be careful to do this only on the right devices. 278 */ 279 if (sc->sc_rev == FXP_REV_82550 || sc->sc_rev == FXP_REV_82550_C) { 280 sc->sc_flags |= FXPF_EXT_RFA | FXPF_IPCB; 281 sc->sc_txcmd = htole16(FXP_CB_COMMAND_IPCBXMIT); 282 } else { 283 sc->sc_txcmd = htole16(FXP_CB_COMMAND_XMIT); 284 } 285 286 sc->sc_rfa_size = 287 (sc->sc_flags & FXPF_EXT_RFA) ? RFA_EXT_SIZE : RFA_SIZE; 288 289 /* 290 * Allocate the control data structures, and create and load the 291 * DMA map for it. 292 */ 293 if ((error = bus_dmamem_alloc(sc->sc_dmat, 294 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 295 0)) != 0) { 296 aprint_error_dev(sc->sc_dev, 297 "unable to allocate control data, error = %d\n", 298 error); 299 goto fail_0; 300 } 301 302 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 303 sizeof(struct fxp_control_data), (void **)&sc->sc_control_data, 304 BUS_DMA_COHERENT)) != 0) { 305 aprint_error_dev(sc->sc_dev, "unable to map control data, error = %d\n", 306 error); 307 goto fail_1; 308 } 309 sc->sc_cdseg = seg; 310 sc->sc_cdnseg = rseg; 311 312 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 313 314 if ((error = bus_dmamap_create(sc->sc_dmat, 315 sizeof(struct fxp_control_data), 1, 316 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 317 aprint_error_dev(sc->sc_dev, "unable to create control data DMA map, " 318 "error = %d\n", error); 319 goto fail_2; 320 } 321 322 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 323 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 324 0)) != 0) { 325 aprint_error_dev(sc->sc_dev, 326 "can't load control data DMA map, error = %d\n", 327 error); 328 goto fail_3; 329 } 330 331 /* 332 * Create the transmit buffer DMA maps. 333 */ 334 for (i = 0; i < FXP_NTXCB; i++) { 335 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 336 (sc->sc_flags & FXPF_IPCB) ? FXP_IPCB_NTXSEG : FXP_NTXSEG, 337 MCLBYTES, 0, 0, &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 338 aprint_error_dev(sc->sc_dev, "unable to create tx DMA map %d, " 339 "error = %d\n", i, error); 340 goto fail_4; 341 } 342 } 343 344 /* 345 * Create the receive buffer DMA maps. 346 */ 347 for (i = 0; i < FXP_NRFABUFS; i++) { 348 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 349 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 350 aprint_error_dev(sc->sc_dev, "unable to create rx DMA map %d, " 351 "error = %d\n", i, error); 352 goto fail_5; 353 } 354 } 355 356 /* Initialize MAC address and media structures. */ 357 fxp_get_info(sc, enaddr); 358 359 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 360 ether_sprintf(enaddr)); 361 362 ifp = &sc->sc_ethercom.ec_if; 363 364 /* 365 * Get info about our media interface, and initialize it. Note 366 * the table terminates itself with a phy of -1, indicating 367 * that we're using MII. 368 */ 369 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 370 if (fp->fp_phy == sc->phy_primary_device) 371 break; 372 (*fp->fp_init)(sc); 373 374 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 375 ifp->if_softc = sc; 376 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 377 ifp->if_ioctl = fxp_ioctl; 378 ifp->if_start = fxp_start; 379 ifp->if_watchdog = fxp_watchdog; 380 ifp->if_init = fxp_init; 381 ifp->if_stop = fxp_stop; 382 IFQ_SET_READY(&ifp->if_snd); 383 384 if (sc->sc_flags & FXPF_IPCB) { 385 KASSERT(sc->sc_flags & FXPF_EXT_RFA); /* we have both or none */ 386 /* 387 * IFCAP_CSUM_IPv4_Tx seems to have a problem, 388 * at least, on i82550 rev.12. 389 * specifically, it doesn't set ipv4 checksum properly 390 * when sending UDP (and probably TCP) packets with 391 * 20 byte ipv4 header + 1 or 2 byte data, 392 * though ICMP packets seem working. 393 * FreeBSD driver has related comments. 394 * We've added a workaround to handle the bug by padding 395 * such packets manually. 396 */ 397 ifp->if_capabilities = 398 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 399 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 400 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 401 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 402 } 403 404 /* 405 * We can support 802.1Q VLAN-sized frames. 406 */ 407 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 408 409 /* 410 * Attach the interface. 411 */ 412 if_attach(ifp); 413 ether_ifattach(ifp, enaddr); 414 #if NRND > 0 415 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 416 RND_TYPE_NET, 0); 417 #endif 418 419 #ifdef FXP_EVENT_COUNTERS 420 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 421 NULL, device_xname(sc->sc_dev), "txstall"); 422 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 423 NULL, device_xname(sc->sc_dev), "txintr"); 424 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 425 NULL, device_xname(sc->sc_dev), "rxintr"); 426 if (sc->sc_rev >= FXP_REV_82558_A4) { 427 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 428 NULL, device_xname(sc->sc_dev), "txpause"); 429 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 430 NULL, device_xname(sc->sc_dev), "rxpause"); 431 } 432 #endif /* FXP_EVENT_COUNTERS */ 433 434 /* The attach is successful. */ 435 sc->sc_flags |= FXPF_ATTACHED; 436 437 return; 438 439 /* 440 * Free any resources we've allocated during the failed attach 441 * attempt. Do this in reverse order and fall though. 442 */ 443 fail_5: 444 for (i = 0; i < FXP_NRFABUFS; i++) { 445 if (sc->sc_rxmaps[i] != NULL) 446 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 447 } 448 fail_4: 449 for (i = 0; i < FXP_NTXCB; i++) { 450 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 451 bus_dmamap_destroy(sc->sc_dmat, 452 FXP_DSTX(sc, i)->txs_dmamap); 453 } 454 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 455 fail_3: 456 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 457 fail_2: 458 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 459 sizeof(struct fxp_control_data)); 460 fail_1: 461 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 462 fail_0: 463 return; 464 } 465 466 void 467 fxp_mii_initmedia(struct fxp_softc *sc) 468 { 469 int flags; 470 471 sc->sc_flags |= FXPF_MII; 472 473 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 474 sc->sc_mii.mii_readreg = fxp_mdi_read; 475 sc->sc_mii.mii_writereg = fxp_mdi_write; 476 sc->sc_mii.mii_statchg = fxp_statchg; 477 478 sc->sc_ethercom.ec_mii = &sc->sc_mii; 479 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 480 fxp_mii_mediastatus); 481 482 flags = MIIF_NOISOLATE; 483 if (sc->sc_rev >= FXP_REV_82558_A4) 484 flags |= MIIF_DOPAUSE; 485 /* 486 * The i82557 wedges if all of its PHYs are isolated! 487 */ 488 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 489 MII_OFFSET_ANY, flags); 490 if (LIST_EMPTY(&sc->sc_mii.mii_phys)) { 491 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 492 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 493 } else 494 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 495 } 496 497 void 498 fxp_80c24_initmedia(struct fxp_softc *sc) 499 { 500 501 /* 502 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 503 * doesn't have a programming interface of any sort. The 504 * media is sensed automatically based on how the link partner 505 * is configured. This is, in essence, manual configuration. 506 */ 507 aprint_normal_dev(sc->sc_dev, "Seeq 80c24 AutoDUPLEX media interface present\n"); 508 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 509 fxp_80c24_mediastatus); 510 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 511 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 512 } 513 514 /* 515 * Initialize the interface media. 516 */ 517 void 518 fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 519 { 520 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 521 522 /* 523 * Reset to a stable state. 524 */ 525 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 526 DELAY(100); 527 528 sc->sc_eeprom_size = 0; 529 fxp_autosize_eeprom(sc); 530 if (sc->sc_eeprom_size == 0) { 531 aprint_error_dev(sc->sc_dev, "failed to detect EEPROM size\n"); 532 sc->sc_eeprom_size = 6; /* XXX panic here? */ 533 } 534 #ifdef DEBUG 535 aprint_debug_dev(sc->sc_dev, "detected %d word EEPROM\n", 536 1 << sc->sc_eeprom_size); 537 #endif 538 539 /* 540 * Get info about the primary PHY 541 */ 542 fxp_read_eeprom(sc, &data, 6, 1); 543 sc->phy_primary_device = 544 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 545 546 /* 547 * Read MAC address. 548 */ 549 fxp_read_eeprom(sc, myea, 0, 3); 550 enaddr[0] = myea[0] & 0xff; 551 enaddr[1] = myea[0] >> 8; 552 enaddr[2] = myea[1] & 0xff; 553 enaddr[3] = myea[1] >> 8; 554 enaddr[4] = myea[2] & 0xff; 555 enaddr[5] = myea[2] >> 8; 556 557 /* 558 * Systems based on the ICH2/ICH2-M chip from Intel, as well 559 * as some i82559 designs, have a defect where the chip can 560 * cause a PCI protocol violation if it receives a CU_RESUME 561 * command when it is entering the IDLE state. 562 * 563 * The work-around is to disable Dynamic Standby Mode, so that 564 * the chip never deasserts #CLKRUN, and always remains in the 565 * active state. 566 * 567 * Unfortunately, the only way to disable Dynamic Standby is 568 * to frob an EEPROM setting and reboot (the EEPROM setting 569 * is only consulted when the PCI bus comes out of reset). 570 * 571 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 572 */ 573 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 574 fxp_read_eeprom(sc, &data, 10, 1); 575 if (data & 0x02) { /* STB enable */ 576 aprint_error_dev(sc->sc_dev, "WARNING: " 577 "Disabling dynamic standby mode in EEPROM " 578 "to work around a\n"); 579 aprint_normal_dev(sc->sc_dev, 580 "WARNING: hardware bug. You must reset " 581 "the system before using this\n"); 582 aprint_normal_dev(sc->sc_dev, "WARNING: interface.\n"); 583 data &= ~0x02; 584 fxp_write_eeprom(sc, &data, 10, 1); 585 aprint_normal_dev(sc->sc_dev, "new EEPROM ID: 0x%04x\n", 586 data); 587 fxp_eeprom_update_cksum(sc); 588 } 589 } 590 591 /* Receiver lock-up workaround detection. (FXPF_RECV_WORKAROUND) */ 592 /* Due to false positives we make it conditional on setting link1 */ 593 fxp_read_eeprom(sc, &data, 3, 1); 594 if ((data & 0x03) != 0x03) { 595 aprint_verbose_dev(sc->sc_dev, "May need receiver lock-up workaround\n"); 596 } 597 } 598 599 static void 600 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 601 { 602 uint16_t reg; 603 int x; 604 605 for (x = 1 << (len - 1); x != 0; x >>= 1) { 606 DELAY(40); 607 if (data & x) 608 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 609 else 610 reg = FXP_EEPROM_EECS; 611 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 612 DELAY(40); 613 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 614 reg | FXP_EEPROM_EESK); 615 DELAY(40); 616 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 617 } 618 DELAY(40); 619 } 620 621 /* 622 * Figure out EEPROM size. 623 * 624 * 559's can have either 64-word or 256-word EEPROMs, the 558 625 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 626 * talks about the existence of 16 to 256 word EEPROMs. 627 * 628 * The only known sizes are 64 and 256, where the 256 version is used 629 * by CardBus cards to store CIS information. 630 * 631 * The address is shifted in msb-to-lsb, and after the last 632 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 633 * after which follows the actual data. We try to detect this zero, by 634 * probing the data-out bit in the EEPROM control register just after 635 * having shifted in a bit. If the bit is zero, we assume we've 636 * shifted enough address bits. The data-out should be tri-state, 637 * before this, which should translate to a logical one. 638 * 639 * Other ways to do this would be to try to read a register with known 640 * contents with a varying number of address bits, but no such 641 * register seem to be available. The high bits of register 10 are 01 642 * on the 558 and 559, but apparently not on the 557. 643 * 644 * The Linux driver computes a checksum on the EEPROM data, but the 645 * value of this checksum is not very well documented. 646 */ 647 648 void 649 fxp_autosize_eeprom(struct fxp_softc *sc) 650 { 651 int x; 652 653 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 654 DELAY(40); 655 656 /* Shift in read opcode. */ 657 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 658 659 /* 660 * Shift in address, wait for the dummy zero following a correct 661 * address shift. 662 */ 663 for (x = 1; x <= 8; x++) { 664 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 665 DELAY(40); 666 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 667 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 668 DELAY(40); 669 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 670 FXP_EEPROM_EEDO) == 0) 671 break; 672 DELAY(40); 673 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 674 DELAY(40); 675 } 676 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 677 DELAY(40); 678 if (x != 6 && x != 8) { 679 #ifdef DEBUG 680 printf("%s: strange EEPROM size (%d)\n", 681 device_xname(sc->sc_dev), 1 << x); 682 #endif 683 } else 684 sc->sc_eeprom_size = x; 685 } 686 687 /* 688 * Read from the serial EEPROM. Basically, you manually shift in 689 * the read opcode (one bit at a time) and then shift in the address, 690 * and then you shift out the data (all of this one bit at a time). 691 * The word size is 16 bits, so you have to provide the address for 692 * every 16 bits of data. 693 */ 694 void 695 fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 696 { 697 u_int16_t reg; 698 int i, x; 699 700 for (i = 0; i < words; i++) { 701 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 702 703 /* Shift in read opcode. */ 704 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 705 706 /* Shift in address. */ 707 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 708 709 reg = FXP_EEPROM_EECS; 710 data[i] = 0; 711 712 /* Shift out data. */ 713 for (x = 16; x > 0; x--) { 714 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 715 reg | FXP_EEPROM_EESK); 716 DELAY(40); 717 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 718 FXP_EEPROM_EEDO) 719 data[i] |= (1 << (x - 1)); 720 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 721 DELAY(40); 722 } 723 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 724 DELAY(40); 725 } 726 } 727 728 /* 729 * Write data to the serial EEPROM. 730 */ 731 void 732 fxp_write_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 733 { 734 int i, j; 735 736 for (i = 0; i < words; i++) { 737 /* Erase/write enable. */ 738 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 739 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 740 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 741 sc->sc_eeprom_size); 742 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 743 DELAY(4); 744 745 /* Shift in write opcode, address, data. */ 746 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 747 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 748 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 749 fxp_eeprom_shiftin(sc, data[i], 16); 750 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 751 DELAY(4); 752 753 /* Wait for the EEPROM to finish up. */ 754 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 755 DELAY(4); 756 for (j = 0; j < 1000; j++) { 757 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 758 FXP_EEPROM_EEDO) 759 break; 760 DELAY(50); 761 } 762 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 763 DELAY(4); 764 765 /* Erase/write disable. */ 766 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 767 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 768 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 769 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 770 DELAY(4); 771 } 772 } 773 774 /* 775 * Update the checksum of the EEPROM. 776 */ 777 void 778 fxp_eeprom_update_cksum(struct fxp_softc *sc) 779 { 780 int i; 781 uint16_t data, cksum; 782 783 cksum = 0; 784 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 785 fxp_read_eeprom(sc, &data, i, 1); 786 cksum += data; 787 } 788 i = (1 << sc->sc_eeprom_size) - 1; 789 cksum = 0xbaba - cksum; 790 fxp_read_eeprom(sc, &data, i, 1); 791 fxp_write_eeprom(sc, &cksum, i, 1); 792 log(LOG_INFO, "%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 793 device_xname(sc->sc_dev), i, data, cksum); 794 } 795 796 /* 797 * Start packet transmission on the interface. 798 */ 799 void 800 fxp_start(struct ifnet *ifp) 801 { 802 struct fxp_softc *sc = ifp->if_softc; 803 struct mbuf *m0, *m; 804 struct fxp_txdesc *txd; 805 struct fxp_txsoft *txs; 806 bus_dmamap_t dmamap; 807 int error, lasttx, nexttx, opending, seg, nsegs, len; 808 809 /* 810 * If we want a re-init, bail out now. 811 */ 812 if (sc->sc_flags & FXPF_WANTINIT) { 813 ifp->if_flags |= IFF_OACTIVE; 814 return; 815 } 816 817 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 818 return; 819 820 /* 821 * Remember the previous txpending and the current lasttx. 822 */ 823 opending = sc->sc_txpending; 824 lasttx = sc->sc_txlast; 825 826 /* 827 * Loop through the send queue, setting up transmit descriptors 828 * until we drain the queue, or use up all available transmit 829 * descriptors. 830 */ 831 for (;;) { 832 struct fxp_tbd *tbdp; 833 int csum_flags; 834 835 /* 836 * Grab a packet off the queue. 837 */ 838 IFQ_POLL(&ifp->if_snd, m0); 839 if (m0 == NULL) 840 break; 841 m = NULL; 842 843 if (sc->sc_txpending == FXP_NTXCB - 1) { 844 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 845 break; 846 } 847 848 /* 849 * Get the next available transmit descriptor. 850 */ 851 nexttx = FXP_NEXTTX(sc->sc_txlast); 852 txd = FXP_CDTX(sc, nexttx); 853 txs = FXP_DSTX(sc, nexttx); 854 dmamap = txs->txs_dmamap; 855 856 /* 857 * Load the DMA map. If this fails, the packet either 858 * didn't fit in the allotted number of frags, or we were 859 * short on resources. In this case, we'll copy and try 860 * again. 861 */ 862 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 863 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 864 MGETHDR(m, M_DONTWAIT, MT_DATA); 865 if (m == NULL) { 866 log(LOG_ERR, "%s: unable to allocate Tx mbuf\n", 867 device_xname(sc->sc_dev)); 868 break; 869 } 870 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 871 if (m0->m_pkthdr.len > MHLEN) { 872 MCLGET(m, M_DONTWAIT); 873 if ((m->m_flags & M_EXT) == 0) { 874 log(LOG_ERR, 875 "%s: unable to allocate Tx " 876 "cluster\n", device_xname(sc->sc_dev)); 877 m_freem(m); 878 break; 879 } 880 } 881 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 882 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 883 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 884 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 885 if (error) { 886 log(LOG_ERR, "%s: unable to load Tx buffer, " 887 "error = %d\n", device_xname(sc->sc_dev), error); 888 break; 889 } 890 } 891 892 IFQ_DEQUEUE(&ifp->if_snd, m0); 893 csum_flags = m0->m_pkthdr.csum_flags; 894 if (m != NULL) { 895 m_freem(m0); 896 m0 = m; 897 } 898 899 /* Initialize the fraglist. */ 900 tbdp = txd->txd_tbd; 901 len = m0->m_pkthdr.len; 902 nsegs = dmamap->dm_nsegs; 903 if (sc->sc_flags & FXPF_IPCB) 904 tbdp++; 905 for (seg = 0; seg < nsegs; seg++) { 906 tbdp[seg].tb_addr = 907 htole32(dmamap->dm_segs[seg].ds_addr); 908 tbdp[seg].tb_size = 909 htole32(dmamap->dm_segs[seg].ds_len); 910 } 911 if (__predict_false(len <= FXP_IP4CSUMTX_PADLEN && 912 (csum_flags & M_CSUM_IPv4) != 0)) { 913 /* 914 * Pad short packets to avoid ip4csum-tx bug. 915 * 916 * XXX Should we still consider if such short 917 * (36 bytes or less) packets might already 918 * occupy FXP_IPCB_NTXSEG (15) fragments here? 919 */ 920 KASSERT(nsegs < FXP_IPCB_NTXSEG); 921 nsegs++; 922 tbdp[seg].tb_addr = htole32(FXP_CDTXPADADDR(sc)); 923 tbdp[seg].tb_size = 924 htole32(FXP_IP4CSUMTX_PADLEN + 1 - len); 925 } 926 927 /* Sync the DMA map. */ 928 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 929 BUS_DMASYNC_PREWRITE); 930 931 /* 932 * Store a pointer to the packet so we can free it later. 933 */ 934 txs->txs_mbuf = m0; 935 936 /* 937 * Initialize the transmit descriptor. 938 */ 939 /* BIG_ENDIAN: no need to swap to store 0 */ 940 txd->txd_txcb.cb_status = 0; 941 txd->txd_txcb.cb_command = 942 sc->sc_txcmd | htole16(FXP_CB_COMMAND_SF); 943 txd->txd_txcb.tx_threshold = tx_threshold; 944 txd->txd_txcb.tbd_number = nsegs; 945 946 KASSERT((csum_flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) == 0); 947 if (sc->sc_flags & FXPF_IPCB) { 948 struct m_tag *vtag; 949 struct fxp_ipcb *ipcb; 950 /* 951 * Deal with TCP/IP checksum offload. Note that 952 * in order for TCP checksum offload to work, 953 * the pseudo header checksum must have already 954 * been computed and stored in the checksum field 955 * in the TCP header. The stack should have 956 * already done this for us. 957 */ 958 ipcb = &txd->txd_u.txdu_ipcb; 959 memset(ipcb, 0, sizeof(*ipcb)); 960 /* 961 * always do hardware parsing. 962 */ 963 ipcb->ipcb_ip_activation_high = 964 FXP_IPCB_HARDWAREPARSING_ENABLE; 965 /* 966 * ip checksum offloading. 967 */ 968 if (csum_flags & M_CSUM_IPv4) { 969 ipcb->ipcb_ip_schedule |= 970 FXP_IPCB_IP_CHECKSUM_ENABLE; 971 } 972 /* 973 * TCP/UDP checksum offloading. 974 */ 975 if (csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 976 ipcb->ipcb_ip_schedule |= 977 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 978 } 979 980 /* 981 * request VLAN tag insertion if needed. 982 */ 983 vtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0); 984 if (vtag) { 985 ipcb->ipcb_vlan_id = 986 htobe16(*(u_int *)(vtag + 1)); 987 ipcb->ipcb_ip_activation_high |= 988 FXP_IPCB_INSERTVLAN_ENABLE; 989 } 990 } else { 991 KASSERT((csum_flags & 992 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) == 0); 993 } 994 995 FXP_CDTXSYNC(sc, nexttx, 996 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 997 998 /* Advance the tx pointer. */ 999 sc->sc_txpending++; 1000 sc->sc_txlast = nexttx; 1001 1002 #if NBPFILTER > 0 1003 /* 1004 * Pass packet to bpf if there is a listener. 1005 */ 1006 if (ifp->if_bpf) 1007 bpf_mtap(ifp->if_bpf, m0); 1008 #endif 1009 } 1010 1011 if (sc->sc_txpending == FXP_NTXCB - 1) { 1012 /* No more slots; notify upper layer. */ 1013 ifp->if_flags |= IFF_OACTIVE; 1014 } 1015 1016 if (sc->sc_txpending != opending) { 1017 /* 1018 * We enqueued packets. If the transmitter was idle, 1019 * reset the txdirty pointer. 1020 */ 1021 if (opending == 0) 1022 sc->sc_txdirty = FXP_NEXTTX(lasttx); 1023 1024 /* 1025 * Cause the chip to interrupt and suspend command 1026 * processing once the last packet we've enqueued 1027 * has been transmitted. 1028 * 1029 * To avoid a race between updating status bits 1030 * by the fxp chip and clearing command bits 1031 * by this function on machines which don't have 1032 * atomic methods to clear/set bits in memory 1033 * smaller than 32bits (both cb_status and cb_command 1034 * members are uint16_t and in the same 32bit word), 1035 * we have to prepare a dummy TX descriptor which has 1036 * NOP command and just causes a TX completion interrupt. 1037 */ 1038 sc->sc_txpending++; 1039 sc->sc_txlast = FXP_NEXTTX(sc->sc_txlast); 1040 txd = FXP_CDTX(sc, sc->sc_txlast); 1041 /* BIG_ENDIAN: no need to swap to store 0 */ 1042 txd->txd_txcb.cb_status = 0; 1043 txd->txd_txcb.cb_command = htole16(FXP_CB_COMMAND_NOP | 1044 FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 1045 FXP_CDTXSYNC(sc, sc->sc_txlast, 1046 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1047 1048 /* 1049 * The entire packet chain is set up. Clear the suspend bit 1050 * on the command prior to the first packet we set up. 1051 */ 1052 FXP_CDTXSYNC(sc, lasttx, 1053 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1054 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 1055 htole16(~FXP_CB_COMMAND_S); 1056 FXP_CDTXSYNC(sc, lasttx, 1057 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1058 1059 /* 1060 * Issue a Resume command in case the chip was suspended. 1061 */ 1062 fxp_scb_wait(sc); 1063 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1064 1065 /* Set a watchdog timer in case the chip flakes out. */ 1066 ifp->if_timer = 5; 1067 } 1068 } 1069 1070 /* 1071 * Process interface interrupts. 1072 */ 1073 int 1074 fxp_intr(void *arg) 1075 { 1076 struct fxp_softc *sc = arg; 1077 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1078 bus_dmamap_t rxmap; 1079 int claimed = 0, rnr; 1080 u_int8_t statack; 1081 1082 if (!device_is_active(sc->sc_dev) || sc->sc_enabled == 0) 1083 return (0); 1084 /* 1085 * If the interface isn't running, don't try to 1086 * service the interrupt.. just ack it and bail. 1087 */ 1088 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1089 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1090 if (statack) { 1091 claimed = 1; 1092 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1093 } 1094 return (claimed); 1095 } 1096 1097 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1098 claimed = 1; 1099 1100 /* 1101 * First ACK all the interrupts in this pass. 1102 */ 1103 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1104 1105 /* 1106 * Process receiver interrupts. If a no-resource (RNR) 1107 * condition exists, get whatever packets we can and 1108 * re-start the receiver. 1109 */ 1110 rnr = (statack & (FXP_SCB_STATACK_RNR | FXP_SCB_STATACK_SWI)) ? 1111 1 : 0; 1112 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR | 1113 FXP_SCB_STATACK_SWI)) { 1114 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1115 rnr |= fxp_rxintr(sc); 1116 } 1117 1118 /* 1119 * Free any finished transmit mbuf chains. 1120 */ 1121 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1122 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1123 fxp_txintr(sc); 1124 1125 /* 1126 * Try to get more packets going. 1127 */ 1128 fxp_start(ifp); 1129 1130 if (sc->sc_txpending == 0) { 1131 /* 1132 * Tell them that they can re-init now. 1133 */ 1134 if (sc->sc_flags & FXPF_WANTINIT) 1135 wakeup(sc); 1136 } 1137 } 1138 1139 if (rnr) { 1140 fxp_scb_wait(sc); 1141 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_ABORT); 1142 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1143 fxp_scb_wait(sc); 1144 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1145 rxmap->dm_segs[0].ds_addr + 1146 RFA_ALIGNMENT_FUDGE); 1147 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1148 } 1149 } 1150 1151 #if NRND > 0 1152 if (claimed) 1153 rnd_add_uint32(&sc->rnd_source, statack); 1154 #endif 1155 return (claimed); 1156 } 1157 1158 /* 1159 * Handle transmit completion interrupts. 1160 */ 1161 void 1162 fxp_txintr(struct fxp_softc *sc) 1163 { 1164 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1165 struct fxp_txdesc *txd; 1166 struct fxp_txsoft *txs; 1167 int i; 1168 u_int16_t txstat; 1169 1170 ifp->if_flags &= ~IFF_OACTIVE; 1171 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1172 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1173 txd = FXP_CDTX(sc, i); 1174 txs = FXP_DSTX(sc, i); 1175 1176 FXP_CDTXSYNC(sc, i, 1177 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1178 1179 /* skip dummy NOP TX descriptor */ 1180 if ((le16toh(txd->txd_txcb.cb_command) & FXP_CB_COMMAND_CMD) 1181 == FXP_CB_COMMAND_NOP) 1182 continue; 1183 1184 txstat = le16toh(txd->txd_txcb.cb_status); 1185 1186 if ((txstat & FXP_CB_STATUS_C) == 0) 1187 break; 1188 1189 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1190 0, txs->txs_dmamap->dm_mapsize, 1191 BUS_DMASYNC_POSTWRITE); 1192 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1193 m_freem(txs->txs_mbuf); 1194 txs->txs_mbuf = NULL; 1195 } 1196 1197 /* Update the dirty transmit buffer pointer. */ 1198 sc->sc_txdirty = i; 1199 1200 /* 1201 * Cancel the watchdog timer if there are no pending 1202 * transmissions. 1203 */ 1204 if (sc->sc_txpending == 0) 1205 ifp->if_timer = 0; 1206 } 1207 1208 /* 1209 * fxp_rx_hwcksum: check status of H/W offloading for received packets. 1210 */ 1211 1212 int 1213 fxp_rx_hwcksum(struct mbuf *m, const struct fxp_rfa *rfa) 1214 { 1215 u_int8_t rxparsestat; 1216 u_int8_t csum_stat; 1217 u_int32_t csum_data; 1218 int csum_flags; 1219 1220 /* 1221 * check VLAN tag stripping. 1222 */ 1223 1224 if (rfa->rfa_status & htole16(FXP_RFA_STATUS_VLAN)) { 1225 struct m_tag *vtag; 1226 1227 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), M_NOWAIT); 1228 if (vtag == NULL) 1229 return ENOMEM; 1230 *(u_int *)(vtag + 1) = be16toh(rfa->vlan_id); 1231 m_tag_prepend(m, vtag); 1232 } 1233 1234 /* 1235 * check H/W Checksumming. 1236 */ 1237 1238 csum_stat = rfa->cksum_stat; 1239 rxparsestat = rfa->rx_parse_stat; 1240 if (!(rfa->rfa_status & htole16(FXP_RFA_STATUS_PARSE))) 1241 return 0; 1242 1243 csum_flags = 0; 1244 csum_data = 0; 1245 1246 if (csum_stat & FXP_RFDX_CS_IP_CSUM_BIT_VALID) { 1247 csum_flags = M_CSUM_IPv4; 1248 if (!(csum_stat & FXP_RFDX_CS_IP_CSUM_VALID)) 1249 csum_flags |= M_CSUM_IPv4_BAD; 1250 } 1251 1252 if (csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) { 1253 csum_flags |= (M_CSUM_TCPv4|M_CSUM_UDPv4); /* XXX */ 1254 if (!(csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) 1255 csum_flags |= M_CSUM_TCP_UDP_BAD; 1256 } 1257 1258 m->m_pkthdr.csum_flags = csum_flags; 1259 m->m_pkthdr.csum_data = csum_data; 1260 1261 return 0; 1262 } 1263 1264 /* 1265 * Handle receive interrupts. 1266 */ 1267 int 1268 fxp_rxintr(struct fxp_softc *sc) 1269 { 1270 struct ethercom *ec = &sc->sc_ethercom; 1271 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1272 struct mbuf *m, *m0; 1273 bus_dmamap_t rxmap; 1274 struct fxp_rfa *rfa; 1275 int rnr; 1276 u_int16_t len, rxstat; 1277 1278 rnr = 0; 1279 1280 for (;;) { 1281 m = sc->sc_rxq.ifq_head; 1282 rfa = FXP_MTORFA(m); 1283 rxmap = M_GETCTX(m, bus_dmamap_t); 1284 1285 FXP_RFASYNC(sc, m, 1286 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1287 1288 rxstat = le16toh(rfa->rfa_status); 1289 1290 if ((rxstat & FXP_RFA_STATUS_RNR) != 0) 1291 rnr = 1; 1292 1293 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1294 /* 1295 * We have processed all of the 1296 * receive buffers. 1297 */ 1298 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1299 return rnr; 1300 } 1301 1302 IF_DEQUEUE(&sc->sc_rxq, m); 1303 1304 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1305 1306 len = le16toh(rfa->actual_size) & 1307 (m->m_ext.ext_size - 1); 1308 1309 if (len < sizeof(struct ether_header)) { 1310 /* 1311 * Runt packet; drop it now. 1312 */ 1313 FXP_INIT_RFABUF(sc, m); 1314 continue; 1315 } 1316 1317 /* 1318 * If support for 802.1Q VLAN sized frames is 1319 * enabled, we need to do some additional error 1320 * checking (as we are saving bad frames, in 1321 * order to receive the larger ones). 1322 */ 1323 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1324 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1325 FXP_RFA_STATUS_RNR| 1326 FXP_RFA_STATUS_ALIGN| 1327 FXP_RFA_STATUS_CRC)) != 0) { 1328 FXP_INIT_RFABUF(sc, m); 1329 continue; 1330 } 1331 1332 /* Do checksum checking. */ 1333 m->m_pkthdr.csum_flags = 0; 1334 if (sc->sc_flags & FXPF_EXT_RFA) 1335 if (fxp_rx_hwcksum(m, rfa)) 1336 goto dropit; 1337 1338 /* 1339 * If the packet is small enough to fit in a 1340 * single header mbuf, allocate one and copy 1341 * the data into it. This greatly reduces 1342 * memory consumption when we receive lots 1343 * of small packets. 1344 * 1345 * Otherwise, we add a new buffer to the receive 1346 * chain. If this fails, we drop the packet and 1347 * recycle the old buffer. 1348 */ 1349 if (fxp_copy_small != 0 && len <= MHLEN) { 1350 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1351 if (m0 == NULL) 1352 goto dropit; 1353 MCLAIM(m0, &sc->sc_ethercom.ec_rx_mowner); 1354 memcpy(mtod(m0, void *), 1355 mtod(m, void *), len); 1356 m0->m_pkthdr.csum_flags = m->m_pkthdr.csum_flags; 1357 m0->m_pkthdr.csum_data = m->m_pkthdr.csum_data; 1358 FXP_INIT_RFABUF(sc, m); 1359 m = m0; 1360 } else { 1361 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1362 dropit: 1363 ifp->if_ierrors++; 1364 FXP_INIT_RFABUF(sc, m); 1365 continue; 1366 } 1367 } 1368 1369 m->m_pkthdr.rcvif = ifp; 1370 m->m_pkthdr.len = m->m_len = len; 1371 1372 #if NBPFILTER > 0 1373 /* 1374 * Pass this up to any BPF listeners, but only 1375 * pass it up the stack if it's for us. 1376 */ 1377 if (ifp->if_bpf) 1378 bpf_mtap(ifp->if_bpf, m); 1379 #endif 1380 1381 /* Pass it on. */ 1382 (*ifp->if_input)(ifp, m); 1383 } 1384 } 1385 1386 /* 1387 * Update packet in/out/collision statistics. The i82557 doesn't 1388 * allow you to access these counters without doing a fairly 1389 * expensive DMA to get _all_ of the statistics it maintains, so 1390 * we do this operation here only once per second. The statistics 1391 * counters in the kernel are updated from the previous dump-stats 1392 * DMA and then a new dump-stats DMA is started. The on-chip 1393 * counters are zeroed when the DMA completes. If we can't start 1394 * the DMA immediately, we don't wait - we just prepare to read 1395 * them again next time. 1396 */ 1397 void 1398 fxp_tick(void *arg) 1399 { 1400 struct fxp_softc *sc = arg; 1401 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1402 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1403 int s; 1404 1405 if (!device_is_active(sc->sc_dev)) 1406 return; 1407 1408 s = splnet(); 1409 1410 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1411 1412 ifp->if_opackets += le32toh(sp->tx_good); 1413 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1414 if (sp->rx_good) { 1415 ifp->if_ipackets += le32toh(sp->rx_good); 1416 sc->sc_rxidle = 0; 1417 } else if (sc->sc_flags & FXPF_RECV_WORKAROUND) { 1418 sc->sc_rxidle++; 1419 } 1420 ifp->if_ierrors += 1421 le32toh(sp->rx_crc_errors) + 1422 le32toh(sp->rx_alignment_errors) + 1423 le32toh(sp->rx_rnr_errors) + 1424 le32toh(sp->rx_overrun_errors); 1425 /* 1426 * If any transmit underruns occurred, bump up the transmit 1427 * threshold by another 512 bytes (64 * 8). 1428 */ 1429 if (sp->tx_underruns) { 1430 ifp->if_oerrors += le32toh(sp->tx_underruns); 1431 if (tx_threshold < 192) 1432 tx_threshold += 64; 1433 } 1434 #ifdef FXP_EVENT_COUNTERS 1435 if (sc->sc_rev >= FXP_REV_82558_A4) { 1436 sc->sc_ev_txpause.ev_count += sp->tx_pauseframes; 1437 sc->sc_ev_rxpause.ev_count += sp->rx_pauseframes; 1438 } 1439 #endif 1440 1441 /* 1442 * If we haven't received any packets in FXP_MAX_RX_IDLE seconds, 1443 * then assume the receiver has locked up and attempt to clear 1444 * the condition by reprogramming the multicast filter (actually, 1445 * resetting the interface). This is a work-around for a bug in 1446 * the 82557 where the receiver locks up if it gets certain types 1447 * of garbage in the synchronization bits prior to the packet header. 1448 * This bug is supposed to only occur in 10Mbps mode, but has been 1449 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1450 * speed transition). 1451 */ 1452 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1453 (void) fxp_init(ifp); 1454 splx(s); 1455 return; 1456 } 1457 /* 1458 * If there is no pending command, start another stats 1459 * dump. Otherwise punt for now. 1460 */ 1461 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1462 /* 1463 * Start another stats dump. 1464 */ 1465 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1466 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1467 } else { 1468 /* 1469 * A previous command is still waiting to be accepted. 1470 * Just zero our copy of the stats and wait for the 1471 * next timer event to update them. 1472 */ 1473 /* BIG_ENDIAN: no swap required to store 0 */ 1474 sp->tx_good = 0; 1475 sp->tx_underruns = 0; 1476 sp->tx_total_collisions = 0; 1477 1478 sp->rx_good = 0; 1479 sp->rx_crc_errors = 0; 1480 sp->rx_alignment_errors = 0; 1481 sp->rx_rnr_errors = 0; 1482 sp->rx_overrun_errors = 0; 1483 if (sc->sc_rev >= FXP_REV_82558_A4) { 1484 sp->tx_pauseframes = 0; 1485 sp->rx_pauseframes = 0; 1486 } 1487 } 1488 1489 if (sc->sc_flags & FXPF_MII) { 1490 /* Tick the MII clock. */ 1491 mii_tick(&sc->sc_mii); 1492 } 1493 1494 splx(s); 1495 1496 /* 1497 * Schedule another timeout one second from now. 1498 */ 1499 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1500 } 1501 1502 /* 1503 * Drain the receive queue. 1504 */ 1505 void 1506 fxp_rxdrain(struct fxp_softc *sc) 1507 { 1508 bus_dmamap_t rxmap; 1509 struct mbuf *m; 1510 1511 for (;;) { 1512 IF_DEQUEUE(&sc->sc_rxq, m); 1513 if (m == NULL) 1514 break; 1515 rxmap = M_GETCTX(m, bus_dmamap_t); 1516 bus_dmamap_unload(sc->sc_dmat, rxmap); 1517 FXP_RXMAP_PUT(sc, rxmap); 1518 m_freem(m); 1519 } 1520 } 1521 1522 /* 1523 * Stop the interface. Cancels the statistics updater and resets 1524 * the interface. 1525 */ 1526 void 1527 fxp_stop(struct ifnet *ifp, int disable) 1528 { 1529 struct fxp_softc *sc = ifp->if_softc; 1530 struct fxp_txsoft *txs; 1531 int i; 1532 1533 /* 1534 * Turn down interface (done early to avoid bad interactions 1535 * between panics, shutdown hooks, and the watchdog timer) 1536 */ 1537 ifp->if_timer = 0; 1538 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1539 1540 /* 1541 * Cancel stats updater. 1542 */ 1543 callout_stop(&sc->sc_callout); 1544 if (sc->sc_flags & FXPF_MII) { 1545 /* Down the MII. */ 1546 mii_down(&sc->sc_mii); 1547 } 1548 1549 /* 1550 * Issue software reset. This unloads any microcode that 1551 * might already be loaded. 1552 */ 1553 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1554 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1555 DELAY(50); 1556 1557 /* 1558 * Release any xmit buffers. 1559 */ 1560 for (i = 0; i < FXP_NTXCB; i++) { 1561 txs = FXP_DSTX(sc, i); 1562 if (txs->txs_mbuf != NULL) { 1563 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1564 m_freem(txs->txs_mbuf); 1565 txs->txs_mbuf = NULL; 1566 } 1567 } 1568 sc->sc_txpending = 0; 1569 1570 if (disable) { 1571 fxp_rxdrain(sc); 1572 fxp_disable(sc); 1573 } 1574 1575 } 1576 1577 /* 1578 * Watchdog/transmission transmit timeout handler. Called when a 1579 * transmission is started on the interface, but no interrupt is 1580 * received before the timeout. This usually indicates that the 1581 * card has wedged for some reason. 1582 */ 1583 void 1584 fxp_watchdog(struct ifnet *ifp) 1585 { 1586 struct fxp_softc *sc = ifp->if_softc; 1587 1588 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1589 ifp->if_oerrors++; 1590 1591 (void) fxp_init(ifp); 1592 } 1593 1594 /* 1595 * Initialize the interface. Must be called at splnet(). 1596 */ 1597 int 1598 fxp_init(struct ifnet *ifp) 1599 { 1600 struct fxp_softc *sc = ifp->if_softc; 1601 struct fxp_cb_config *cbp; 1602 struct fxp_cb_ias *cb_ias; 1603 struct fxp_txdesc *txd; 1604 bus_dmamap_t rxmap; 1605 int i, prm, save_bf, lrxen, vlan_drop, allm, error = 0; 1606 uint16_t status; 1607 1608 if ((error = fxp_enable(sc)) != 0) 1609 goto out; 1610 1611 /* 1612 * Cancel any pending I/O 1613 */ 1614 fxp_stop(ifp, 0); 1615 1616 /* 1617 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1618 * flag, and this prevents the MII from detaching resulting in 1619 * a panic. The flags field should perhaps be split in runtime 1620 * flags and more static information. For now, just clear the 1621 * only other flag set. 1622 */ 1623 1624 sc->sc_flags &= ~FXPF_WANTINIT; 1625 1626 /* 1627 * Initialize base of CBL and RFA memory. Loading with zero 1628 * sets it up for regular linear addressing. 1629 */ 1630 fxp_scb_wait(sc); 1631 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1632 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1633 1634 fxp_scb_wait(sc); 1635 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1636 1637 /* 1638 * Initialize the multicast filter. Do this now, since we might 1639 * have to setup the config block differently. 1640 */ 1641 fxp_mc_setup(sc); 1642 1643 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1644 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1645 1646 /* 1647 * In order to support receiving 802.1Q VLAN frames, we have to 1648 * enable "save bad frames", since they are 4 bytes larger than 1649 * the normal Ethernet maximum frame length. On i82558 and later, 1650 * we have a better mechanism for this. 1651 */ 1652 save_bf = 0; 1653 lrxen = 0; 1654 vlan_drop = 0; 1655 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1656 if (sc->sc_rev < FXP_REV_82558_A4) 1657 save_bf = 1; 1658 else 1659 lrxen = 1; 1660 if (sc->sc_rev >= FXP_REV_82550) 1661 vlan_drop = 1; 1662 } 1663 1664 /* 1665 * Initialize base of dump-stats buffer. 1666 */ 1667 fxp_scb_wait(sc); 1668 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1669 sc->sc_cddma + FXP_CDSTATSOFF); 1670 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1671 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1672 1673 cbp = &sc->sc_control_data->fcd_configcb; 1674 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1675 1676 /* 1677 * Load microcode for this controller. 1678 */ 1679 fxp_load_ucode(sc); 1680 1681 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK1)) 1682 sc->sc_flags |= FXPF_RECV_WORKAROUND; 1683 else 1684 sc->sc_flags &= ~FXPF_RECV_WORKAROUND; 1685 1686 /* 1687 * This copy is kind of disgusting, but there are a bunch of must be 1688 * zero and must be one bits in this structure and this is the easiest 1689 * way to initialize them all to proper values. 1690 */ 1691 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1692 1693 /* BIG_ENDIAN: no need to swap to store 0 */ 1694 cbp->cb_status = 0; 1695 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1696 FXP_CB_COMMAND_EL); 1697 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1698 cbp->link_addr = 0xffffffff; /* (no) next command */ 1699 /* bytes in config block */ 1700 cbp->byte_count = (sc->sc_flags & FXPF_EXT_RFA) ? 1701 FXP_EXT_CONFIG_LEN : FXP_CONFIG_LEN; 1702 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1703 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1704 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1705 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1706 cbp->type_enable = 0; /* actually reserved */ 1707 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1708 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1709 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1710 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1711 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1712 cbp->late_scb = 0; /* (don't) defer SCB update */ 1713 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1714 cbp->ci_int = 1; /* interrupt on CU idle */ 1715 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1716 cbp->ext_stats_dis = 1; /* disable extended counters */ 1717 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1718 cbp->save_bf = save_bf;/* save bad frames */ 1719 cbp->disc_short_rx = !prm; /* discard short packets */ 1720 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1721 cbp->ext_rfa = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1722 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1723 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1724 /* interface mode */ 1725 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1726 cbp->csma_dis = 0; /* (don't) disable link */ 1727 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1728 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1729 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1730 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1731 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1732 cbp->nsai = 1; /* (don't) disable source addr insert */ 1733 cbp->preamble_length = 2; /* (7 byte) preamble */ 1734 cbp->loopback = 0; /* (don't) loopback */ 1735 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1736 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1737 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1738 cbp->promiscuous = prm; /* promiscuous mode */ 1739 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1740 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1741 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1742 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1743 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1744 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1745 cbp->padding = 1; /* (do) pad short tx packets */ 1746 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1747 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1748 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1749 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1750 /* must set wake_en in PMCSR also */ 1751 cbp->force_fdx = 0; /* (don't) force full duplex */ 1752 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1753 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1754 cbp->mc_all = allm; /* accept all multicasts */ 1755 cbp->ext_rx_mode = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1756 cbp->vlan_drop_en = vlan_drop; 1757 1758 if (sc->sc_rev < FXP_REV_82558_A4) { 1759 /* 1760 * The i82557 has no hardware flow control, the values 1761 * here are the defaults for the chip. 1762 */ 1763 cbp->fc_delay_lsb = 0; 1764 cbp->fc_delay_msb = 0x40; 1765 cbp->pri_fc_thresh = 3; 1766 cbp->tx_fc_dis = 0; 1767 cbp->rx_fc_restop = 0; 1768 cbp->rx_fc_restart = 0; 1769 cbp->fc_filter = 0; 1770 cbp->pri_fc_loc = 1; 1771 } else { 1772 cbp->fc_delay_lsb = 0x1f; 1773 cbp->fc_delay_msb = 0x01; 1774 cbp->pri_fc_thresh = 3; 1775 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1776 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1777 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1778 cbp->fc_filter = !prm; /* drop FC frames to host */ 1779 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1780 cbp->ext_stats_dis = 0; /* enable extended stats */ 1781 } 1782 1783 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1784 1785 /* 1786 * Start the config command/DMA. 1787 */ 1788 fxp_scb_wait(sc); 1789 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1790 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1791 /* ...and wait for it to complete. */ 1792 for (i = 1000; i > 0; i--) { 1793 FXP_CDCONFIGSYNC(sc, 1794 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1795 status = le16toh(cbp->cb_status); 1796 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD); 1797 if ((status & FXP_CB_STATUS_C) != 0) 1798 break; 1799 DELAY(1); 1800 } 1801 if (i == 0) { 1802 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1803 device_xname(sc->sc_dev), __LINE__); 1804 return (ETIMEDOUT); 1805 } 1806 1807 /* 1808 * Initialize the station address. 1809 */ 1810 cb_ias = &sc->sc_control_data->fcd_iascb; 1811 /* BIG_ENDIAN: no need to swap to store 0 */ 1812 cb_ias->cb_status = 0; 1813 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1814 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1815 cb_ias->link_addr = 0xffffffff; 1816 memcpy(cb_ias->macaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1817 1818 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1819 1820 /* 1821 * Start the IAS (Individual Address Setup) command/DMA. 1822 */ 1823 fxp_scb_wait(sc); 1824 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1825 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1826 /* ...and wait for it to complete. */ 1827 for (i = 1000; i > 0; i++) { 1828 FXP_CDIASSYNC(sc, 1829 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1830 status = le16toh(cb_ias->cb_status); 1831 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD); 1832 if ((status & FXP_CB_STATUS_C) != 0) 1833 break; 1834 DELAY(1); 1835 } 1836 if (i == 0) { 1837 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1838 device_xname(sc->sc_dev), __LINE__); 1839 return (ETIMEDOUT); 1840 } 1841 1842 /* 1843 * Initialize the transmit descriptor ring. txlast is initialized 1844 * to the end of the list so that it will wrap around to the first 1845 * descriptor when the first packet is transmitted. 1846 */ 1847 for (i = 0; i < FXP_NTXCB; i++) { 1848 txd = FXP_CDTX(sc, i); 1849 memset(txd, 0, sizeof(*txd)); 1850 txd->txd_txcb.cb_command = 1851 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1852 txd->txd_txcb.link_addr = 1853 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1854 if (sc->sc_flags & FXPF_EXT_TXCB) 1855 txd->txd_txcb.tbd_array_addr = 1856 htole32(FXP_CDTBDADDR(sc, i) + 1857 (2 * sizeof(struct fxp_tbd))); 1858 else 1859 txd->txd_txcb.tbd_array_addr = 1860 htole32(FXP_CDTBDADDR(sc, i)); 1861 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1862 } 1863 sc->sc_txpending = 0; 1864 sc->sc_txdirty = 0; 1865 sc->sc_txlast = FXP_NTXCB - 1; 1866 1867 /* 1868 * Initialize the receive buffer list. 1869 */ 1870 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1871 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1872 rxmap = FXP_RXMAP_GET(sc); 1873 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1874 log(LOG_ERR, "%s: unable to allocate or map rx " 1875 "buffer %d, error = %d\n", 1876 device_xname(sc->sc_dev), 1877 sc->sc_rxq.ifq_len, error); 1878 /* 1879 * XXX Should attempt to run with fewer receive 1880 * XXX buffers instead of just failing. 1881 */ 1882 FXP_RXMAP_PUT(sc, rxmap); 1883 fxp_rxdrain(sc); 1884 goto out; 1885 } 1886 } 1887 sc->sc_rxidle = 0; 1888 1889 /* 1890 * Give the transmit ring to the chip. We do this by pointing 1891 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1892 * issuing a start command. It will execute the NOP and then 1893 * suspend, pointing at the first descriptor. 1894 */ 1895 fxp_scb_wait(sc); 1896 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1897 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1898 1899 /* 1900 * Initialize receiver buffer area - RFA. 1901 */ 1902 #if 0 /* initialization will be done by FXP_SCB_INTRCNTL_REQUEST_SWI later */ 1903 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1904 fxp_scb_wait(sc); 1905 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1906 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1907 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1908 #endif 1909 1910 if (sc->sc_flags & FXPF_MII) { 1911 /* 1912 * Set current media. 1913 */ 1914 if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) 1915 goto out; 1916 } 1917 1918 /* 1919 * ...all done! 1920 */ 1921 ifp->if_flags |= IFF_RUNNING; 1922 ifp->if_flags &= ~IFF_OACTIVE; 1923 1924 /* 1925 * Request a software generated interrupt that will be used to 1926 * (re)start the RU processing. If we direct the chip to start 1927 * receiving from the start of queue now, instead of letting the 1928 * interrupt handler first process all received packets, we run 1929 * the risk of having it overwrite mbuf clusters while they are 1930 * being processed or after they have been returned to the pool. 1931 */ 1932 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTRCNTL_REQUEST_SWI); 1933 1934 /* 1935 * Start the one second timer. 1936 */ 1937 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1938 1939 /* 1940 * Attempt to start output on the interface. 1941 */ 1942 fxp_start(ifp); 1943 1944 out: 1945 if (error) { 1946 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1947 ifp->if_timer = 0; 1948 log(LOG_ERR, "%s: interface not running\n", 1949 device_xname(sc->sc_dev)); 1950 } 1951 return (error); 1952 } 1953 1954 /* 1955 * Notify the world which media we're using. 1956 */ 1957 void 1958 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1959 { 1960 struct fxp_softc *sc = ifp->if_softc; 1961 1962 if (sc->sc_enabled == 0) { 1963 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1964 ifmr->ifm_status = 0; 1965 return; 1966 } 1967 1968 ether_mediastatus(ifp, ifmr); 1969 1970 /* 1971 * XXX Flow control is always turned on if the chip supports 1972 * XXX it; we can't easily control it dynamically, since it 1973 * XXX requires sending a setup packet. 1974 */ 1975 if (sc->sc_rev >= FXP_REV_82558_A4) 1976 ifmr->ifm_active |= IFM_FLOW|IFM_ETH_TXPAUSE|IFM_ETH_RXPAUSE; 1977 } 1978 1979 int 1980 fxp_80c24_mediachange(struct ifnet *ifp) 1981 { 1982 1983 /* Nothing to do here. */ 1984 return (0); 1985 } 1986 1987 void 1988 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1989 { 1990 struct fxp_softc *sc = ifp->if_softc; 1991 1992 /* 1993 * Media is currently-selected media. We cannot determine 1994 * the link status. 1995 */ 1996 ifmr->ifm_status = 0; 1997 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1998 } 1999 2000 /* 2001 * Add a buffer to the end of the RFA buffer list. 2002 * Return 0 if successful, error code on failure. 2003 * 2004 * The RFA struct is stuck at the beginning of mbuf cluster and the 2005 * data pointer is fixed up to point just past it. 2006 */ 2007 int 2008 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 2009 { 2010 struct mbuf *m; 2011 int error; 2012 2013 MGETHDR(m, M_DONTWAIT, MT_DATA); 2014 if (m == NULL) 2015 return (ENOBUFS); 2016 2017 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2018 MCLGET(m, M_DONTWAIT); 2019 if ((m->m_flags & M_EXT) == 0) { 2020 m_freem(m); 2021 return (ENOBUFS); 2022 } 2023 2024 if (unload) 2025 bus_dmamap_unload(sc->sc_dmat, rxmap); 2026 2027 M_SETCTX(m, rxmap); 2028 2029 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2030 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, 2031 BUS_DMA_READ|BUS_DMA_NOWAIT); 2032 if (error) { 2033 /* XXX XXX XXX */ 2034 aprint_error_dev(sc->sc_dev, "can't load rx DMA map %d, error = %d\n", 2035 sc->sc_rxq.ifq_len, error); 2036 panic("fxp_add_rfabuf"); 2037 } 2038 2039 FXP_INIT_RFABUF(sc, m); 2040 2041 return (0); 2042 } 2043 2044 int 2045 fxp_mdi_read(device_t self, int phy, int reg) 2046 { 2047 struct fxp_softc *sc = device_private(self); 2048 int count = 10000; 2049 int value; 2050 2051 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2052 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2053 2054 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 2055 0x10000000) == 0 && count--) 2056 DELAY(10); 2057 2058 if (count <= 0) 2059 log(LOG_WARNING, 2060 "%s: fxp_mdi_read: timed out\n", device_xname(self)); 2061 2062 return (value & 0xffff); 2063 } 2064 2065 void 2066 fxp_statchg(device_t self) 2067 { 2068 2069 /* Nothing to do. */ 2070 } 2071 2072 void 2073 fxp_mdi_write(device_t self, int phy, int reg, int value) 2074 { 2075 struct fxp_softc *sc = device_private(self); 2076 int count = 10000; 2077 2078 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2079 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2080 (value & 0xffff)); 2081 2082 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2083 count--) 2084 DELAY(10); 2085 2086 if (count <= 0) 2087 log(LOG_WARNING, 2088 "%s: fxp_mdi_write: timed out\n", device_xname(self)); 2089 } 2090 2091 int 2092 fxp_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2093 { 2094 struct fxp_softc *sc = ifp->if_softc; 2095 struct ifreq *ifr = (struct ifreq *)data; 2096 int s, error; 2097 2098 s = splnet(); 2099 2100 switch (cmd) { 2101 case SIOCSIFMEDIA: 2102 case SIOCGIFMEDIA: 2103 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2104 break; 2105 2106 default: 2107 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 2108 break; 2109 2110 error = 0; 2111 2112 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2113 ; 2114 else if (ifp->if_flags & IFF_RUNNING) { 2115 /* 2116 * Multicast list has changed; set the 2117 * hardware filter accordingly. 2118 */ 2119 while (sc->sc_txpending) { 2120 sc->sc_flags |= FXPF_WANTINIT; 2121 tsleep(sc, PSOCK, "fxp_init", 0); 2122 } 2123 error = fxp_init(ifp); 2124 } 2125 break; 2126 } 2127 2128 /* Try to get more packets going. */ 2129 if (sc->sc_enabled) 2130 fxp_start(ifp); 2131 2132 splx(s); 2133 return (error); 2134 } 2135 2136 /* 2137 * Program the multicast filter. 2138 * 2139 * This function must be called at splnet(). 2140 */ 2141 void 2142 fxp_mc_setup(struct fxp_softc *sc) 2143 { 2144 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 2145 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2146 struct ethercom *ec = &sc->sc_ethercom; 2147 struct ether_multi *enm; 2148 struct ether_multistep step; 2149 int count, nmcasts; 2150 uint16_t status; 2151 2152 #ifdef DIAGNOSTIC 2153 if (sc->sc_txpending) 2154 panic("fxp_mc_setup: pending transmissions"); 2155 #endif 2156 2157 ifp->if_flags &= ~IFF_ALLMULTI; 2158 2159 /* 2160 * Initialize multicast setup descriptor. 2161 */ 2162 nmcasts = 0; 2163 ETHER_FIRST_MULTI(step, ec, enm); 2164 while (enm != NULL) { 2165 /* 2166 * Check for too many multicast addresses or if we're 2167 * listening to a range. Either way, we simply have 2168 * to accept all multicasts. 2169 */ 2170 if (nmcasts >= MAXMCADDR || 2171 memcmp(enm->enm_addrlo, enm->enm_addrhi, 2172 ETHER_ADDR_LEN) != 0) { 2173 /* 2174 * Callers of this function must do the 2175 * right thing with this. If we're called 2176 * from outside fxp_init(), the caller must 2177 * detect if the state if IFF_ALLMULTI changes. 2178 * If it does, the caller must then call 2179 * fxp_init(), since allmulti is handled by 2180 * the config block. 2181 */ 2182 ifp->if_flags |= IFF_ALLMULTI; 2183 return; 2184 } 2185 memcpy(&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 2186 ETHER_ADDR_LEN); 2187 nmcasts++; 2188 ETHER_NEXT_MULTI(step, enm); 2189 } 2190 2191 /* BIG_ENDIAN: no need to swap to store 0 */ 2192 mcsp->cb_status = 0; 2193 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2194 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2195 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2196 2197 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2198 2199 /* 2200 * Wait until the command unit is not active. This should never 2201 * happen since nothing is queued, but make sure anyway. 2202 */ 2203 count = 100; 2204 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2205 FXP_SCB_CUS_ACTIVE && --count) 2206 DELAY(1); 2207 if (count == 0) { 2208 log(LOG_WARNING, "%s: line %d: command queue timeout\n", 2209 device_xname(sc->sc_dev), __LINE__); 2210 return; 2211 } 2212 2213 /* 2214 * Start the multicast setup command/DMA. 2215 */ 2216 fxp_scb_wait(sc); 2217 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2218 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2219 2220 /* ...and wait for it to complete. */ 2221 for (count = 1000; count > 0; count--) { 2222 FXP_CDMCSSYNC(sc, 2223 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2224 status = le16toh(mcsp->cb_status); 2225 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD); 2226 if ((status & FXP_CB_STATUS_C) != 0) 2227 break; 2228 DELAY(1); 2229 } 2230 if (count == 0) { 2231 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 2232 device_xname(sc->sc_dev), __LINE__); 2233 return; 2234 } 2235 } 2236 2237 static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2238 static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2239 static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2240 static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2241 static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2242 static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2243 2244 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2245 2246 static const struct ucode { 2247 int32_t revision; 2248 const uint32_t *ucode; 2249 size_t length; 2250 uint16_t int_delay_offset; 2251 uint16_t bundle_max_offset; 2252 } ucode_table[] = { 2253 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2254 D101_CPUSAVER_DWORD, 0 }, 2255 2256 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2257 D101_CPUSAVER_DWORD, 0 }, 2258 2259 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2260 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2261 2262 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2263 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2264 2265 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2266 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2267 2268 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2269 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2270 2271 { 0, NULL, 0, 0, 0 } 2272 }; 2273 2274 void 2275 fxp_load_ucode(struct fxp_softc *sc) 2276 { 2277 const struct ucode *uc; 2278 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2279 int count, i; 2280 uint16_t status; 2281 2282 if (sc->sc_flags & FXPF_UCODE_LOADED) 2283 return; 2284 2285 /* 2286 * Only load the uCode if the user has requested that 2287 * we do so. 2288 */ 2289 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2290 sc->sc_int_delay = 0; 2291 sc->sc_bundle_max = 0; 2292 return; 2293 } 2294 2295 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2296 if (sc->sc_rev == uc->revision) 2297 break; 2298 } 2299 if (uc->ucode == NULL) 2300 return; 2301 2302 /* BIG ENDIAN: no need to swap to store 0 */ 2303 cbp->cb_status = 0; 2304 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2305 cbp->link_addr = 0xffffffff; /* (no) next command */ 2306 for (i = 0; i < uc->length; i++) 2307 cbp->ucode[i] = htole32(uc->ucode[i]); 2308 2309 if (uc->int_delay_offset) 2310 *(volatile uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2311 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2312 2313 if (uc->bundle_max_offset) 2314 *(volatile uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2315 htole16(fxp_bundle_max); 2316 2317 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2318 2319 /* 2320 * Download the uCode to the chip. 2321 */ 2322 fxp_scb_wait(sc); 2323 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2324 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2325 2326 /* ...and wait for it to complete. */ 2327 for (count = 10000; count > 0; count--) { 2328 FXP_CDUCODESYNC(sc, 2329 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2330 status = le16toh(cbp->cb_status); 2331 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD); 2332 if ((status & FXP_CB_STATUS_C) != 0) 2333 break; 2334 DELAY(2); 2335 } 2336 if (count == 0) { 2337 sc->sc_int_delay = 0; 2338 sc->sc_bundle_max = 0; 2339 log(LOG_WARNING, "%s: timeout loading microcode\n", 2340 device_xname(sc->sc_dev)); 2341 return; 2342 } 2343 2344 if (sc->sc_int_delay != fxp_int_delay || 2345 sc->sc_bundle_max != fxp_bundle_max) { 2346 sc->sc_int_delay = fxp_int_delay; 2347 sc->sc_bundle_max = fxp_bundle_max; 2348 log(LOG_INFO, "%s: Microcode loaded: int delay: %d usec, " 2349 "max bundle: %d\n", device_xname(sc->sc_dev), 2350 sc->sc_int_delay, 2351 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2352 } 2353 2354 sc->sc_flags |= FXPF_UCODE_LOADED; 2355 } 2356 2357 int 2358 fxp_enable(struct fxp_softc *sc) 2359 { 2360 2361 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2362 if ((*sc->sc_enable)(sc) != 0) { 2363 log(LOG_ERR, "%s: device enable failed\n", 2364 device_xname(sc->sc_dev)); 2365 return (EIO); 2366 } 2367 } 2368 2369 sc->sc_enabled = 1; 2370 return (0); 2371 } 2372 2373 void 2374 fxp_disable(struct fxp_softc *sc) 2375 { 2376 2377 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2378 (*sc->sc_disable)(sc); 2379 sc->sc_enabled = 0; 2380 } 2381 } 2382 2383 /* 2384 * fxp_activate: 2385 * 2386 * Handle device activation/deactivation requests. 2387 */ 2388 int 2389 fxp_activate(device_t self, enum devact act) 2390 { 2391 struct fxp_softc *sc = device_private(self); 2392 int s, error = 0; 2393 2394 s = splnet(); 2395 switch (act) { 2396 case DVACT_ACTIVATE: 2397 error = EOPNOTSUPP; 2398 break; 2399 2400 case DVACT_DEACTIVATE: 2401 if (sc->sc_flags & FXPF_MII) 2402 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 2403 MII_OFFSET_ANY); 2404 if_deactivate(&sc->sc_ethercom.ec_if); 2405 break; 2406 } 2407 splx(s); 2408 2409 return (error); 2410 } 2411 2412 /* 2413 * fxp_detach: 2414 * 2415 * Detach an i82557 interface. 2416 */ 2417 int 2418 fxp_detach(struct fxp_softc *sc) 2419 { 2420 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2421 int i; 2422 2423 /* Succeed now if there's no work to do. */ 2424 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2425 return (0); 2426 2427 /* Unhook our tick handler. */ 2428 callout_stop(&sc->sc_callout); 2429 2430 if (sc->sc_flags & FXPF_MII) { 2431 /* Detach all PHYs */ 2432 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2433 } 2434 2435 /* Delete all remaining media. */ 2436 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2437 2438 #if NRND > 0 2439 rnd_detach_source(&sc->rnd_source); 2440 #endif 2441 ether_ifdetach(ifp); 2442 if_detach(ifp); 2443 2444 for (i = 0; i < FXP_NRFABUFS; i++) { 2445 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2446 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2447 } 2448 2449 for (i = 0; i < FXP_NTXCB; i++) { 2450 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2451 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2452 } 2453 2454 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2455 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2456 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 2457 sizeof(struct fxp_control_data)); 2458 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2459 2460 return (0); 2461 }
Cache object: 4de5dccfc5d2b45a82900248c2a131bd
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]