FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/i82557reg.h
1 /* $NetBSD: i82557reg.h,v 1.18.24.1 2008/02/02 23:16:03 riz Exp $ */
2
3 /*-
4 * Copyright (c) 1998, 1999, 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the NetBSD
22 * Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40 /*
41 * Copyright (c) 1995, David Greenman
42 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
43 * All rights reserved.
44 *
45 * Redistribution and use in source and binary forms, with or without
46 * modification, are permitted provided that the following conditions
47 * are met:
48 * 1. Redistributions of source code must retain the above copyright
49 * notice unmodified, this list of conditions, and the following
50 * disclaimer.
51 * 2. Redistributions in binary form must reproduce the above copyright
52 * notice, this list of conditions and the following disclaimer in the
53 * documentation and/or other materials provided with the distribution.
54 *
55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
65 * SUCH DAMAGE.
66 *
67 * Id: if_fxpreg.h,v 1.24 2001/05/15 18:52:40 jlemon Exp
68 */
69
70 #define FXP_PCI_MMBA 0x10
71 #define FXP_PCI_IOBA 0x14
72
73 /*
74 * Control/status registers.
75 */
76 #define FXP_CSR_SCB_RUSCUS 0x00 /* scb_rus/scb_cus (1 byte) */
77 #define FXP_CSR_SCB_STATACK 0x01 /* scb_statack (1 byte) */
78 #define FXP_CSR_SCB_COMMAND 0x02 /* scb_command (1 byte) */
79 #define FXP_CSR_SCB_INTRCNTL 0x03 /* scb_intrcntl (1 byte) */
80 #define FXP_CSR_SCB_GENERAL 0x04 /* scb_general (4 bytes) */
81 #define FXP_CSR_PORT 0x08 /* port (4 bytes) */
82 #define FXP_CSR_FLASHCONTROL 0x0c /* flash control (2 bytes) */
83 #define FXP_CSR_EEPROMCONTROL 0x0e /* eeprom control (2 bytes) */
84 #define FXP_CSR_MDICONTROL 0x10 /* mdi control (4 bytes) */
85 #define FXP_CSR_FLOWCONTROL 0x19 /* flow control (2 bytes) */
86
87 /*
88 * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS:
89 *
90 * volatile u_int8_t :2,
91 * scb_rus:4,
92 * scb_cus:2;
93 */
94
95 #define FXP_PORT_SOFTWARE_RESET 0
96 #define FXP_PORT_SELFTEST 1
97 #define FXP_PORT_SELECTIVE_RESET 2
98 #define FXP_PORT_DUMP 3
99
100 #define FXP_SCB_RUS_IDLE 0
101 #define FXP_SCB_RUS_SUSPENDED 1
102 #define FXP_SCB_RUS_NORESOURCES 2
103 #define FXP_SCB_RUS_READY 4
104 #define FXP_SCB_RUS_SUSP_NORBDS 9
105 #define FXP_SCB_RUS_NORES_NORBDS 10
106 #define FXP_SCB_RUS_READY_NORBDS 12
107
108 #define FXP_SCB_CUS_IDLE 0
109 #define FXP_SCB_CUS_SUSPENDED 1
110 #define FXP_SCB_CUS_ACTIVE 2
111
112 #define FXP_SCB_INTR_DISABLE 0x01 /* disable all interrupts */
113 #define FXP_SCB_INTR_SWI 0x02 /* generate SWI */
114 #define FXP_SCB_INTMASK_FCP 0x04
115 #define FXP_SCB_INTMASK_ER 0x08
116 #define FXP_SCB_INTMASK_RNR 0x10
117 #define FXP_SCB_INTMASK_CNA 0x20
118 #define FXP_SCB_INTMASK_FR 0x40
119 #define FXP_SCB_INTMASK_CXTNO 0x80
120
121 #define FXP_SCB_STATACK_FCP 0x01 /* flow control pause */
122 #define FXP_SCB_STATACK_ER 0x02 /* early receive */
123 #define FXP_SCB_STATACK_SWI 0x04
124 #define FXP_SCB_STATACK_MDI 0x08
125 #define FXP_SCB_STATACK_RNR 0x10
126 #define FXP_SCB_STATACK_CNA 0x20
127 #define FXP_SCB_STATACK_FR 0x40
128 #define FXP_SCB_STATACK_CXTNO 0x80
129
130 #define FXP_SCB_COMMAND_CU_NOP 0x00
131 #define FXP_SCB_COMMAND_CU_START 0x10
132 #define FXP_SCB_COMMAND_CU_RESUME 0x20
133 #define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40
134 #define FXP_SCB_COMMAND_CU_DUMP 0x50
135 #define FXP_SCB_COMMAND_CU_BASE 0x60
136 #define FXP_SCB_COMMAND_CU_DUMPRESET 0x70
137
138 #define FXP_SCB_COMMAND_RU_NOP 0
139 #define FXP_SCB_COMMAND_RU_START 1
140 #define FXP_SCB_COMMAND_RU_RESUME 2
141 #define FXP_SCB_COMMAND_RU_ABORT 4
142 #define FXP_SCB_COMMAND_RU_LOADHDS 5
143 #define FXP_SCB_COMMAND_RU_BASE 6
144 #define FXP_SCB_COMMAND_RU_RBDRESUME 7
145
146 #define FXP_SCB_INTRCNTL_REQUEST_SWI 0x02
147 /*
148 * Command block definitions
149 */
150
151 /*
152 * NOP command.
153 */
154 struct fxp_cb_nop {
155 volatile u_int16_t cb_status;
156 volatile u_int16_t cb_command;
157 volatile u_int32_t link_addr;
158 };
159
160 /*
161 * Individual Address command.
162 */
163 struct fxp_cb_ias {
164 volatile u_int16_t cb_status;
165 volatile u_int16_t cb_command;
166 volatile u_int32_t link_addr;
167 u_int8_t macaddr[6];
168 };
169
170 #if BYTE_ORDER == LITTLE_ENDIAN
171 #define __FXP_BITFIELD2(a, b) a, b
172 #define __FXP_BITFIELD3(a, b, c) a, b, c
173 #define __FXP_BITFIELD4(a, b, c, d) a, b, c, d
174 #define __FXP_BITFIELD5(a, b, c, d, e) a, b, c, d, e
175 #define __FXP_BITFIELD6(a, b, c, d, e, f) a, b, c, d, e, f
176 #define __FXP_BITFIELD7(a, b, c, d, e, f, g) a, b, c, d, e, f, g
177 #define __FXP_BITFIELD8(a, b, c, d, e, f, g, h) a, b, c, d, e, f, g, h
178 #else
179 #define __FXP_BITFIELD2(a, b) b, a
180 #define __FXP_BITFIELD3(a, b, c) c, b, a
181 #define __FXP_BITFIELD4(a, b, c, d) d, c, b, a
182 #define __FXP_BITFIELD5(a, b, c, d, e) e, d, c, b, a
183 #define __FXP_BITFIELD6(a, b, c, d, e, f) f, e, d, c, b, a
184 #define __FXP_BITFIELD7(a, b, c, d, e, f, g) g, f, e, d, c, b, a
185 #define __FXP_BITFIELD8(a, b, c, d, e, f, g, h) h, g, f, e, d, c, b, a
186 #endif
187
188 /*
189 * Configure command.
190 */
191 struct fxp_cb_config {
192 volatile u_int16_t cb_status;
193 volatile u_int16_t cb_command;
194 volatile u_int32_t link_addr;
195
196 /* Bytes 0 - 21 -- common to all i8255x */
197 /**/ volatile u_int8_t __FXP_BITFIELD2(byte_count:6, :2);
198 /*1*/ volatile u_int8_t __FXP_BITFIELD3(rx_fifo_limit:4,
199 tx_fifo_limit:3,
200 :1);
201 /*2*/ volatile u_int8_t adaptive_ifs;
202 /*3*/ volatile u_int8_t __FXP_BITFIELD5(mwi_enable:1, /* 8,9 */
203 type_enable:1, /* 8,9 */
204 read_align_en:1, /* 8,9 */
205 end_wr_on_cl:1, /* 8,9 */
206 :4);
207 /*4*/ volatile u_int8_t __FXP_BITFIELD2(rx_dma_bytecount:7,
208 :1);
209 /*5*/ volatile u_int8_t __FXP_BITFIELD2(tx_dma_bytecount:7,
210 dma_mbce:1);
211 /*6*/ volatile u_int8_t __FXP_BITFIELD8(late_scb:1, /* 7 */
212 direct_dma_dis:1, /* 8,9 */
213 tno_int_or_tco_en:1, /* 7,9 */
214 ci_int:1,
215 ext_txcb_dis:1, /* 8,9 */
216 ext_stats_dis:1, /* 8,9 */
217 keep_overrun_rx:1,
218 save_bf:1);
219 /*7*/ volatile u_int8_t __FXP_BITFIELD6(disc_short_rx:1,
220 underrun_retry:2,
221 :2,
222 ext_rfa:1, /* 0 */
223 two_frames:1, /* 8,9 */
224 dyn_tbd:1); /* 8,9 */
225 /*8*/ volatile u_int8_t __FXP_BITFIELD3(mediatype:1, /* 7 */
226 :6,
227 csma_dis:1); /* 8,9 */
228 /*9*/ volatile u_int8_t __FXP_BITFIELD6(tcp_udp_cksum:1,/* 9 */
229 :3,
230 vlan_tco:1, /* 8,9 */
231 link_wake_en:1, /* 8,9 */
232 arp_wake_en:1, /* 8 */
233 mc_wake_en:1); /* 8 */
234 /*10*/ volatile u_int8_t __FXP_BITFIELD4(:3,
235 nsai:1,
236 preamble_length:2,
237 loopback:2);
238 /*11*/ volatile u_int8_t __FXP_BITFIELD2(linear_priority:3,/* 7 */
239 :5);
240 /*12*/ volatile u_int8_t __FXP_BITFIELD3(linear_pri_mode:1,/* 7 */
241 :3,
242 interfrm_spacing:4);
243 /*13*/ volatile u_int8_t :8;
244 /*14*/ volatile u_int8_t :8;
245 /*15*/ volatile u_int8_t __FXP_BITFIELD8(promiscuous:1,
246 bcast_disable:1,
247 wait_after_win:1, /* 8,9 */
248 :1,
249 ignore_ul:1, /* 8,9 */
250 crc16_en:1, /* 9 */
251 :1,
252 crscdt:1);
253 /*16*/ volatile u_int8_t fc_delay_lsb:8; /* 8,9 */
254 /*17*/ volatile u_int8_t fc_delay_msb:8; /* 8,9 */
255 /*18*/ volatile u_int8_t __FXP_BITFIELD6(stripping:1,
256 padding:1,
257 rcv_crc_xfer:1,
258 long_rx_en:1, /* 8,9 */
259 pri_fc_thresh:3, /* 8,9 */
260 :1);
261 /*19*/ volatile u_int8_t __FXP_BITFIELD8(ia_wake_en:1, /* 8 */
262 magic_pkt_dis:1, /* 8,9,!9ER */
263 tx_fc_dis:1, /* 8,9 */
264 rx_fc_restop:1, /* 8,9 */
265 rx_fc_restart:1, /* 8,9 */
266 fc_filter:1, /* 8,9 */
267 force_fdx:1,
268 fdx_pin_en:1);
269 /*20*/ volatile u_int8_t __FXP_BITFIELD4(:5,
270 pri_fc_loc:1 /* 8,9 */,
271 multi_ia:1,
272 :1);
273 /*21*/ volatile u_int8_t __FXP_BITFIELD3(:3, mc_all:1, :4);
274
275 /* Bytes 22 - 31 -- i82550 only */
276 /*22*/ volatile u_int8_t __FXP_BITFIELD3(ext_rx_mode:1,
277 vlan_drop_en:1,
278 :6);
279 volatile u_int8_t reserved[9];
280 };
281
282 #define FXP_CONFIG_LEN 22 /* i8255x */
283 #define FXP_EXT_CONFIG_LEN 32 /* i82550 */
284
285 /*
286 * Multicast setup command.
287 */
288 #define MAXMCADDR 80
289 struct fxp_cb_mcs {
290 volatile u_int16_t cb_status;
291 volatile u_int16_t cb_command;
292 volatile u_int32_t link_addr;
293 volatile u_int16_t mc_cnt;
294 u_int8_t mc_addr[MAXMCADDR][6];
295 };
296
297 #define MAXUCODESIZE 192
298 struct fxp_cb_ucode {
299 volatile u_int16_t cb_status;
300 volatile u_int16_t cb_command;
301 volatile u_int32_t link_addr;
302 u_int32_t ucode[MAXUCODESIZE];
303 };
304
305 struct fxp_ipcb {
306 /*
307 * The following fields are valid only when
308 * using the IPCB command block for TX checksum offload
309 * (and TCP large send, VLANs, and (I think) IPsec). To use
310 * them, you must enable extended TxCBs (available only
311 * on the 82559 and later) and use the IPCBXMIT command.
312 * Note that Intel defines the IPCB to be 32 bytes long,
313 * the last 8 bytes of which comprise the first entry
314 * in the TBD array. This means we only have to define
315 * 8 extra bytes here.
316 */
317 volatile u_int16_t ipcb_schedule_low;
318 volatile u_int8_t ipcb_ip_schedule;
319 volatile u_int8_t ipcb_ip_activation_high;
320 volatile u_int16_t ipcb_vlan_id;
321 volatile u_int8_t ipcb_ip_header_offset;
322 volatile u_int8_t ipcb_tcp_header_offset;
323 };
324
325 /*
326 * IPCB field definitions
327 */
328 /* for ipcb_ip_schedule */
329 #define FXP_IPCB_IP_CHECKSUM_ENABLE 0x10
330 #define FXP_IPCB_TCPUDP_CHECKSUM_ENABLE 0x20
331 #define FXP_IPCB_TCP_PACKET 0x40
332 #define FXP_IPCB_LARGESEND_ENABLE 0x80
333 /* for ipcb_ip_activation_high */
334 #define FXP_IPCB_HARDWAREPARSING_ENABLE 0x01
335 #define FXP_IPCB_INSERTVLAN_ENABLE 0x02
336
337 /*
338 * Transmit command.
339 */
340 struct fxp_cb_tx {
341 volatile u_int16_t cb_status;
342 volatile u_int16_t cb_command;
343 volatile u_int32_t link_addr;
344 volatile u_int32_t tbd_array_addr;
345 volatile u_int16_t byte_count;
346 volatile u_int8_t tx_threshold;
347 volatile u_int8_t tbd_number;
348 /*
349 * If using the extended TxCB feature, there is a
350 * two TBDs right here. We handle this in the
351 * fxp_control_data in i82557var.h.
352 */
353 };
354
355 /*
356 * Transmit buffer descriptors.
357 */
358 struct fxp_tbd {
359 volatile u_int32_t tb_addr;
360 volatile u_int32_t tb_size;
361 };
362
363 /*
364 * Control Block (CB) definitions
365 */
366
367 /* status */
368 #define FXP_CB_STATUS_OK 0x2000
369 #define FXP_CB_STATUS_C 0x8000
370
371 /* commands */
372 #define FXP_CB_COMMAND_CMD 0x0007 /* XXX how about FXPF_IPCB case? */
373 #define FXP_CB_COMMAND_NOP 0x0
374 #define FXP_CB_COMMAND_IAS 0x1
375 #define FXP_CB_COMMAND_CONFIG 0x2
376 #define FXP_CB_COMMAND_MCAS 0x3
377 #define FXP_CB_COMMAND_XMIT 0x4
378 #define FXP_CB_COMMAND_UCODE 0x5
379 #define FXP_CB_COMMAND_DUMP 0x6
380 #define FXP_CB_COMMAND_DIAG 0x7
381 #define FXP_CB_COMMAND_IPCBXMIT 0x9
382
383 /* command flags */
384 #define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */
385 #define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */
386 #define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */
387 #define FXP_CB_COMMAND_EL 0x8000 /* end of list */
388
389 /*
390 * Receive Frame Area.
391 *
392 * NOTE! The RFA will NOT be aligned on a 4-byte boundary in the DMA
393 * area! To prevent EGCS from optimizing the copy of link_addr and
394 * rbd_addr (which would cause an unaligned access fault on RISC systems),
395 * we must make them an array of bytes!
396 */
397 struct fxp_rfa {
398 /* Fields common to all i8255x chips. */
399 volatile u_int16_t rfa_status;
400 volatile u_int16_t rfa_control;
401 volatile u_int8_t link_addr[4];
402 volatile u_int8_t rbd_addr[4];
403 volatile u_int16_t actual_size;
404 volatile u_int16_t size;
405
406 /* Fields available only on the i82550/i82551 in extended RFD mode. */
407 volatile u_int16_t vlan_id;
408 volatile u_int8_t rx_parse_stat;
409 volatile u_int8_t reserved;
410 volatile u_int16_t security_stat;
411 volatile u_int8_t cksum_stat;
412 volatile u_int8_t zerocopy_stat;
413 volatile u_int8_t unused[8];
414 };
415
416 #define RFA_SIZE 16
417 #define RFA_EXT_SIZE 32
418
419 #define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */
420 #define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */
421 #define FXP_RFA_STATUS_NOAMATCH 0x0004 /* 1 = doesn't match anything */
422 #define FXP_RFA_STATUS_PARSE 0x0008 /* pkt parse ok (82550/1 only) */
423 #define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */
424 #define FXP_RFA_STATUS_TL 0x0020 /* type/length */
425 #define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */
426 #define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */
427 #define FXP_RFA_STATUS_RNR 0x0200 /* no resources */
428 #define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */
429 #define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */
430 #define FXP_RFA_STATUS_VLAN 0x1000 /* VLAN */
431 #define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */
432 #define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */
433
434 #define FXP_RFA_CONTROL_SF 0x0008 /* simple/flexible memory mode */
435 #define FXP_RFA_CONTROL_H 0x0010 /* header RFD */
436 #define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */
437 #define FXP_RFA_CONTROL_EL 0x8000 /* end of list */
438
439 /* Bits in the 'cksum_stat' byte */
440 #define FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID 0x10
441 #define FXP_RFDX_CS_TCPUDP_CSUM_VALID 0x20
442 #define FXP_RFDX_CS_IP_CSUM_BIT_VALID 0x01
443 #define FXP_RFDX_CS_IP_CSUM_VALID 0x02
444
445 /* Bits in the 'rx_parse_stat' byte */
446 #define FXP_RFDX_P_PARSE_BIT 0x08
447 #define FXP_RFDX_P_CSUM_PROTOCOL_MASK 0x03
448 #define FXP_RFDX_P_TCP_PACKET 0x00
449 #define FXP_RFDX_P_UDP_PACKET 0x01
450 #define FXP_RFDX_P_IP_PACKET 0x03
451
452 /*
453 * Statistics dump area definitions
454 */
455 struct fxp_stats {
456 volatile u_int32_t tx_good;
457 volatile u_int32_t tx_maxcols;
458 volatile u_int32_t tx_latecols;
459 volatile u_int32_t tx_underruns;
460 volatile u_int32_t tx_lostcrs;
461 volatile u_int32_t tx_deferred;
462 volatile u_int32_t tx_single_collisions;
463 volatile u_int32_t tx_multiple_collisions;
464 volatile u_int32_t tx_total_collisions;
465 volatile u_int32_t rx_good;
466 volatile u_int32_t rx_crc_errors;
467 volatile u_int32_t rx_alignment_errors;
468 volatile u_int32_t rx_rnr_errors;
469 volatile u_int32_t rx_overrun_errors;
470 volatile u_int32_t rx_cdt_errors;
471 volatile u_int32_t rx_shortframes;
472 volatile u_int32_t tx_pauseframes;
473 #define completion_status tx_pauseframes
474 volatile u_int32_t rx_pauseframes;
475 volatile u_int32_t rx_unsupportedframes;
476 volatile u_int32_t tx_tco_frames;
477 volatile u_int32_t rx_tco_frames;
478 volatile u_int32_t ext_completion_status;
479 };
480 #define FXP_STATS_DUMP_COMPLETE 0xa005
481 #define FXP_STATS_DR_COMPLETE 0xa007
482
483 /*
484 * Serial EEPROM control register bits
485 */
486 #define FXP_EEPROM_EESK 0x01 /* shift clock */
487 #define FXP_EEPROM_EECS 0x02 /* chip select */
488 #define FXP_EEPROM_EEDI 0x04 /* data in */
489 #define FXP_EEPROM_EEDO 0x08 /* data out */
490
491 /*
492 * Serial EEPROM opcodes, including start bit
493 */
494 #define FXP_EEPROM_OPC_ERASE 0x4
495 #define FXP_EEPROM_OPC_WRITE 0x5
496 #define FXP_EEPROM_OPC_READ 0x6
497
498 /*
499 * Management Data Interface opcodes
500 */
501 #define FXP_MDI_WRITE 0x1
502 #define FXP_MDI_READ 0x2
503
504 /*
505 * PHY device types (from EEPROM)
506 */
507 #define FXP_PHY_DEVICE_MASK 0x3f00
508 #define FXP_PHY_DEVICE_SHIFT 8
509 #define FXP_PHY_DEVADDR_MASK 0x00ff
510 #define FXP_PHY_SERIAL_ONLY 0x8000
511 #define FXP_PHY_NONE 0
512 #define FXP_PHY_82553A 1
513 #define FXP_PHY_82553C 2
514 #define FXP_PHY_82503 3
515 #define FXP_PHY_DP83840 4
516 #define FXP_PHY_80C240 5
517 #define FXP_PHY_80C24 6
518 #define FXP_PHY_82555 7
519 #define FXP_PHY_DP83840A 10
520 #define FXP_PHY_DP82555B 11
521
522 /*
523 * PCI revisions.
524 */
525 #define FXP_REV_82558_A4 4
526 #define FXP_REV_82558_B0 5
527 #define FXP_REV_82559_A0 8
528 #define FXP_REV_82559S_A 9
529 #define FXP_REV_82550 12
530 #define FXP_REV_82550_C 13
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