The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/i82557var.h

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    1 /*      $NetBSD: i82557var.h,v 1.35.24.1 2008/02/02 23:16:03 riz Exp $  */
    2 
    3 /*-
    4  * Copyright (c) 1997, 1998, 1999, 2001 The NetBSD Foundation, Inc.
    5  * All rights reserved.
    6  *
    7  * This code is derived from software contributed to The NetBSD Foundation
    8  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
    9  * NASA Ames Research Center.
   10  *
   11  * Redistribution and use in source and binary forms, with or without
   12  * modification, are permitted provided that the following conditions
   13  * are met:
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions and the following disclaimer.
   16  * 2. Redistributions in binary form must reproduce the above copyright
   17  *    notice, this list of conditions and the following disclaimer in the
   18  *    documentation and/or other materials provided with the distribution.
   19  * 3. All advertising materials mentioning features or use of this software
   20  *    must display the following acknowledgement:
   21  *      This product includes software developed by the NetBSD
   22  *      Foundation, Inc. and its contributors.
   23  * 4. Neither the name of The NetBSD Foundation nor the names of its
   24  *    contributors may be used to endorse or promote products derived
   25  *    from this software without specific prior written permission.
   26  *
   27  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   29  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   30  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   37  * POSSIBILITY OF SUCH DAMAGE.
   38  */
   39 
   40 /*
   41  * Copyright (c) 1995, David Greenman
   42  * All rights reserved.
   43  *
   44  * Redistribution and use in source and binary forms, with or without
   45  * modification, are permitted provided that the following conditions
   46  * are met:
   47  * 1. Redistributions of source code must retain the above copyright
   48  *    notice unmodified, this list of conditions, and the following
   49  *    disclaimer.
   50  * 2. Redistributions in binary form must reproduce the above copyright
   51  *    notice, this list of conditions and the following disclaimer in the
   52  *    documentation and/or other materials provided with the distribution.
   53  *
   54  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   55  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   56  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   57  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   58  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   59  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   60  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   61  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   62  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   63  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   64  * SUCH DAMAGE.
   65  *
   66  *      Id: if_fxpvar.h,v 1.4 1997/11/29 08:11:01 davidg Exp
   67  */
   68 
   69 #include <sys/callout.h>
   70 
   71 /*
   72  * Misc. definitions for the Intel i82557 fast Ethernet controller
   73  * driver.
   74  */
   75 
   76 /*
   77  * Transmit descriptor list size.
   78  */
   79 #define FXP_NTXCB               256
   80 #define FXP_NTXCB_MASK          (FXP_NTXCB - 1)
   81 #define FXP_NEXTTX(x)           ((x + 1) & FXP_NTXCB_MASK)
   82 #define FXP_NTXSEG              16
   83 #define FXP_IPCB_NTXSEG         (FXP_NTXSEG - 1)
   84 
   85 /*
   86  * Number of receive frame area buffers.  These are large, so
   87  * choose wisely.
   88  */
   89 #define FXP_NRFABUFS            128
   90 
   91 /*
   92  * Maximum number of seconds that the receiver can be idle before we
   93  * assume it's dead and attempt to reset it by reprogramming the
   94  * multicast filter.  This is part of a work-around for a bug in the
   95  * NIC.  See fxp_stats_update().
   96  */
   97 #define FXP_MAX_RX_IDLE 15
   98 
   99 /*
  100  * Misc. DMA'd data structures are allocated in a single clump, that
  101  * maps to a single DMA segment, to make several things easier (computing
  102  * offsets, setting up DMA maps, etc.)
  103  */
  104 struct fxp_control_data {
  105         /*
  106          * The transmit control blocks and transmit buffer descriptors.
  107          * We arrange them like this so that everything is all lined
  108          * up to use the extended TxCB feature.
  109          */
  110         struct fxp_txdesc {
  111                 struct fxp_cb_tx txd_txcb;
  112                 union {
  113                         struct fxp_ipcb txdu_ipcb;
  114                         struct fxp_tbd txdu_tbd[FXP_NTXSEG];
  115                 } txd_u;
  116         } fcd_txdescs[FXP_NTXCB];
  117 
  118         /*
  119          * The configuration CB.
  120          */
  121         struct fxp_cb_config fcd_configcb;
  122 
  123         /*
  124          * The Individual Address CB.
  125          */
  126         struct fxp_cb_ias fcd_iascb;
  127 
  128         /*
  129          * The multicast setup CB.
  130          */
  131         struct fxp_cb_mcs fcd_mcscb;
  132 
  133         /*
  134          * The microcode setup CB.
  135          */
  136         struct fxp_cb_ucode fcd_ucode;
  137 
  138         /*
  139          * The NIC statistics.
  140          */
  141         struct fxp_stats fcd_stats;
  142 };
  143 
  144 #define txd_tbd txd_u.txdu_tbd
  145 
  146 #define FXP_CDOFF(x)    offsetof(struct fxp_control_data, x)
  147 #define FXP_CDTXOFF(x)  FXP_CDOFF(fcd_txdescs[(x)].txd_txcb)
  148 #define FXP_CDTBDOFF(x) FXP_CDOFF(fcd_txdescs[(x)].txd_tbd)
  149 #define FXP_CDCONFIGOFF FXP_CDOFF(fcd_configcb)
  150 #define FXP_CDIASOFF    FXP_CDOFF(fcd_iascb)
  151 #define FXP_CDMCSOFF    FXP_CDOFF(fcd_mcscb)
  152 #define FXP_CDUCODEOFF  FXP_CDOFF(fcd_ucode)
  153 #define FXP_CDSTATSOFF  FXP_CDOFF(fcd_stats)
  154 
  155 /*
  156  * Software state for transmit descriptors.
  157  */
  158 struct fxp_txsoft {
  159         struct mbuf *txs_mbuf;          /* head of mbuf chain */
  160         bus_dmamap_t txs_dmamap;        /* our DMA map */
  161 };
  162 
  163 /*
  164  * Software state per device.
  165  */
  166 struct fxp_softc {
  167         struct device sc_dev;           /* generic device structures */
  168         bus_space_tag_t sc_st;          /* bus space tag */
  169         bus_space_handle_t sc_sh;       /* bus space handle */
  170         bus_dma_tag_t sc_dmat;          /* bus dma tag */
  171         struct ethercom sc_ethercom;    /* ethernet common part */
  172         void *sc_sdhook;                /* shutdown hook */
  173         void *sc_ih;                    /* interrupt handler cookie */
  174         void *sc_powerhook;             /* power hook */
  175 
  176         struct mii_data sc_mii;         /* MII/media information */
  177         struct callout sc_callout;      /* MII callout */
  178 
  179         /*
  180          * We create a single DMA map that maps all data structure
  181          * overhead, except for RFAs, which are mapped by the
  182          * fxp_rxdesc DMA map on a per-mbuf basis.
  183          */
  184         bus_dmamap_t sc_dmamap;
  185 #define sc_cddma        sc_dmamap->dm_segs[0].ds_addr
  186 
  187         /*
  188          * Software state for transmit descriptors.
  189          */
  190         struct fxp_txsoft sc_txsoft[FXP_NTXCB];
  191 
  192         int     sc_rfa_size;            /* size of the RFA structure */
  193         struct ifqueue sc_rxq;          /* receive buffer queue */
  194         bus_dmamap_t sc_rxmaps[FXP_NRFABUFS]; /* free receive buffer DMA maps */
  195         int     sc_rxfree;              /* free map index */
  196         int     sc_rxidle;              /* # of seconds RX has been idle */
  197         u_int16_t sc_txcmd;             /* transmit command (LITTLE ENDIAN) */
  198 
  199         /*
  200          * Control data structures.
  201          */
  202         struct fxp_control_data *sc_control_data;
  203 
  204 #ifdef FXP_EVENT_COUNTERS
  205         struct evcnt sc_ev_txstall;     /* Tx stalled */
  206         struct evcnt sc_ev_txintr;      /* Tx interrupts */
  207         struct evcnt sc_ev_rxintr;      /* Rx interrupts */
  208         struct evcnt sc_ev_txpause;     /* Tx PAUSE frames */
  209         struct evcnt sc_ev_rxpause;     /* Rx PAUSE frames */
  210 #endif /* FXP_EVENT_COUNTERS */
  211 
  212         bus_dma_segment_t sc_cdseg;     /* control dma segment */
  213         int     sc_cdnseg;
  214 
  215         int     sc_rev;                 /* chip revision */
  216         int     sc_flags;               /* misc. flags */
  217 
  218 #define FXPF_MII                0x0001  /* device uses MII */
  219 #define FXPF_ATTACHED           0x0002  /* attach has succeeded */
  220 #define FXPF_WANTINIT           0x0004  /* want a re-init */
  221 #define FXPF_HAS_RESUME_BUG     0x0008  /* has the resume bug */
  222 #define FXPF_MWI                0x0010  /* enable PCI MWI */
  223 #define FXPF_READ_ALIGN         0x0020  /* align read access w/ cacheline */
  224 #define FXPF_WRITE_ALIGN        0x0040  /* end write on cacheline */
  225 #define FXPF_EXT_TXCB           0x0080  /* enable extended TxCB */
  226 #define FXPF_UCODE_LOADED       0x0100  /* microcode is loaded */
  227 #define FXPF_EXT_RFA            0x0200  /* enable extended RFD */
  228 #define FXPF_IPCB               0x0400  /* use IPCB */
  229 #define FXPF_RECV_WORKAROUND    0x0800  /* receiver lock-up workaround */
  230 
  231         int     sc_int_delay;           /* interrupt delay */
  232         int     sc_bundle_max;          /* max packet bundle */
  233 
  234         int     sc_txpending;           /* number of TX requests pending */
  235         int     sc_txdirty;             /* first dirty TX descriptor */
  236         int     sc_txlast;              /* last used TX descriptor */
  237 
  238         int phy_primary_device;         /* device type of primary PHY */
  239 
  240         int     sc_enabled;     /* boolean; power enabled on interface */
  241         int     (*sc_enable)(struct fxp_softc *);
  242         void    (*sc_disable)(struct fxp_softc *);
  243 
  244         int     sc_eeprom_size;         /* log2 size of EEPROM */
  245 #if NRND > 0
  246         rndsource_element_t rnd_source; /* random source */
  247 #endif
  248 
  249 };
  250 
  251 #ifdef FXP_EVENT_COUNTERS
  252 #define FXP_EVCNT_INCR(ev)      (ev)->ev_count++
  253 #else
  254 #define FXP_EVCNT_INCR(ev)      /* nothing */
  255 #endif
  256 
  257 #define FXP_RXMAP_GET(sc)       ((sc)->sc_rxmaps[(sc)->sc_rxfree++])
  258 #define FXP_RXMAP_PUT(sc, map)  (sc)->sc_rxmaps[--(sc)->sc_rxfree] = (map)
  259 
  260 #define FXP_CDTXADDR(sc, x)     ((sc)->sc_cddma + FXP_CDTXOFF((x)))
  261 #define FXP_CDTBDADDR(sc, x)    ((sc)->sc_cddma + FXP_CDTBDOFF((x)))
  262 
  263 #define FXP_CDTX(sc, x)         (&(sc)->sc_control_data->fcd_txdescs[(x)])
  264 
  265 #define FXP_DSTX(sc, x)         (&(sc)->sc_txsoft[(x)])
  266 
  267 #define FXP_CDTXSYNC(sc, x, ops)                                        \
  268         bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap,                 \
  269             FXP_CDTXOFF((x)), sizeof(struct fxp_txdesc), (ops))
  270 
  271 #define FXP_CDCONFIGSYNC(sc, ops)                                       \
  272         bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap,                 \
  273             FXP_CDCONFIGOFF, sizeof(struct fxp_cb_config), (ops))
  274 
  275 #define FXP_CDIASSYNC(sc, ops)                                          \
  276         bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap,                 \
  277             FXP_CDIASOFF, sizeof(struct fxp_cb_ias), (ops))
  278 
  279 #define FXP_CDMCSSYNC(sc, ops)                                          \
  280         bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap,                 \
  281             FXP_CDMCSOFF, sizeof(struct fxp_cb_mcs), (ops))
  282 
  283 #define FXP_CDUCODESYNC(sc, ops)                                        \
  284         bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap,                 \
  285             FXP_CDUCODEOFF, sizeof(struct fxp_cb_ucode), (ops))
  286 
  287 #define FXP_CDSTATSSYNC(sc, ops)                                        \
  288         bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap,                 \
  289             FXP_CDSTATSOFF, sizeof(struct fxp_stats), (ops))
  290 
  291 #define FXP_RXBUFSIZE(sc, m)    ((m)->m_ext.ext_size -                  \
  292                                  (sc->sc_rfa_size +                     \
  293                                   RFA_ALIGNMENT_FUDGE))
  294 
  295 #define FXP_RFASYNC(sc, m, ops)                                         \
  296         bus_dmamap_sync((sc)->sc_dmat, M_GETCTX((m), bus_dmamap_t),     \
  297             RFA_ALIGNMENT_FUDGE, (sc)->sc_rfa_size, (ops))
  298 
  299 #define FXP_RXBUFSYNC(sc, m, ops)                                       \
  300         bus_dmamap_sync((sc)->sc_dmat, M_GETCTX((m), bus_dmamap_t),     \
  301             RFA_ALIGNMENT_FUDGE + (sc)->sc_rfa_size,                    \
  302             FXP_RXBUFSIZE((sc), (m)), (ops))
  303 
  304 #define FXP_MTORFA(m)   (struct fxp_rfa *)((m)->m_ext.ext_buf +         \
  305                                            RFA_ALIGNMENT_FUDGE)
  306 
  307 #define FXP_INIT_RFABUF(sc, m)                                          \
  308 do {                                                                    \
  309         bus_dmamap_t __rxmap = M_GETCTX((m), bus_dmamap_t);             \
  310         struct mbuf *__p_m;                                             \
  311         struct fxp_rfa *__rfa, *__p_rfa;                                \
  312         u_int32_t __v;                                                  \
  313                                                                         \
  314         (m)->m_data = (m)->m_ext.ext_buf + (sc)->sc_rfa_size +          \
  315             RFA_ALIGNMENT_FUDGE;                                        \
  316                                                                         \
  317         __rfa = FXP_MTORFA((m));                                        \
  318         __rfa->size = htole16(FXP_RXBUFSIZE((sc), (m)));                \
  319         /* BIG_ENDIAN: no need to swap to store 0 */                    \
  320         __rfa->rfa_status = 0;                                          \
  321         __rfa->rfa_control =                                            \
  322             htole16(FXP_RFA_CONTROL_EL | FXP_RFA_CONTROL_S);            \
  323         /* BIG_ENDIAN: no need to swap to store 0 */                    \
  324         __rfa->actual_size = 0;                                         \
  325                                                                         \
  326         /* NOTE: the RFA is misaligned, so we must copy. */             \
  327         /* BIG_ENDIAN: no need to swap to store 0xffffffff */           \
  328         __v = 0xffffffff;                                               \
  329         memcpy((void *)&__rfa->link_addr, &__v, sizeof(__v));           \
  330         memcpy((void *)&__rfa->rbd_addr, &__v, sizeof(__v));            \
  331                                                                         \
  332         FXP_RFASYNC((sc), (m),                                          \
  333             BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);                  \
  334                                                                         \
  335         FXP_RXBUFSYNC((sc), (m), BUS_DMASYNC_PREREAD);                  \
  336                                                                         \
  337         if ((__p_m = (sc)->sc_rxq.ifq_tail) != NULL) {                  \
  338                 __p_rfa = FXP_MTORFA(__p_m);                            \
  339                 __v = htole32(__rxmap->dm_segs[0].ds_addr +             \
  340                     RFA_ALIGNMENT_FUDGE);                               \
  341                 FXP_RFASYNC((sc), __p_m,                                \
  342                     BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);        \
  343                 memcpy((void *)&__p_rfa->link_addr, &__v,               \
  344                     sizeof(__v));                                       \
  345                 __p_rfa->rfa_control &= htole16(~(FXP_RFA_CONTROL_EL|   \
  346                     FXP_RFA_CONTROL_S));                                \
  347                 FXP_RFASYNC((sc), __p_m,                                \
  348                     BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);          \
  349         }                                                               \
  350         IF_ENQUEUE(&(sc)->sc_rxq, (m));                                 \
  351 } while (0)
  352 
  353 /* Macros to ease CSR access. */
  354 #define CSR_READ_1(sc, reg)                                             \
  355         bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
  356 #define CSR_READ_2(sc, reg)                                             \
  357         bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
  358 #define CSR_READ_4(sc, reg)                                             \
  359         bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
  360 #define CSR_WRITE_1(sc, reg, val)                                       \
  361         bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
  362 #define CSR_WRITE_2(sc, reg, val)                                       \
  363         bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
  364 #define CSR_WRITE_4(sc, reg, val)                                       \
  365         bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
  366 
  367 void    fxp_attach(struct fxp_softc *);
  368 int     fxp_activate(struct device *, enum devact);
  369 int     fxp_detach(struct fxp_softc *);
  370 int     fxp_intr(void *);
  371 
  372 int     fxp_enable(struct fxp_softc*);
  373 void    fxp_disable(struct fxp_softc*);

Cache object: d17106d12185617570263e968debf720


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