The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/i82595reg.h

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    1 /*      $NetBSD: i82595reg.h,v 1.7 2005/02/27 00:27:01 perry Exp $      */
    2 
    3 /*-
    4  * Copyright (c) 1996 The NetBSD Foundation, Inc.
    5  * All rights reserved.
    6  *
    7  * This code is derived from software contributed to The NetBSD Foundation
    8  * by Ignatios Souvatzis.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  * 3. All advertising materials mentioning features or use of this software
   19  *    must display the following acknowledgement:
   20  *        This product includes software developed by the NetBSD
   21  *        Foundation, Inc. and its contributors.
   22  * 4. Neither the name of The NetBSD Foundation nor the names of its
   23  *    contributors may be used to endorse or promote products derived
   24  *    from this software without specific prior written permission.
   25  *
   26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   36  * POSSIBILITY OF SUCH DAMAGE.
   37  */
   38 
   39 /*
   40  * Intel 82595 Ethernet chip register, bit, and structure definitions.
   41  *
   42  * Written by is with reference to Intel's i82595FX data sheet, with some
   43  * clarification coming from looking at the Clarkson Packet Driver code for this
   44  * chip written by Russ Nelson and others;
   45  *
   46  * and
   47  *
   48  * configuration EEPROM layout. Written with reference to Intels
   49  * public "LAN595 Hardware and Software Specifications" document.
   50  */
   51 
   52 /* registers */
   53 
   54 /* bank0 */
   55 
   56 #define COMMAND_REG 0   /* available in any bank */
   57 
   58 #define         MC_SETUP_CMD    0x03
   59 #define         XMT_CMD         0x04
   60 #define         TDR_CMD         0x05
   61 #define         DUMP_CMD        0x06
   62 #define         DIAG_CMD        0x07
   63 #define         RCV_ENABLE_CMD  0x08
   64 #define         RCV_DISABLE_CMD 0x0a
   65 #define         RCV_STOP_CMD    0x0b
   66 #define         RESET_CMD       0x0e
   67 #define         TRISTATE_CMD    0x16
   68 #define         NO_TRISTATE_CMD 0x17
   69 #define         POWER_DOWN_CMD  0x18
   70 #define         SLEEP_MODE_CMD  0x19
   71 #define         NEGOTIATE_CMD   0x1a
   72 #define         RESUME_XMT_CMD  0x1c
   73 #define         SEL_RESET_CMD   0x1e
   74 #define         BANK_SEL(n)     (n<<6)  /* 0, 1, 2 */
   75 
   76 #define STATUS_REG 1
   77 
   78 #define         RX_STP_INT      0x01
   79 #define         RX_INT          0x02
   80 #define         TX_INT          0x04
   81 #define         EXEC_INT        0x08
   82 #define         EXEC_STATUS     0x30
   83 
   84 #define ID_REG 2
   85 
   86 #define         ID_REG_MASK     0x2c
   87 #define         ID_REG_SIG      0x24
   88 #define         R_ROBIN_BITS    0xc0
   89 #define         R_ROBIN_SHIFT   6
   90 #define         AUTO_ENABLE     0x10
   91 
   92 #define INT_MASK_REG 3
   93 
   94 #define         RX_STOP_BIT     0x01
   95 #define         RX_BIT          0x02
   96 #define         TX_BIT          0x04
   97 #define         EXEC_BIT        0x08
   98 #define         ALL_INTS        0x0f
   99 
  100 #define RCV_START_LOW 4
  101 #define RCV_START_HIGH 5
  102 
  103 #define RCV_STOP_LOW 6
  104 #define RCV_STOP_HIGH 7
  105 
  106 #define RCV_COPY_THRESHOLD 8    /* byte */
  107 
  108 #define XMT_ADDR_REG 0x0a
  109 #define HOST_ADDR_REG 0x0c
  110 #define MEM_PORT_REG 0x0e
  111 
  112 /* -------------------- bank1 -------------------- */
  113 
  114 #define REG1 1
  115 
  116 #define         WORD_WIDTH      0x02
  117 #define         INT_ENABLE      0x80
  118 
  119 #define INT_NO_REG 2
  120 
  121 #define RCV_LOWER_LIMIT_REG 8
  122 #define RCV_UPPER_LIMIT_REG 9
  123 
  124 #define XMT_LOWER_LIMIT_REG 10
  125 #define XMT_UPPER_LIMIT_REG 11
  126 
  127 /* bank2 */
  128 
  129 /* reg1, apparently */
  130 
  131 #define         XMT_CHAIN_INT   0x20    /* interrupt at end of xmt chain */
  132 #define         XMT_CHAIN_ERRSTOP 0x40  /* int at end of chain even if err */
  133 #define         RCV_DISCARD_BAD 0x80    /* Throw bad frames away and continue */
  134 
  135 #define RECV_MODES_REG 2
  136 
  137 #define         PROMISC_MODE    0x01
  138 #define         NO_BRDCST       0x02
  139 #define         NO_RX_CRC       0x04
  140 #define         NO_ADD_INS      0x10
  141 #define         MULTI_IA        0x20
  142 
  143 #define         MATCH_ID        (NO_ADD_INS | NO_RX_CRC | NO_BRDCST)
  144 #define         MATCH_BRDCST    (NO_ADD_INS | NO_RX_CRC)
  145 #define         MATCH_MULTI     (NO_ADD_INS | NO_RX_CRC | MULTI_IA)
  146 #define         MATCH_ALL       (NO_ADD_INS | NO_RX_CRC | PROMISC_MODE)
  147 
  148 #define MEDIA_SELECT 3
  149 
  150 #define         TPE_BIT         0x04
  151 #define         BNC_BIT         0x20
  152 #define         TEST_MODE_MASK  0x3f
  153 
  154 #define I_ADD(n) (n+4)  /* 0..5 -> 4..9 */
  155 
  156 #define EEPROM_REG 10
  157 
  158 #define         EEDO 8
  159 #define         EEDI 4
  160 #define         EECS 2
  161 #define         EESK 1
  162 
  163 /*
  164  * EEPROM layout. Written with reference to Intels public "LAN595 Hardware and
  165  * Software Specifications" document.
  166  */
  167 
  168 #define EEPPW0          0
  169 #define         EEPP_BusWidth   0x0004
  170 #define         EEPP_FlashAdrs  0x0038
  171 #define         EEPP_FLASHTRANSFORM {-1, -1, 0xC8000, 0xCC000, 0xD0000, \
  172                                         0xD4000, 0xD8000, 0xDC000}
  173 #define         EEPP_AutoIO     0x0040
  174 #define         EEPP_IOMapping  0xfc00
  175 
  176 #define EEPPW1          1
  177 #define         EEPP_Int        0x0007
  178 #define         EEPP_INTMAP     {3, 5, 9, 10, 11, -1, -1, -1}
  179 #define         EEPP_RINTMAP    {0xff, 0xff, 0x02, 0x00, 0xff, 0x01, 0xff, \
  180                                  0xff, 0xff, 0x02, 0x03, 0x04 }
  181 
  182 #define         EEPP_LinkInteg  0x0008
  183 #define         EEPP_PolarCorr  0x0010
  184 #define         EEPP_AuiTpe     0x0020
  185 #define         EEPP_Jabber     0x0040
  186 #define         EEPP_AutoPort   0x0080
  187 #define         EEPP_SmOut      0x0100
  188 #define         EEPP_BootFls    0x0200
  189 #define         EEPP_DramSize   0x1000
  190 #define         EEPP_AltReady   0x2000
  191 
  192 #define EEPPEther2      2
  193 #define EEPPEther1      3
  194 #define EEPPEther0      4
  195 
  196 #define EEPPEther2a     0x3c
  197 #define EEPPEther1a     0x3d
  198 #define EEPPEther0a     0x3e
  199 
  200 #define EEPPW5          5
  201 #define         EEPP_BncTpe     0x0001
  202 #define         EEPP_RomSlct    0x0006  /* none, NetWare, NDIS, rsrvd. */
  203 #define         EEPP_NumConn    0x0008  /* 0=2, 1=3 */
  204 
  205 #define EEPW6           6
  206 #define EEPP_BoardRev   0x00FF
  207 
  208 #define EEPP_LENGTH 0x40
  209 #define EEPP_CHKSUM 0xBABA /* Intel claim 0x0, but this seems to be wrong */
  210 
  211 #define RCV_NO_RSC_REG  11
  212         /* How many packets were dropped due to insufficient space */
  213 
  214 /* ---- xmt /rcv /exec buffer format ---- */
  215 
  216 #define I595_XMT_HDRLEN 8
  217 
  218 #define CMD_MASK        0x001f
  219 #define TX_DONE         0x0080
  220 #define CHAIN           0x8000
  221 
  222 #define XMT_STATUS      0x02
  223 #define XMT_CHAIN       0x04
  224 #define XMT_COUNT       0x06
  225 
  226 #define I595_RCV_HDRLEN 8
  227 
  228 #define RCV_DONE        0x0008
  229 #define RX_OK           0x2000
  230 #define RX_ERR          0x0d81
  231 
  232 

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