1 /* $NetBSD: i82801lpcreg.h,v 1.2 2004/07/31 17:28:36 mrg Exp $ */
2
3 /*-
4 * Copyright (c) 2004 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Minoura Makoto.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 /*
40 * Intel 82801 Series I/O Controller Hub (ICH) -- LPC Interface Bridge part
41 * register definitions.
42 */
43 /*
44 * Currently only necessory part is defined (specifically TCO timer function).
45 */
46
47 /*
48 * PCI configuration registers
49 */
50 #define LPCIB_PCI_PMBASE 0x40
51 #define LPCIB_PCI_ACPI_CNTL 0x44
52 #define LPCIB_PCI_BIOS_CNTL 0x4e
53 #define LPCIB_PCI_TCO_CNTL 0x54
54 #define LPCIB_PCI_GPIO_BASE 0x58
55 #define LPCIB_PCI_GPIO_CNTL 0x5c
56 #define LPCIB_PCI_PIRQA_ROUT 0x60
57 #define LPCIB_PCI_PIRQB_ROUT 0x61
58 #define LPCIB_PCI_PIRQC_ROUT 0x62
59 #define LPCIB_PCI_PIRQD_ROUT 0x63
60 #define LPCIB_PCI_SIRQ_CNTL 0x64
61 #define LPCIB_PCI_PIRQE_ROUT 0x68
62 #define LPCIB_PCI_PIRQF_ROUT 0x69
63 #define LPCIB_PCI_PIRQG_ROUT 0x6a
64 #define LPCIB_PCI_PIRQH_ROUT 0x6b
65 #define LPCIB_PCI_D31_ERR_CFG 0x88
66 #define LPCIB_PCI_D31_ERR_STS 0x8a
67 #define LPCIB_PCI_PCI_DMA_C 0x90
68 #define LPCIB_PCI_GEN_PMCON_1 0xa0
69 # define LPCIB_PCI_GEN_PMCON_1_SS_EN 0x08
70 #define LPCIB_PCI_GEN_PMCON_2 0xa2
71 #define LPCIB_PCI_GEN_PMCON_3 0xa4
72 #define LPCIB_PCI_STPCLK_DEL 0xa8
73 #define LPCIB_PCI_GPI_ROUT 0xb8
74 #define LPCIB_PCI_TRP_FWD_EN 0xc0
75 #define LPCIB_PCI_MON4_TRP_RNG 0xc4
76 #define LPCIB_PCI_MON5_TRP_RNG 0xc5
77 #define LPCIB_PCI_MON6_TRP_RNG 0xc6
78 #define LPCIB_PCI_MON7_TRP_RNG 0xc7
79 #define LPCIB_PCI_MON_TRP_MSK oxcc
80 #define LPCIB_PCI_GEN_CNTL 0xd0
81 #define LPCIB_PCI_GEN_STA 0xd4
82 # define LPCIB_PCI_GEN_STA_SAFE_MODE (1<<2)
83 # define LPCIB_PCI_GEN_STA_NO_REBOOT (1<<1)
84 #define LPCIB_PCI_BACK_CNTL 0xd5
85 #define LPCIB_PCI_RTC_CONF 0xd8
86 #define LPCIB_PCI_COM_DEC 0xe0
87 #define LPCIB_PCI_LPCFDD_DEC 0xe1
88 #define LPCIB_PCI_SND_DEC 0xe2
89 #define LPCIB_PCI_FWH_DEC_EN1 0xe3
90 #define LPCIB_PCI_GEN1_DEC 0xe4
91 #define LPCIB_PCI_LPC_EN 0xe6
92 #define LPCIB_PCI_FWH_SEL1 0xe8
93 #define LPCIB_PCI_GEN2_DEC 0xec
94 #define LPCIB_PCI_FWH_SEL2 0xee
95 #define LPCIB_PCI_FWH_DEC_EN2 0xf0
96 #define LPCIB_PCI_FUNC_DIS 0xf2
97
98 /*
99 * Power management I/O registers
100 * (offset from PMBASE)
101 */
102 #define LPCIB_PM1_STS 0x00 /* ACPI PM1a_EVT_BLK fixed event status */
103 #define LPCIB_PM1_EN 0x02 /* ACPI PM1a_EVT_BLK fixed event enable */
104 #define LPCIB_PM1_CNT 0x04 /* ACPI PM1a_CNT_BLK */
105 #define LPCIB_PM1_TMR 0x08 /* ACPI PMTMR_BLK power mgmt timer */
106 #define LPCIB_PROC_CNT 0x10 /* ACPI P_BLK processor control */
107 #define LPCIB_LV2 0x14 /* ACPI P_BLK processor C2 control */
108 #define LPCIB_PM_CTRL 0x20 /* ACPI Power Management Control */
109 # define LPCIB_PM_SS_STATE_LOW 0x01 /* SpeedStep Low Power State */
110 #define LPCIB_GPE0_STS 0x28 /* ACPI GPE0_BLK GPE0 status */
111 #define LPCIB_GPE0_EN 0x2c /* ACPI GPE0_BLK GPE0 enable */
112 #define LPCIB_SMI_EN 0x30
113 # define LPCIB_SMI_EN_INTEL_USB2_EN (1 << 18)
114 # define LPCIB_SMI_EN_LEGACY_USB2_EN (1 << 17)
115 # define LPCIB_SMI_EN_PERIODIC_EN (1 << 14)
116 # define LPCIB_SMI_EN_TCO_EN (1 << 13)
117 # define LPCIB_SMI_EN_MCSMI_EN (1 << 11)
118 # define LPCIB_SMI_EN_BIOS_RLS (1 << 7)
119 # define LPCIB_SMI_EN_SWSMI_TMR_EN (1 << 6)
120 # define LPCIB_SMI_EN_APMC_EN (1 << 5)
121 # define LPCIB_SMI_EN_SLP_SMI_EN (1 << 4)
122 # define LPCIB_SMI_EN_LEGACY_USB_EN (1 << 3)
123 # define LPCIB_SMI_EN_BIOS_EN (1 << 2)
124 # define LPCIB_SMI_EN_EOS (1 << 1)
125 # define LPCIB_SMI_EN_GBL_SMI_EN (1 << 0)
126 #define LPCIB_SMI_STS 0x34
127 #define LPCIB_ALT_GP_SMI_EN 0x38
128 #define LPCIB_ALT_GP_SMI_STS 0x3a
129 #define LPCIB_MON_SMI 0x40
130 #define LPCIB_DEVACT_STS 0x44
131 #define LPCIB_DEVTRAP_EN 0x48
132 #define LPCIB_BUS_ADDR_TRACK 0x4c
133 #define LPCIB_BUS_CYC_TRACK 0x4e
134 #define LPCIB_PM_SS_CNTL 0x50 /* SpeedStep control */
135 # define LPCIB_PM_SS_CNTL_ARB_DIS 0x01 /* disable arbiter */
136
137 /*
138 * System management TCO registers
139 * (offset from PMBASE)
140 */
141 #define LPCIB_TCO_BASE 0x60
142 #define LPCIB_TCO_RLD (LPCIB_TCO_BASE+0x00)
143 #define LPCIB_TCO_TMR (LPCIB_TCO_BASE+0x01)
144 # define LPCIB_TCO_TMR_MASK 0x3f
145 #define LPCIB_TCO_DAT_IN (LPCIB_TCO_BASE+0x02)
146 #define LPCIB_TCO_DAT_OUT (LPCIB_TCO_BASE+0x03)
147 #define LPCIB_TCO1_STS (LPCIB_TCO_BASE+0x04)
148 #define LPCIB_TCO2_STS (LPCIB_TCO_BASE+0x06)
149 #define LPCIB_TCO1_CNT (LPCIB_TCO_BASE+0x08)
150 # define LPCIB_TCO1_CNT_TCO_TMR_HLT (1 << 11)
151 # define LPCIB_TCO1_CNT_SEND_NOW (1 << 10)
152 # define LPCIB_TCO1_CNT_NMI2SMI_EN (1 << 9)
153 # define LPCIB_TCO1_CNT_NMI_NOW (1 << 8)
154 #define LPCIB_TCO2_CNT (LPCIB_TCO_BASE+0x0a)
155 #define LPCIB_TCO_MESSAGE1 (LPCIB_TCO_BASE+0x0c)
156 #define LPCIB_TCO_MESSAGE2 (LPCIB_TCO_BASE+0x0d)
157 #define LPCIB_TCO_WDSTATUS (LPCIB_TCO_BASE+0x0e)
158 #define LPCIB_SW_IRQ_GEN (LPCIB_TCO_BASE+0x10)
159
160 /*
161 * TCO timer tick. ICH datasheets say:
162 * - The timer is clocked at approximately 0.6 seconds
163 * - 6 bit; values of 0-3 will be ignored and should not be attempted
164 */
165 static inline int
166 lpcib_tcotimer_tick_to_second(int tick)
167 {
168 return tick * 6 / 10;
169 }
170
171 static inline int
172 lpcib_tcotimer_second_to_tick(int tick)
173 {
174 return tick * 10 / 6;
175 }
176 #define LPCIB_TCOTIMER_MIN_TICK 4
177 #define LPCIB_TCOTIMER_MAX_TICK 0x3f
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