1 /* $NetBSD: i82801lpcreg.h,v 1.8 2008/04/28 20:23:50 martin Exp $ */
2
3 /*-
4 * Copyright (c) 2004 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Minoura Makoto.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * Intel 82801 Series I/O Controller Hub (ICH) -- LPC Interface Bridge part
34 * register definitions.
35 */
36
37 #ifndef _DEV_IC_I82801LPGREG_H_
38 #define _DEV_IC_I82801LPGREG_H_
39 /*
40 * PCI configuration registers
41 */
42 #define LPCIB_PCI_PMBASE 0x40
43 #define LPCIB_PCI_ACPI_CNTL 0x44
44 # define LPCIB_PCI_ACPI_CNTL_EN (1 << 4)
45 #define LPCIB_PCI_BIOS_CNTL 0x4e
46 #define LPCIB_PCI_TCO_CNTL 0x54
47 #define LPCIB_PCI_GPIO_BASE 0x58
48 #define LPCIB_PCI_GPIO_CNTL 0x5c
49 #define LPCIB_PCI_PIRQA_ROUT 0x60
50 #define LPCIB_PCI_PIRQB_ROUT 0x61
51 #define LPCIB_PCI_PIRQC_ROUT 0x62
52 #define LPCIB_PCI_PIRQD_ROUT 0x63
53 #define LPCIB_PCI_SIRQ_CNTL 0x64
54 #define LPCIB_PCI_PIRQE_ROUT 0x68
55 #define LPCIB_PCI_PIRQF_ROUT 0x69
56 #define LPCIB_PCI_PIRQG_ROUT 0x6a
57 #define LPCIB_PCI_PIRQH_ROUT 0x6b
58 #define LPCIB_PCI_D31_ERR_CFG 0x88
59 #define LPCIB_PCI_D31_ERR_STS 0x8a
60 #define LPCIB_PCI_PCI_DMA_C 0x90
61 #define LPCIB_PCI_GEN_PMCON_1 0xa0
62 # define LPCIB_PCI_GEN_PMCON_1_SS_EN 0x08
63 #define LPCIB_PCI_GEN_PMCON_2 0xa2
64 #define LPCIB_PCI_GEN_PMCON_3 0xa4
65 #define LPCIB_PCI_STPCLK_DEL 0xa8
66 #define LPCIB_PCI_GPI_ROUT 0xb8
67 #define LPCIB_PCI_TRP_FWD_EN 0xc0
68 #define LPCIB_PCI_MON4_TRP_RNG 0xc4
69 #define LPCIB_PCI_MON5_TRP_RNG 0xc5
70 #define LPCIB_PCI_MON6_TRP_RNG 0xc6
71 #define LPCIB_PCI_MON7_TRP_RNG 0xc7
72 #define LPCIB_PCI_MON_TRP_MSK oxcc
73 #define LPCIB_PCI_GEN_CNTL 0xd0
74 #define LPCIB_ICH5_HPTC_EN 0x00020000
75 #define LPCIB_ICH5_HPTC_WIN_MASK 0x0000c000
76 #define LPCIB_ICH5_HPTC_0000 0x00000000
77 #define LPCIB_ICH5_HPTC_0000_BASE 0xfed00000
78 #define LPCIB_ICH5_HPTC_1000 0x00008000
79 #define LPCIB_ICH5_HPTC_1000_BASE 0xfed01000
80 #define LPCIB_ICH5_HPTC_2000 0x00010000
81 #define LPCIB_ICH5_HPTC_2000_BASE 0xfed02000
82 #define LPCIB_ICH5_HPTC_3000 0x00018000
83 #define LPCIB_ICH5_HPTC_3000_BASE 0xfed03000
84 #define LPCIB_PCI_GEN_STA 0xd4
85 # define LPCIB_PCI_GEN_STA_SAFE_MODE (1 << 2)
86 # define LPCIB_PCI_GEN_STA_NO_REBOOT (1 << 1)
87 #define LPCIB_PCI_BACK_CNTL 0xd5
88 #define LPCIB_PCI_RTC_CONF 0xd8
89 #define LPCIB_PCI_COM_DEC 0xe0
90 #define LPCIB_PCI_LPCFDD_DEC 0xe1
91 #define LPCIB_PCI_SND_DEC 0xe2
92 #define LPCIB_PCI_FWH_DEC_EN1 0xe3
93 #define LPCIB_PCI_GEN1_DEC 0xe4
94 #define LPCIB_PCI_LPC_EN 0xe6
95 #define LPCIB_PCI_FWH_SEL1 0xe8
96 #define LPCIB_PCI_GEN2_DEC 0xec
97 #define LPCIB_PCI_FWH_SEL2 0xee
98 #define LPCIB_PCI_FWH_DEC_EN2 0xf0
99 #define LPCIB_PCI_FUNC_DIS 0xf2
100
101 /*
102 * Power management I/O registers
103 * (offset from PMBASE)
104 */
105 #define LPCIB_PM1_STS 0x00 /* ACPI PM1a_EVT_BLK fixed event status */
106 #define LPCIB_PM1_EN 0x02 /* ACPI PM1a_EVT_BLK fixed event enable */
107 #define LPCIB_PM1_CNT 0x04 /* ACPI PM1a_CNT_BLK */
108 #define LPCIB_PM1_TMR 0x08 /* ACPI PMTMR_BLK power mgmt timer */
109 #define LPCIB_PROC_CNT 0x10 /* ACPI P_BLK processor control */
110 #define LPCIB_LV2 0x14 /* ACPI P_BLK processor C2 control */
111 #define LPCIB_PM_CTRL 0x20 /* ACPI Power Management Control */
112 # define LPCIB_PM_SS_STATE_LOW 0x01 /* SpeedStep Low Power State */
113 #define LPCIB_GPE0_STS 0x28 /* ACPI GPE0_BLK GPE0 status */
114 #define LPCIB_GPE0_EN 0x2c /* ACPI GPE0_BLK GPE0 enable */
115 #define LPCIB_SMI_EN 0x30
116 # define LPCIB_SMI_EN_INTEL_USB2_EN (1 << 18)
117 # define LPCIB_SMI_EN_LEGACY_USB2_EN (1 << 17)
118 # define LPCIB_SMI_EN_PERIODIC_EN (1 << 14)
119 # define LPCIB_SMI_EN_TCO_EN (1 << 13)
120 # define LPCIB_SMI_EN_MCSMI_EN (1 << 11)
121 # define LPCIB_SMI_EN_BIOS_RLS (1 << 7)
122 # define LPCIB_SMI_EN_SWSMI_TMR_EN (1 << 6)
123 # define LPCIB_SMI_EN_APMC_EN (1 << 5)
124 # define LPCIB_SMI_EN_SLP_SMI_EN (1 << 4)
125 # define LPCIB_SMI_EN_LEGACY_USB_EN (1 << 3)
126 # define LPCIB_SMI_EN_BIOS_EN (1 << 2)
127 # define LPCIB_SMI_EN_EOS (1 << 1)
128 # define LPCIB_SMI_EN_GBL_SMI_EN (1 << 0)
129 #define LPCIB_SMI_STS 0x34
130 #define LPCIB_ALT_GP_SMI_EN 0x38
131 #define LPCIB_ALT_GP_SMI_STS 0x3a
132 #define LPCIB_MON_SMI 0x40
133 #define LPCIB_DEVACT_STS 0x44
134 #define LPCIB_DEVTRAP_EN 0x48
135 #define LPCIB_BUS_ADDR_TRACK 0x4c
136 #define LPCIB_BUS_CYC_TRACK 0x4e
137 #define LPCIB_PM_SS_CNTL 0x50 /* SpeedStep control */
138 # define LPCIB_PM_SS_CNTL_ARB_DIS 0x01 /* disable arbiter */
139
140 /*
141 * SMBus controller registers.
142 */
143
144 /* PCI configuration registers */
145 #define LPCIB_SMB_BASE 0x20 /* SMBus base address */
146 #define LPCIB_SMB_HOSTC 0x40 /* host configuration */
147 #define LPCIB_SMB_HOSTC_HSTEN (1 << 0) /* enable host controller */
148 #define LPCIB_SMB_HOSTC_SMIEN (1 << 1) /* generate SMI */
149 #define LPCIB_SMB_HOSTC_I2CEN (1 << 2) /* enable I2C commands */
150
151 /* SMBus I/O registers */
152 #define LPCIB_SMB_HS 0x00 /* host status */
153 #define LPCIB_SMB_HS_BUSY (1 << 0) /* running a command */
154 #define LPCIB_SMB_HS_INTR (1 << 1) /* command completed */
155 #define LPCIB_SMB_HS_DEVERR (1 << 2) /* command error */
156 #define LPCIB_SMB_HS_BUSERR (1 << 3) /* transaction collision */
157 #define LPCIB_SMB_HS_FAILED (1 << 4) /* failed bus transaction */
158 #define LPCIB_SMB_HS_SMBAL (1 << 5) /* SMBALERT# asserted */
159 #define LPCIB_SMB_HS_INUSE (1 << 6) /* bus semaphore */
160 #define LPCIB_SMB_HS_BDONE (1 << 7) /* byte received/transmitted */
161 #define LPCIB_SMB_HS_BITS "\020\001BUSY\002INTR\003DEVERR\004BUSERR\005FAILED\006SMBAL\007INUSE\010BDONE"
162 #define LPCIB_SMB_HC 0x02 /* host control */
163 #define LPCIB_SMB_HC_INTREN (1 << 0) /* enable interrupts */
164 #define LPCIB_SMB_HC_KILL (1 << 1) /* kill current transaction */
165 #define LPCIB_SMB_HC_CMD_QUICK (0 << 2) /* QUICK command */
166 #define LPCIB_SMB_HC_CMD_BYTE (1 << 2) /* BYTE command */
167 #define LPCIB_SMB_HC_CMD_BDATA (2 << 2) /* BYTE DATA command */
168 #define LPCIB_SMB_HC_CMD_WDATA (3 << 2) /* WORD DATA command */
169 #define LPCIB_SMB_HC_CMD_PCALL (4 << 2) /* PROCESS CALL command */
170 #define LPCIB_SMB_HC_CMD_BLOCK (5 << 2) /* BLOCK command */
171 #define LPCIB_SMB_HC_CMD_I2CREAD (6 << 2) /* I2C READ command */
172 #define LPCIB_SMB_HC_CMD_BLOCKP (7 << 2) /* BLOCK PROCESS command */
173 #define LPCIB_SMB_HC_LASTB (1 << 5) /* last byte in block */
174 #define LPCIB_SMB_HC_START (1 << 6) /* start transaction */
175 #define LPCIB_SMB_HC_PECEN (1 << 7) /* enable PEC */
176 #define LPCIB_SMB_HCMD 0x03 /* host command */
177 #define LPCIB_SMB_TXSLVA 0x04 /* transmit slave address */
178 #define LPCIB_SMB_TXSLVA_READ (1 << 0) /* read direction */
179 #define LPCIB_SMB_TXSLVA_ADDR(x) (((x) & 0x7f) << 1) /* 7-bit address */
180 #define LPCIB_SMB_HD0 0x05 /* host data 0 */
181 #define LPCIB_SMB_HD1 0x06 /* host data 1 */
182 #define LPCIB_SMB_HBDB 0x07 /* host block data byte */
183 #define LPCIB_SMB_PEC 0x08 /* PEC data */
184 #define LPCIB_SMB_RXSLVA 0x09 /* receive slave address */
185 #define LPCIB_SMB_SD 0x0a /* receive slave data */
186 #define LPCIB_SMB_SD_MSG0(x) ((x) & 0xff) /* data message byte 0 */
187 #define LPCIB_SMB_SD_MSG1(x) ((x) >> 8) /* data message byte 1 */
188 #define LPCIB_SMB_AS 0x0c /* auxiliary status */
189 #define LPCIB_SMB_AS_CRCE (1 << 0) /* CRC error */
190 #define LPCIB_SMB_AS_TCO (1 << 1) /* advanced TCO mode */
191 #define LPCIB_SMB_AC 0x0d /* auxiliary control */
192 #define LPCIB_SMB_AC_AAC (1 << 0) /* automatically append CRC */
193 #define LPCIB_SMB_AC_E32B (1 << 1) /* enable 32-byte buffer */
194 #define LPCIB_SMB_SMLPC 0x0e /* SMLink pin control */
195 #define LPCIB_SMB_SMLPC_LINK0 (1 << 0) /* SMLINK0 pin state */
196 #define LPCIB_SMB_SMLPC_LINK1 (1 << 1) /* SMLINK1 pin state */
197 #define LPCIB_SMB_SMLPC_CLKC (1 << 2) /* SMLINK0 pin is untouched */
198 #define LPCIB_SMB_SMBPC 0x0f /* SMBus pin control */
199 #define LPCIB_SMB_SMBPC_CLK (1 << 0) /* SMBCLK pin state */
200 #define LPCIB_SMB_SMBPC_DATA (1 << 1) /* SMBDATA pin state */
201 #define LPCIB_SMB_SMBPC_CLKC (1 << 2) /* SMBCLK pin is untouched */
202 #define LPCIB_SMB_SS 0x10 /* slave status */
203 #define LPCIB_SMB_SS_HN (1 << 0) /* Host Notify command */
204 #define LPCIB_SMB_SCMD 0x11 /* slave command */
205 #define LPCIB_SMB_SCMD_INTREN (1 << 0) /* enable interrupts on HN */
206 #define LPCIB_SMB_SCMD_WKEN (1 << 1) /* wake on HN */
207 #define LPCIB_SMB_SCMD_SMBALDS (1 << 2) /* disable SMBALERT# intr */
208 #define LPCIB_SMB_NDADDR 0x14 /* notify device address */
209 #define LPCIB_SMB_NDADDR_ADDR(x) ((x) >> 1) /* 7-bit address */
210 #define LPCIB_SMB_NDLOW 0x16 /* notify data low byte */
211 #define LPCIB_SMB_NDHIGH 0x17 /* notify data high byte */
212
213 /* ICH Chipset Configuration Registers (ICH6 and newer) */
214 #define LPCIB_RCBA 0xf0
215 #define LPCIB_RCBA_EN 0x00000001
216 #define LPCIB_RCBA_SIZE 0x00004000
217 #define LPCIB_GCS_OFFSET 0x3410
218 #define LPCIB_GCS_NO_REBOOT 0x20
219 #define LPCIB_RCBA_HPTC 0x00003404
220 #define LPCIB_RCBA_HPTC_EN 0x00000080
221 #define LPCIB_RCBA_HPTC_WIN_MASK 0x00000003
222 #define LPCIB_RCBA_HPTC_0000 0x00000000
223 #define LPCIB_RCBA_HPTC_0000_BASE 0xfed00000
224 #define LPCIB_RCBA_HPTC_1000 0x00000001
225 #define LPCIB_RCBA_HPTC_1000_BASE 0xfed01000
226 #define LPCIB_RCBA_HPTC_2000 0x00000002
227 #define LPCIB_RCBA_HPTC_2000_BASE 0xfed02000
228 #define LPCIB_RCBA_HPTC_3000 0x00000003
229 #define LPCIB_RCBA_HPTC_3000_BASE 0xfed03000
230
231 /*
232 * System management TCO registers
233 * (offset from PMBASE)
234 */
235 #define LPCIB_TCO_BASE 0x60
236 #define LPCIB_TCO_RLD (LPCIB_TCO_BASE+0x00)
237 #define LPCIB_TCO_TMR (LPCIB_TCO_BASE+0x01)
238 #define LPCIB_TCO_TMR2 (LPCIB_TCO_BASE+0x12) /* ICH6 and newer */
239 # define LPCIB_TCO_TMR_MASK 0x3f
240 #define LPCIB_TCO_DAT_IN (LPCIB_TCO_BASE+0x02)
241 #define LPCIB_TCO_DAT_OUT (LPCIB_TCO_BASE+0x03)
242 #define LPCIB_TCO1_STS (LPCIB_TCO_BASE+0x04)
243 # define LPCIB_TCO1_STS_TIMEOUT 0x08
244 #define LPCIB_TCO2_STS (LPCIB_TCO_BASE+0x06)
245 # define LPCIB_TCO2_STS_BOOT_STS 0x04
246 # define LPCIB_TCO2_STS_SECONDS_TO_STS 0x02
247 #define LPCIB_TCO1_CNT (LPCIB_TCO_BASE+0x08)
248 # define LPCIB_TCO1_CNT_TCO_LOCK (1 << 12)
249 # define LPCIB_TCO1_CNT_TCO_TMR_HLT (1 << 11)
250 # define LPCIB_TCO1_CNT_SEND_NOW (1 << 10)
251 # define LPCIB_TCO1_CNT_NMI2SMI_EN (1 << 9)
252 # define LPCIB_TCO1_CNT_NMI_NOW (1 << 8)
253 #define LPCIB_TCO2_CNT (LPCIB_TCO_BASE+0x0a)
254 #define LPCIB_TCO_MESSAGE1 (LPCIB_TCO_BASE+0x0c)
255 #define LPCIB_TCO_MESSAGE2 (LPCIB_TCO_BASE+0x0d)
256 #define LPCIB_TCO_WDSTATUS (LPCIB_TCO_BASE+0x0e)
257 #define LPCIB_SW_IRQ_GEN (LPCIB_TCO_BASE+0x10)
258
259 /*
260 * TCO timer tick. ICH datasheets say:
261 * - The timer is clocked at approximately 0.6 seconds
262 * - 6 bit; values of 0-3 will be ignored and should not be attempted
263 */
264 static __inline int
265 lpcib_tcotimer_tick_to_second(int ltick)
266 {
267 return ltick * 6 / 10;
268 }
269
270 static __inline int
271 lpcib_tcotimer_second_to_tick(int ltick)
272 {
273 return ltick * 10 / 6;
274 }
275
276 #define LPCIB_TCOTIMER_MIN_TICK 4
277 #define LPCIB_TCOTIMER2_MIN_TICK 2
278 #define LPCIB_TCOTIMER_MAX_TICK 0x3f /* 39 seconds max */
279 #define LPCIB_TCOTIMER2_MAX_TICK 0x265 /* 613 seconds max */
280
281 #endif /* _DEV_IC_I82801LPGREG_H_ */
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