Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/ic/iha.h
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1 /* $OpenBSD: iha.h,v 1.24 2020/07/22 13:16:04 krw Exp $ */ 2 /*------------------------------------------------------------------------- 3 * 4 * Device driver for the INI-9XXXU/UW or INIC-940/950 PCI SCSI Controller. 5 * 6 * Written for 386bsd and FreeBSD by 7 * Winston Hung <winstonh@initio.com> 8 * 9 * Copyright (c) 1997-1999 Initio Corp 10 * Copyright (c) 2000-2002 Ken Westerback 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer, 17 * without modification, immediately at the beginning of the file. 18 * 2. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 30 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 *------------------------------------------------------------------------- 34 */ 35 36 #define IHA_MAX_SG_ENTRIES 33 37 #define IHA_MAX_TARGETS 16 38 #define IHA_MAX_SCB 32 39 #define IHA_MAX_EXTENDED_MSG 4 /* SDTR(3) and WDTR(4) only */ 40 41 /* 42 * Scatter-Gather Element Structure 43 */ 44 struct iha_sg_element { 45 u_int32_t SG_Addr; /* Physical address of segment */ 46 u_int32_t SG_Len; /* Length of segment */ 47 }; 48 49 /* 50 * iha_scb - SCSI Request structure used by the 51 * Tulip (aka inic-940/950). Note that 32 52 * bit pointers and ints are assumed! 53 */ 54 55 struct iha_scb { 56 TAILQ_ENTRY(iha_scb) SCB_ScbList; 57 58 bus_dmamap_t SCB_DataDma; /* maps xfer buffer */ 59 bus_dmamap_t SCB_SGDma; /* maps scatter-gather list */ 60 61 int SCB_Status; /* Current status of the SCB */ 62 #define STATUS_QUEUED 0 /* SCB one of Free/Done/Pend */ 63 #define STATUS_RENT 1 /* SCB allocated, not queued */ 64 #define STATUS_SELECT 2 /* SCB being selected */ 65 #define STATUS_BUSY 3 /* SCB I/O is active */ 66 u_int8_t SCB_NxtStat; /* Next state function to apply */ 67 int SCB_Flags; /* SCB Flags (xs->flags + private)*/ 68 #define FLAG_RSENS 0x00010000 /* Request Sense sent */ 69 #define FLAG_SG 0x00020000 /* Scatter/Gather used */ 70 #define FLAG_DIR (SCSI_DATA_IN | SCSI_DATA_OUT) 71 u_int8_t SCB_Target; /* Target Id */ 72 u_int8_t SCB_Lun; /* Lun */ 73 u_int32_t SCB_BufChars; /* size of data buf */ 74 u_int32_t SCB_BufCharsLeft; /* Chars left to xfer to/from buf */ 75 u_int8_t SCB_HaStat; /* Status of Host Adapter */ 76 #define HOST_OK 0x00 /* OK - operation a success */ 77 #define HOST_TIMED_OUT 0x01 /* Request timed out */ 78 #define HOST_SPERR 0x10 /* SCSI parity error */ 79 #define HOST_SEL_TOUT 0x11 /* Selection Timeout */ 80 #define HOST_DO_DU 0x12 /* Data Over/Underrun */ 81 #define HOST_BAD_PHAS 0x14 /* Unexpected SCSI bus phase */ 82 #define HOST_SCSI_RST 0x1B /* SCSI bus was reset */ 83 #define HOST_DEV_RST 0x1C /* Device was reset */ 84 u_int8_t SCB_TaStat; /* SCSI Status Byte */ 85 u_int8_t SCB_Ident; /* Identity Message */ 86 u_int8_t SCB_TagMsg; /* Tag Message */ 87 u_int8_t SCB_TagId; /* Queue Tag */ 88 89 u_int8_t SCB_CDB[12]; /* SCSI command being executed */ 90 u_int8_t SCB_CDBLen; /* Length of SCSI command in CDB */ 91 92 struct scsi_xfer *SCB_Xs; /* xs this SCB is executing */ 93 94 struct iha_sg_element SCB_SGList[IHA_MAX_SG_ENTRIES]; /* SG list */ 95 u_int16_t SCB_SGCount; /* # segments in list */ 96 u_int16_t SCB_SGIdx; /* index to current element */ 97 98 struct scsi_sense_data SCB_ScsiSenseData; /* DMA-able sense buffer */ 99 struct tcs *SCB_Tcs; /* tcs for SCB_Target */ 100 }; 101 102 /* 103 * Target Device Control Structure 104 */ 105 struct tcs { 106 u_int16_t TCS_Flags; 107 #define FLAG_SCSI_RATE 0x0007 /* Index into tul_rate_tbl[] */ 108 #define FLAG_EN_DISC 0x0008 /* Enable disconnect */ 109 #define FLAG_NO_SYNC 0x0010 /* No sync data transfer */ 110 #define FLAG_NO_WIDE 0x0020 /* No wide data transfer */ 111 #define FLAG_1GIGA 0x0040 /* 255 hd/63 sec (64/32) */ 112 #define FLAG_SPINUP 0x0080 /* Start disk drive */ 113 #define FLAG_WIDE_DONE 0x0100 /* WDTR msg has been sent */ 114 #define FLAG_SYNC_DONE 0x0200 /* SDTR msg has been sent */ 115 #define FLAG_NO_NEG_SYNC (FLAG_NO_SYNC | FLAG_SYNC_DONE) 116 #define FLAG_NO_NEG_WIDE (FLAG_NO_WIDE | FLAG_WIDE_DONE) 117 u_int8_t TCS_JS_Period; 118 #define PERIOD_WIDE_SCSI 0x80 /* Enable Wide SCSI */ 119 #define PERIOD_SYXPD 0x70 /* Synch. SCSI Xfer rate */ 120 #define PERIOD_SYOFS 0x0f /* Synch. SCSI Offset */ 121 u_int8_t TCS_SConfig0; 122 u_int8_t TCS_TagCnt; 123 124 struct iha_scb *TCS_NonTagScb; 125 }; 126 127 struct iha_softc { 128 struct device sc_dev; 129 130 bus_space_tag_t sc_iot; 131 bus_space_handle_t sc_ioh; 132 133 bus_dma_tag_t sc_dmat; 134 bus_dmamap_t sc_dmamap; 135 136 u_int16_t sc_id; 137 u_int16_t sc_maxtargets; 138 139 void *sc_ih; 140 141 /* 142 * Initio specific fields 143 */ 144 u_int8_t HCS_Flags; 145 #define FLAG_EXPECT_DISC 0x01 146 #define FLAG_EXPECT_SELECT 0x02 147 #define FLAG_EXPECT_RESET 0x10 148 #define FLAG_EXPECT_DONE_DISC 0x20 149 u_int8_t HCS_Semaph; 150 #define SEMAPH_IN_MAIN 0x00 /* Already in tulip_main */ 151 u_int8_t HCS_Phase; /* MSG C/D I/O */ 152 #define PHASE_DATA_OUT 0x00 /* 0 0 0 */ 153 #define PHASE_DATA_IN 0x01 /* 0 0 1 */ 154 #define PHASE_CMD_OUT 0x02 /* 0 1 0 */ 155 #define PHASE_STATUS_IN 0x03 /* 0 1 1 */ 156 #define PHASE_MSG_OUT 0x06 /* 1 1 0 */ 157 #define PHASE_MSG_IN 0x07 /* 1 1 1 */ 158 u_int8_t HCS_JSInt; 159 u_int8_t HCS_JSStatus0; 160 u_int8_t HCS_JSStatus1; 161 u_int8_t HCS_SConf1; 162 u_int8_t HCS_Msg[IHA_MAX_EXTENDED_MSG]; /* [0] len, [1] Msg Code */ 163 164 struct iha_scb *HCS_Scb; /* SCB array */ 165 struct iha_scb *HCS_ActScb; /* SCB using SCSI bus */ 166 167 TAILQ_HEAD(, iha_scb) HCS_FreeScb, HCS_PendScb, HCS_DoneScb; 168 169 struct tcs HCS_Tcs[IHA_MAX_TARGETS]; 170 171 struct mutex sc_scb_mtx; /* scb queue protection */ 172 struct scsi_iopool sc_iopool; 173 }; 174 175 /* 176 * EEPROM for one SCSI Channel 177 * 178 */ 179 struct iha_nvram_scsi { 180 u_int8_t NVM_SCSI_Id; /* 0x00 Channel Adapter SCSI Id */ 181 u_int8_t NVM_SCSI_Cfg; /* 0x01 Channel configuration */ 182 #define CFG_SCSI_RESET 0x0001 /* Reset bus at power up */ 183 #define CFG_EN_PAR 0x0002 /* SCSI parity enable */ 184 #define CFG_ACT_TERM1 0x0004 /* Enable active term 1 */ 185 #define CFG_ACT_TERM2 0x0008 /* Enable active term 2 */ 186 #define CFG_AUTO_TERM 0x0010 /* Enable auto terminator */ 187 #define CFG_EN_PWR 0x0080 /* Enable power mgmt */ 188 u_int8_t NVM_SCSI_CfgByte2; /* 0x02 Unused Channel Cfg byte 2*/ 189 u_int8_t NVM_SCSI_Targets; /* 0x03 Number of SCSI targets */ 190 /* 0x04 Lower bytes of targ flags*/ 191 u_int8_t NVM_SCSI_TargetFlags[IHA_MAX_TARGETS]; 192 }; 193 194 /* 195 * Tulip (aka ini-940/950) Serial EEPROM Layout 196 * 197 */ 198 struct iha_nvram { 199 /* ---------- Header ------------------------------------------------*/ 200 u_int16_t NVM_Signature; /* 0x00 NVRAM Signature */ 201 #define SIGNATURE 0xC925 202 u_int8_t NVM_Size; /* 0x02 Size of data structure*/ 203 u_int8_t NVM_Revision; /* 0x03 Rev. of data structure*/ 204 205 /* ---------- Host Adapter Structure --------------------------------*/ 206 u_int8_t NVM_ModelByte0; /* 0x04 Model number (byte 0) */ 207 u_int8_t NVM_ModelByte1; /* 0x05 Model number (byte 1) */ 208 u_int8_t NVM_ModelInfo; /* 0x06 Model information */ 209 u_int8_t NVM_NumOfCh; /* 0x07 Number of SCSI channel*/ 210 u_int8_t NVM_BIOSConfig1; /* 0x08 BIOS configuration 1 */ 211 #define BIOSCFG_ENABLE 0x01 /* BIOS enable */ 212 #define BIOSCFG_8DRIVE 0x02 /* Support > 2 drives */ 213 #define BIOSCFG_REMOVABLE 0x04 /* Support removable drv */ 214 #define BIOSCFG_INT19 0x08 /* Intercept int 19h */ 215 #define BIOSCFG_BIOSSCAN 0x10 /* Dynamic BIOS scan */ 216 #define BIOSCFG_LUNSUPPORT 0x40 /* Support LUN */ 217 #define BIOSCFG_DEFAULT (BIOSCFG_ENABLE) 218 u_int8_t NVM_BIOSConfig2; /* 0x09 BIOS configuration 2 */ 219 u_int8_t NVM_HAConfig1; /* 0x0a Host adapter config 1 */ 220 #define HACFG_BOOTIDMASK 0x0F /* Boot ID number */ 221 #define HACFG_LUNMASK 0x70 /* Boot LUN number */ 222 #define HACFG_CHANMASK 0x80 /* Boot Channel number */ 223 u_int8_t NVM_HAConfig2; /* 0x0b Host adapter config 2 */ 224 struct iha_nvram_scsi NVM_Scsi[2]; /* 0x0c */ 225 u_int8_t NVM_Reserved[10]; /* 0x34 */ 226 227 /* --------- CheckSum -----------------------------------------------*/ 228 u_int16_t NVM_CheckSum; /* 0x3E Checksum of NVRam */ 229 }; 230 231 /* 232 * Tulip (aka inic-940/950) PCI Configuration Space Initio Specific Registers 233 * 234 * Offsets 0x00 through 0x3f are the standard PCI Configuration Header 235 * registers. 236 * 237 * Offsets 0x40 through 0x4f, 0x51, 0x53, 0x57, 0x5b, 0x5e and 0x5f are 238 * reserved registers. 239 * 240 * Registers 0x50 and 0x52 always read as 0. 241 * 242 * The register offset names and associated bit field names are taken 243 * from the Inic-950 Data Sheet, Version 2.1, March 1997 244 */ 245 #define TUL_GCTRL0 0x54 /* R/W Global Control 0 */ 246 #define EEPRG 0x04 /* Enable EEPROM Programming */ 247 #define TUL_GCTRL1 0x55 /* R/W Global Control 1 */ 248 #define ATDEN 0x01 /* Auto Termination Detect Enable */ 249 #define TUL_GSTAT 0x56 /* R/W Global Status - connector type */ 250 #define TUL_EPAD0 0x58 /* R/W External EEPROM Addr (lo byte) */ 251 #define TUL_EPAD1 0x59 /* R/W External EEPROM Addr (hi byte) */ 252 #define TUL_PNVPG 0x5A /* R/W Data port to external BIOS */ 253 #define TUL_EPDATA 0x5C /* R/W EEPROM Data port */ 254 #define TUL_NVRAM 0x5D /* R/W Non-volatile RAM port */ 255 #define NVREAD 0x80 /* Read from given NVRAM addr */ 256 #define NVWRITE 0x40 /* Write to given NVRAM addr */ 257 #define NVENABLE_ERASE 0x30 /* Enable NVRAM Erase/Write */ 258 #define NVRCS 0x08 /* Select external NVRAM */ 259 #define NVRCK 0x04 /* NVRAM Clock */ 260 #define NVRDO 0x02 /* NVRAM Write Data */ 261 #define NVRDI 0x01 /* NVRAM Read Data */ 262 263 /* 264 * Tulip (aka inic-940/950) SCSI Registers 265 */ 266 #define TUL_STCNT0 0x80 /* R/W 24 bit SCSI Xfer Count */ 267 #define TCNT 0x00ffffff /* SCSI Xfer Transfer Count */ 268 #define TUL_SFIFOCNT 0x83 /* R/W 5 bit FIFO counter */ 269 #define FIFOC 0x1f /* SCSI Offset Fifo Count */ 270 #define TUL_SISTAT 0x84 /* R Interrupt Register */ 271 #define RSELED 0x80 /* Reselected */ 272 #define STIMEO 0x40 /* Selected/Reselected Timeout */ 273 #define SBSRV 0x20 /* SCSI Bus Service */ 274 #define SRSTD 0x10 /* SCSI Reset Detected */ 275 #define DISCD 0x08 /* Disconnected Status */ 276 #define SELED 0x04 /* Select Interrupt */ 277 #define SCAMSCT 0x02 /* SCAM selected */ 278 #define SCMDN 0x01 /* Command Complete */ 279 #define TUL_SIEN 0x84 /* W Interrupt enable */ 280 #define ALL_INTERRUPTS 0xff 281 #define TUL_STAT0 0x85 /* R Status 0 */ 282 #define INTPD 0x80 /* Interrupt pending */ 283 #define SQACT 0x40 /* Sequencer active */ 284 #define XFCZ 0x20 /* Xfer counter zero */ 285 #define SFEMP 0x10 /* FIFO empty */ 286 #define SPERR 0x08 /* SCSI parity error */ 287 #define PH_MASK 0x07 /* SCSI phase mask */ 288 #define TUL_SCTRL0 0x85 /* W Control 0 */ 289 #define RSSQC 0x20 /* Reset sequence counter */ 290 #define RSFIFO 0x10 /* Flush FIFO */ 291 #define CMDAB 0x04 /* Abort command (sequence) */ 292 #define RSMOD 0x02 /* Reset SCSI Chip */ 293 #define RSCSI 0x01 /* Reset SCSI Bus */ 294 #define TUL_STAT1 0x86 /* R Status 1 */ 295 #define STRCV 0x80 /* Status received */ 296 #define MSGST 0x40 /* Message sent */ 297 #define CPDNE 0x20 /* Data phase done */ 298 #define DPHDN 0x10 /* Data phase done */ 299 #define STSNT 0x08 /* Status sent */ 300 #define SXCMP 0x04 /* Xfer completed */ 301 #define SLCMP 0x02 /* Selection completed */ 302 #define ARBCMP 0x01 /* Arbitration completed */ 303 #define TUL_SCTRL1 0x86 /* W Control 1 */ 304 #define ENSCAM 0x80 /* Enable SCAM */ 305 #define NIDARB 0x40 /* No ID for Arbitration */ 306 #define ENLRS 0x20 /* Low Level Reselect */ 307 #define PWDN 0x10 /* Power down mode */ 308 #define WCPU 0x08 /* Wide CPU */ 309 #define EHRSL 0x04 /* Enable HW reselect */ 310 #define ESBUSOUT 0x02 /* Enable SCSI data bus out latch */ 311 #define ESBUSIN 0x01 /* Enable SCSI data bus in latch */ 312 #define TUL_SSTATUS2 0x87 /* R Status 2 */ 313 #define SABRT 0x80 /* Command aborted */ 314 #define OSCZ 0x40 /* Offset counter zero */ 315 #define SFFUL 0x20 /* FIFO full */ 316 #define TMCZ 0x10 /* Timeout counter zero */ 317 #define BSYGN 0x08 /* Busy release */ 318 #define PHMIS 0x04 /* Phase mismatch */ 319 #define SBEN 0x02 /* SCSI data bus enable */ 320 #define SRST 0x01 /* SCSI bus reset in progress */ 321 #define TUL_SCONFIG0 0x87 /* W Configuration */ 322 #define PHLAT 0x80 /* Enable phase latch */ 323 #define ITMOD 0x40 /* Initiator mode */ 324 #define SPCHK 0x20 /* Enable SCSI parity */ 325 #define ADMA8 0x10 /* Alternate dma 8-bits mode */ 326 #define ADMAW 0x08 /* Alternate dma 16-bits mode */ 327 #define EDACK 0x04 /* Enable DACK in wide SCSI xfer */ 328 #define ALTPD 0x02 /* Alternate sync period mode */ 329 #define DSRST 0x01 /* Disable SCSI Reset signal */ 330 #define SCONFIG0DEFAULT (PHLAT | ITMOD | ALTPD | DSRST) 331 #define TUL_SOFSC 0x88 /* R Offset */ 332 #define TUL_SYNCM 0x88 /* W Sync. Xfer Period & Offset */ 333 #define TUL_SBID 0x89 /* R SCSI BUS ID */ 334 #define TUL_SID 0x89 /* W SCSI ID */ 335 #define TUL_SALVC 0x8A /* R FIFO Avail Cnt/Identify Msg */ 336 #define TUL_STIMO 0x8A /* W Sel/Resel Time Out Register */ 337 #define TUL_SDATI 0x8B /* R SCSI Bus contents */ 338 #define TUL_SDAT0 0x8B /* W SCSI Data Out */ 339 #define TUL_SFIFO 0x8C /* R/W FIFO */ 340 #define TUL_SSIGI 0x90 /* R SCSI signal in */ 341 #define REQ 0x80 /* REQ signal */ 342 #define ACK 0x40 /* ACK signal */ 343 #define BSY 0x20 /* BSY signal */ 344 #define SEL 0x10 /* SEL signal */ 345 #define ATN 0x08 /* ATN signal */ 346 #define MSG 0x04 /* MSG signal */ 347 #define CD 0x02 /* C/D signal */ 348 #define IO 0x01 /* I/O signal */ 349 #define TUL_SSIGO 0x90 /* W SCSI signal out */ 350 #define TUL_SCMD 0x91 /* R/W SCSI Command */ 351 #define NO_OP 0x00 /* Place Holder for tulip_wait() */ 352 #define SEL_NOATN 0x01 /* Select w/o ATN Sequence */ 353 #define XF_FIFO_OUT 0x03 /* FIFO Xfer Information out */ 354 #define MSG_ACCEPT 0x0F /* Message Accept */ 355 #define SEL_ATN 0x11 /* Select w ATN Sequence */ 356 #define SEL_ATNSTOP 0x12 /* Select w ATN & Stop Sequence */ 357 #define SELATNSTOP 0x1E /* Select w ATN & Stop Sequence */ 358 #define SEL_ATN3 0x31 /* Select w ATN3 Sequence */ 359 #define XF_DMA_OUT 0x43 /* DMA Xfer Information out */ 360 #define EN_RESEL 0x80 /* Enable Reselection */ 361 #define XF_FIFO_IN 0x83 /* FIFO Xfer Information in */ 362 #define CMD_COMP 0x84 /* Command Complete Sequence */ 363 #define XF_DMA_IN 0xC3 /* DMA Xfer Information in */ 364 #define TUL_STEST0 0x92 /* R/W Test0 */ 365 #define TUL_STEST1 0x93 /* R/W Test1 */ 366 367 /* 368 * Tulip (aka inic-940/950) DMA Registers 369 */ 370 #define TUL_DXPA 0xC0 /* R/W DMA Xfer Physcl Addr 0-31*/ 371 #define TUL_DXPAE 0xC4 /* R/W DMA Xfer Physcl Addr 32-63*/ 372 #define TUL_DCXA 0xC8 /* R DMA Curr Xfer Physcl Addr 0-31*/ 373 #define TUL_DCXAE 0xCC /* R DMA Curr Xfer Physcl Addr 32-63*/ 374 #define TUL_DXC 0xD0 /* R/W DMA Xfer Counter */ 375 #define TUL_DCXC 0xD4 /* R DMA Current Xfer Counter */ 376 #define TUL_DCMD 0xD8 /* R/W DMA Command Register */ 377 #define SGXFR 0x80 /* Scatter/Gather Xfer */ 378 #define RSVD 0x40 /* Reserved - always reads as 0 */ 379 #define XDIR 0x20 /* Xfer Direction 0/1 = out/in */ 380 #define BMTST 0x10 /* Bus Master Test */ 381 #define CLFIFO 0x08 /* Clear FIFO */ 382 #define ABTXFR 0x04 /* Abort Xfer */ 383 #define FRXFR 0x02 /* Force Xfer */ 384 #define STRXFR 0x01 /* Start Xfer */ 385 #define ST_X_IN (XDIR | STRXFR) 386 #define ST_X_OUT ( STRXFR) 387 #define ST_SG_IN (SGXFR | ST_X_IN) 388 #define ST_SG_OUT (SGXFR | ST_X_OUT) 389 #define TUL_ISTUS0 0xDC /* R/W Interrupt Status Register */ 390 #define DGINT 0x80 /* DMA Global Interrupt */ 391 #define RSVRD0 0x40 /* Reserved */ 392 #define RSVRD1 0x20 /* Reserved */ 393 #define SCMP 0x10 /* SCSI Complete */ 394 #define PXERR 0x08 /* PCI Xfer Error */ 395 #define DABT 0x04 /* DMA Xfer Aborted */ 396 #define FXCMP 0x02 /* Forced Xfer Complete */ 397 #define XCMP 0x01 /* Bus Master Xfer Complete */ 398 #define TUL_ISTUS1 0xDD /* R DMA status Register */ 399 #define SCBSY 0x08 /* SCSI Busy */ 400 #define FFULL 0x04 /* FIFO Full */ 401 #define FEMPT 0x02 /* FIFO Empty */ 402 #define XPEND 0x01 /* Xfer pending */ 403 #define TUL_IMSK 0xE0 /* R/W Interrupt Mask Register */ 404 #define MSCMP 0x10 /* Mask SCSI Complete */ 405 #define MPXFER 0x08 /* Mask PCI Xfer Error */ 406 #define MDABT 0x04 /* Mask Bus Master Abort */ 407 #define MFCMP 0x02 /* Mask Force Xfer Complete */ 408 #define MXCMP 0x01 /* Mask Bus Master Xfer Complete */ 409 #define MASK_ALL (MXCMP | MFCMP | MDABT | MPXFER | MSCMP) 410 #define TUL_DCTRL0 0xE4 /* R/W DMA Control Register */ 411 #define SXSTP 0x80 /* SCSI Xfer Stop */ 412 #define RPMOD 0x40 /* Reset PCI Module */ 413 #define RSVRD2 0x20 /* SCSI Xfer Stop */ 414 #define PWDWN 0x10 /* Power Down */ 415 #define ENTM 0x08 /* Enable SCSI Terminator Low */ 416 #define ENTMW 0x04 /* Enable SCSI Terminator High */ 417 #define DISAFC 0x02 /* Disable Auto Clear */ 418 #define LEDCTL 0x01 /* LED Control */ 419 #define TUL_DCTRL1 0xE5 /* R/W DMA Control Register 1 */ 420 #define SDWS 0x01 /* SCSI DMA Wait State */ 421 #define TUL_DFIFO 0xE8 /* R/W DMA FIFO */ 422 423 #define TUL_WCTRL 0xF7 /* ?/? Bus master wait state control */ 424 #define TUL_DCTRL 0xFB /* ?/? DMA delay control */ 425 426 /* Functions used by higher SCSI layers, the kernel, or iha.c and iha_pci.c */ 427 428 void iha_scsi_cmd(struct scsi_xfer *); 429 int iha_intr(void *); 430 int iha_init_tulip(struct iha_softc *); 431 432
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