The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/interwavereg.h

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    1 #ifndef INTERWAVEREG_H
    2 #define INTERWAVEREG_H
    3 
    4 /*      $NetBSD: interwavereg.h,v 1.8 2005/12/11 12:21:27 christos Exp $        */
    5 
    6 /*
    7  * Copyright (c) 1997 The NetBSD Foundation, Inc.
    8  * All rights reserved.
    9  *
   10  * Author: Kari Mettinen
   11  *
   12  * Redistribution and use in source and binary forms, with or without
   13  * modification, are permitted provided that the following conditions
   14  * are met:
   15  * 1. Redistributions of source code must retain the above copyright
   16  *    notice, this list of conditions and the following disclaimer.
   17  * 2. Redistributions in binary form must reproduce the above copyright
   18  *    notice, this list of conditions and the following disclaimer in the
   19  *    documentation and/or other materials provided with the distribution.
   20  * 3. All advertising materials mentioning features or use of this software
   21  *    must display the following acknowledgement:
   22  *        This product includes software developed by the NetBSD
   23  *        Foundation, Inc. and its contributors.
   24  * 4. Neither the name of The NetBSD Foundation nor the names of its
   25  *    contributors may be used to endorse or promote products derived
   26  *    from this software without specific prior written permission.
   27  *
   28  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   29  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   30  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   31  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   32  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   33  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   34  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   35  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   36  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   37  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   38  * POSSIBILITY OF SUCH DAMAGE.
   39  */
   40 
   41 
   42 #define IW_LINELEVEL_MAX        ((1L << 10) - 1)
   43 #define IW_LINELEVEL_CODEC_MAX  ((1L << 10) - 1)
   44 
   45 #define IW_OUTPUT_CLASS         10
   46 #define IW_INPUT_CLASS          11
   47 #define IW_RECORD_CLASS         12
   48 
   49 
   50 #define IW_MIC_IN               11
   51 #define IW_MIC_IN_LVL           0
   52 
   53 /* these 2 are hw dependent values */
   54 #define IW_RIGHT_MIC_IN_PORT    0x16
   55 #define IW_LEFT_MIC_IN_PORT     0x17
   56 
   57 #define IW_AUX1                 12
   58 #define IW_AUX1_LVL             1
   59 
   60 #define IW_RIGHT_AUX1_PORT      0x02
   61 #define IW_LEFT_AUX1_PORT       0x03
   62 
   63 #define IW_AUX2                 13
   64 #define IW_AUX2_LVL             2
   65 
   66 #define IW_RIGHT_AUX2_PORT      0x04
   67 #define IW_LEFT_AUX2_PORT       0x05
   68 
   69 #define IW_LINE_IN              14
   70 #define IW_LINE_IN_LVL          3
   71 
   72 #define IW_RIGHT_LINE_IN_PORT   0x12
   73 #define IW_LEFT_LINE_IN_PORT    0x13
   74 
   75 #define IW_LINE_OUT             15
   76 #define IW_LINE_OUT_LVL         4
   77 
   78 #define IW_RIGHT_LINE_OUT_PORT  0x19
   79 #define IW_LEFT_LINE_OUT_PORT   0x1b
   80 
   81 #define IW_RECORD_SOURCE        5
   82 
   83 #define IW_REC                  16
   84 #define IW_REC_LVL              6
   85 #define IW_REC_LEFT_PORT        0x00
   86 #define IW_REC_RIGHT_PORT       0x01
   87 
   88 #define IW_DAC                  18
   89 #define IW_DAC_LVL              7
   90 #define IW_LEFT_DAC_PORT        0x06
   91 #define IW_RIGHT_DAC_PORT       0x07
   92 
   93 #define IW_LOOPBACK             19
   94 #define IW_LOOPBACK_LVL         8
   95 #define IW_LOOPBACK_PORT        0x0d
   96 
   97 #define IW_MONO_IN              20
   98 #define IW_MONO_IN_LVL          9
   99 #define IW_MONO_IN_PORT         0x1a
  100 
  101 #define IW_LINE_IN_SRC          0
  102 #define IW_AUX1_SRC             1
  103 #define IW_MIC_IN_SRC           2
  104 #define IW_MIX_OUT_SRC          3
  105 
  106 
  107 /* DMA flags */
  108 
  109 #define IW_PLAYBACK 1L
  110 #define IW_RECORD   2L
  111 
  112 #define ADDR_HIGH(a)  (u_short)((a) >> 7)
  113 #define ADDR_LOW(a)   (u_short)((a) << 9)
  114 
  115 #define MIDI_TX_IRQ       0x01
  116 #define MIDI_RX_IRQ       0x02
  117 #define ALIB_TIMER1_IRQ   0x04
  118 #define ALIB_TIMER2_IRQ   0x08
  119 #define UASBCI            0x45          /* UASBCI index */
  120 #define SAMPLE_CONTROL    0x49          /* Not used by IW */
  121 #define SET_VOICES        0x0E
  122 #define SAVI_WR           0x0E
  123 #define WAVETABLE_IRQ     0x20
  124 #define ENVELOPE_IRQ      0x40
  125 #define DMA_TC_IRQ        0x80
  126 
  127 #define GEN_INDEX         0x03           /* IGIDX offset into p3xr */
  128 #define VOICE_SELECT      0x02           /* SVSR offset into p3xr */
  129 #define VOICE_IRQS        0x8F           /* SVII index (read) */
  130 #define URSTI             0x4C           /* URSTI index */
  131 #define GF1_SET           0x01           /* URSTI[0] */
  132 #define GF1_OUT_ENABLE    0x02           /* URSTI[1] */
  133 #define GF1_IRQ_ENABLE    0x04           /* URSTI[2] */
  134 #define GF1_RESET         0xFE           /* URSTI[0]=0 */
  135 #define VOICE_VOLUME_IRQ  0x04           /* SVII[2] */
  136 #define VOICE_WAVE_IRQ    0x08           /* SVII[3] */
  137 #define VC_IRQ_ENABLE     0x20           /* SACI[5] or SVCI[5]*/
  138 #define VOICE_NUMBER      0x1F           /* Mask for SVII[4:0] */
  139 #define VC_IRQ_PENDING    0x80           /* SACI[7] or SVCI[7] */
  140 #define VC_DIRECT         0x40           /* SACI[6] or SVCI[6]*/
  141 #define VC_DATA_WIDTH     0x04           /* SACI[2] */
  142 #define VOICE_STOP        0x02           /* SACI[1] */
  143 #define VOICE_STOPPED     0x01           /* SACI[0] */
  144 #define VOLUME_STOP       0x02           /* SVCI[1] */
  145 #define VOLUME_STOPPED    0x01           /* SVCI[0] */
  146 #define VC_ROLLOVER       0x04           /* SVCI[2] */
  147 #define VC_LOOP_ENABLE    0x08           /* SVCI[3] or SACI[3]*/
  148 #define VC_BI_LOOP        0x10           /* SVCI[4] or SACI[4]*/
  149 #define VOICE_OFFSET      0x20           /* SMSI[5] */
  150 #define VOLUME_RATE0      0x00           /* SVRI[7:6]=(0,0) */
  151 #define VOLUME_RATE1      0x40           /* SVRI[7:6]=(0,1) */
  152 #define VOLUME_RATE2      0x80           /* SVRI[7:6]=(1,0) */
  153 #define VOLUME_RATE3      0xC0           /* SVRI[7:6]=(1,1) */
  154 
  155 #define CSR1R             0x02
  156 #define CPDR              0x03
  157 #define CRDR              0x03
  158 
  159 #define SHUT_DOWN         0x7E           /* shuts InterWave down */
  160 #define POWER_UP          0xFE           /* enables all modules */
  161 #define CODEC_PWR_UP      0x81           /* enables Codec Analog Ckts */
  162 #define CODEC_PWR_DOWN    0x01           /* disables Codec Analog Ckts */
  163 #define CODEC_REC_UP      0x82           /* Enables Record Path */
  164 #define CODEC_REC_DOWN    0x02           /* Disables Record Path */
  165 #define CODEC_PLAY_UP     0x84           /* Enables Playback Path */
  166 #define CODEC_PLAY_DOWN   0x04           /* Disables Playback Path */
  167 #define CODEC_IRQ_ENABLE  0x02           /* CEXTI[2] */
  168 #define CODEC_TIMER_IRQ   0x40           /* CSR3I[6] */
  169 #define CODEC_REC_IRQ     0x20           /* CSR3I[5] */
  170 #define CODEC_PLAY_IRQ    0x10           /* CSR3I[4] */
  171 #define CODEC_INT         0x01           /* CSR1R[0] */
  172 #define MONO_INPUT        0x80           /* CMONOI[7] */
  173 #define MONO_OUTPUT       0x40           /* CMONOI[6] */
  174 #define MIDI_UP           0x88           /* Enables MIDI ports */
  175 #define MIDI_DOWN         0x08           /* Disables MIDI ports */
  176 #define SYNTH_UP          0x90           /* Enables Synthesizer */
  177 #define SYNTH_DOWN        0x10           /* Disables Synthesizer */
  178 #define LMC_UP            0xA0           /* Enables LM Module */
  179 #define LMC_DOWN          0x20           /* Disbales LM Module */
  180 #define XTAL24_UP         0xC0           /* Enables 24MHz Osc */
  181 #define XTAL24_DOWN       0x40           /* Disables 24MHz Osc */
  182 #define PPWRI             0xF2           /* PPWRI index */
  183 #define PLAY              0x0F
  184 #define REC               0x1F
  185 #define LEFT_AUX1_INPUT   0x02
  186 #define RIGHT_AUX1_INPUT  0x03
  187 #define LEFT_AUX2_INPUT   0x04
  188 #define RIGHT_AUX2_INPUT  0x05
  189 #define LEFT_LINE_IN      0x12
  190 #define RIGHT_LINE_IN     0x13
  191 #define LEFT_LINE_OUT     0x19
  192 #define RIGHT_LINE_OUT    0x1B
  193 #define LEFT_SOURCE       0x00
  194 #define RIGHT_SOURCE      0x01
  195 #define LINE_IN           0x00
  196 #define AUX1_IN           0x40
  197 #define MIC_IN            0x80
  198 #define MIX_IN            0xC0
  199 #define LEFT_DAC          0x06
  200 #define RIGHT_DAC         0x07
  201 #define LEFT_MIC_IN       0x16
  202 #define RIGHT_MIC_IN      0x17
  203 #define CUPCTI            0x0E
  204 #define CLPCTI            0x0F
  205 #define CURCTI            0x1E
  206 #define CLRCTI            0x1F
  207 #define CLAX1I            0x02
  208 #define CRAX1I            0x03
  209 #define CLAX2I            0x04
  210 #define CRAX2I            0x05
  211 #define CLLICI            0x12
  212 #define CRLICI            0x13
  213 #define CLOAI             0x19
  214 #define CROAI             0x1B
  215 #define CLICI             0x00
  216 #define CRICI             0x01
  217 #define CLDACI            0x06
  218 #define CRDACI            0x07
  219 #define CPVFI             0x1D
  220 
  221 #define MAX_DMA           0x07
  222 #define DMA_DECREMENT     0x20
  223 #define AUTO_INIT         0x10
  224 #define DMA_READ          0x01
  225 #define DMA_WRITE         0x02
  226 #define AUTO_READ         0x03
  227 #define AUTO_WRITE        0x04
  228 #define IDMA_INV          0x0400
  229 #define IDMA_WIDTH_16     0x0100
  230 
  231 #define LDMACI            0x41  /* Index */
  232 #define DMA_INV           0x80
  233 #define DMA_IRQ_ENABLE    0x20
  234 #define DMA_IRQ_PENDING   0x40  /* on reads of LDMACI[6] */
  235 #define DMA_DATA_16       0x40  /* on writes to LDMACI[6] */
  236 #define DMA_WIDTH_16      0x04  /* 1=16-bit, 0=8-bit (DMA channel) */
  237 #define DMA_RATE          0x18  /* 00=fastest,...,11=slowest */
  238 #define DMA_UPLOAD        0x02  /* From LM to PC */
  239 #define DMA_ENABLE        0x01
  240 
  241 #define GUS_MODE          0x00  /* SGMI[0]=0 */
  242 #define ENH_MODE          0x01  /* SGMI[0]=1 */
  243 #define ENABLE_LFOS       0x02  /* SGMI[1] */
  244 #define NO_WAVETABLE      0x04  /* SGMI[2] */
  245 #define RAM_TEST          0x08  /* SGMI[3] */
  246 
  247 #define DMA_SET_MASK      0x04
  248 
  249 #define VOICE_STOP        0x02           /* SACI[1] */
  250 #define VOICE_STOPPED     0x01           /* SACI[0] */
  251 
  252 #define LDSALI            0x42
  253 #define LDSAHI            0x50
  254 #define LMALI             0x43
  255 #define LMAHI             0x44
  256 #define LMCFI             0x52
  257 #define LMCI              0x53
  258 #define LMFSI             0x56
  259 #define LDIBI             0x58
  260 #define LDICI             0x57
  261 #define LMSBAI            0x51
  262 #define LMRFAI            0x54
  263 #define LMPFAI            0x55
  264 #define SVCI_RD           0x8D
  265 #define SVCI_WR           0x0D
  266 #define SACI_RD           0x80
  267 #define SACI_WR           0x00
  268 #define SALI_RD           0x8B
  269 #define SALI_WR           0x0B
  270 #define SAHI_RD           0x8A
  271 #define SAHI_WR           0x0A
  272 #define SASHI_RD          0x82
  273 #define SASHI_WR          0x02
  274 #define SASLI_RD          0x83
  275 #define SASLI_WR          0x03
  276 #define SAEHI_RD          0x84
  277 #define SAEHI_WR          0x04
  278 #define SAELI_RD          0x85
  279 #define SAELI_WR          0x05
  280 #define SVRI_RD           0x86
  281 #define SVRI_WR           0x06
  282 #define SVSI_RD           0x87
  283 #define SVSI_WR           0x07
  284 #define SVEI_RD           0x88
  285 #define SVEI_WR           0x08
  286 #define SVLI_RD           0x89
  287 #define SVLI_WR           0x09
  288 #define SROI_RD           0x8C
  289 #define SROI_WR           0x0C
  290 #define SLOI_RD           0x93
  291 #define SLOI_WR           0x13
  292 #define SMSI_RD           0x95
  293 #define SMSI_WR           0x15
  294 #define SGMI_RD           0x99
  295 #define SGMI_WR           0x19
  296 #define SFCI_RD           0x81
  297 #define SFCI_WR           0x01
  298 #define SUAI_RD           0x90
  299 #define SUAI_WR           0x10
  300 #define SVII              0x8F
  301 #define CMODEI            0x0C        /* index for CMODEI */
  302 #define CMONOI            0x1A
  303 #define CFIG3I            0x11
  304 #define CFIG2I            0x10
  305 #define CLTIMI            0x14
  306 #define CUTIMI            0x15
  307 #define CSR3I             0x18        /* Index to CSR3I (Interrupt Status) */
  308 #define CEXTI             0x0A        /* Index to External Control Register */
  309 #define CFIG1I            0x09        /* Index to Codec Conf Reg 1 */
  310 #define CSR2I             0x0B        /* Index to Codec Stat Reg 2 */
  311 #define CPDFI             0x08        /* Index to Play Data Format Reg */
  312 #define CRDFI             0x1C        /* Index to Rec Data Format Reg */
  313 #define CLMICI            0x16        /* Index to Left Mic Input Ctrl Register */
  314 #define CRMICI            0x17        /* Index to Right Mic Input Ctrl Register */
  315 #define CLCI              0x0D        /* Index to Loopback Ctrl Register */
  316 #define IVERI             0x5B        /* Index to register IVERI */
  317 #define IDECI             0x5A
  318 #define ICMPTI            0x59
  319 #define CODEC_MODE1       0x00
  320 #define CODEC_MODE2       0x40
  321 #define CODEC_MODE3       0x6C        /* Enhanced Mode */
  322 #define CODEC_STATUS1     0x01
  323 #define CODEC_STATUS2     0x0B        /* Index to CSR2I */
  324 #define CODEC_STATUS3     0x18        /* Index to CSR3I */
  325 #define PLAYBACK          0x01        /* Enable playback path CFIG1I[0]=1*/
  326 #define RECORD            0x02        /* Enable Record path CFIG1I[1]=1*/
  327 #define TIMER_ENABLE      0x40        /* CFIG2I[6] */
  328 #define CODEC_MCE         0x40        /* CIDXR[6] */
  329 #define CALIB_IN_PROGRESS 0x20        /* CSR2I[5] */
  330 #define CODEC_INIT        0x80        /* CIDXR[7] */
  331 #define BIT16_BIG         0xC0        /* 16-bit signed, big endian */
  332 #define IMA_ADPCM         0xA0        /* IMA-compliant ADPCM */
  333 #define BIT8_ALAW         0x60        /* 8-bit A-law */
  334 #define BIT16_LITTLE      0x40        /* 16-bit signed, little endian */
  335 #define BIT8_ULAW         0x20        /* 8-bit mu-law */
  336 #define BIT8_LINEAR       0x00        /* 8-bit unsigned */
  337 #define REC_DFORMAT       0x1C
  338 #define PLAY_DFORMAT      0x08
  339 #define DMA_ACCESS        0x00
  340 #define PIO_ACCESS        0xC0
  341 #define DMA_SIMPLEX       0x04
  342 #define STEREO            0x10        /* CxDFI[4] */
  343 #define AUTOCALIB         0x08        /* CFIG1I[3] */
  344 #define ROM_IO            0x02        /* ROM I/O cycles - LMCI[1]=1 */
  345 #define DRAM_IO           0x4D        /* DRAM I/O cycles - LMCI[1]=0 */
  346 #define AUTOI             0x01        /* LMCI[0]=1 */
  347 #define PLDNI             0x07
  348 #define ACTIVATE_DEV      0x30
  349 #define PWAKEI            0x03        /* Index for PWAKEI */
  350 #define PISOCI            0x01        /* Index for PISOCI */
  351 #define PSECI             0xF1        /* Index for PSECI */
  352 #define RANGE_IOCHK       0x31        /* PURCI or PRRCI Index */
  353 #define MIDI_RESET        0x03
  354 
  355 #define IW_DMA_RECORD     0x02
  356 #define IW_DMA_PLAYBACK   0x01
  357 
  358 #define IW_MCE            0x40
  359 
  360 #define IN                0
  361 #define OUT               1
  362 
  363 /* codec indirect register access */
  364 
  365 #define IW_WRITE_CODEC_1(reg, val) \
  366 do {\
  367         bus_space_write_1(sc->sc_iot, sc->codec_index_h, 0, (u_char)(reg));\
  368         bus_space_write_1(sc->sc_iot, sc->codec_index_h, sc->cdatap, (u_char)val);\
  369         bus_space_write_1(sc->sc_iot, sc->codec_index_h, 0, 0);\
  370 } while (0)\
  371 
  372 #define IW_READ_CODEC_1(reg, ret) \
  373 do {\
  374         bus_space_write_1(sc->sc_iot, sc->codec_index_h, sc->codec_index, (u_char)(reg));\
  375         ret = bus_space_read_1(sc->sc_iot, sc->codec_index_h, sc->cdatap);\
  376         bus_space_write_1(sc->sc_iot, sc->codec_index_h, 0, 0);\
  377 } while (0)\
  378 
  379 /* iw direct register access */
  380 
  381 #define IW_WRITE_DIRECT_1(reg, h, val) \
  382 do {\
  383         bus_space_write_1(sc->sc_iot, h, reg, (u_char)val);\
  384 } while (0)\
  385 
  386 #define IW_READ_DIRECT_1(reg, h, ret) \
  387 do {\
  388         ret = bus_space_read_1(sc->sc_iot, h, (u_char)reg);\
  389 } while (0)\
  390 
  391 /* general indexed regs access */
  392 
  393 #define IW_WRITE_GENERAL_1(reg, val) \
  394 do {\
  395         bus_space_write_1(sc->sc_iot, sc->p3xr_h, 3, (u_char)reg);\
  396         bus_space_write_1(sc->sc_iot, sc->p3xr_h, 5, (u_char)val);\
  397 } while (0)\
  398 
  399 #define IW_WRITE_GENERAL_2(reg, val) \
  400 do {\
  401         bus_space_write_1(sc->sc_iot, sc->p3xr_h, 3, (u_char)reg);\
  402         bus_space_write_2(sc->sc_iot, sc->p3xr_h, 4, (u_short)val);\
  403 } while (0)\
  404 
  405 #define IW_READ_GENERAL_1(reg, ret) \
  406 do{\
  407         bus_space_write_1(sc->sc_iot, sc->p3xr_h, 3, (u_char)reg);\
  408         ret = bus_space_read_1(sc->sc_iot, sc->p3xr_h, 5);\
  409 } while (0)\
  410 
  411 #define IW_READ_GENERAL_2(reg, ret) \
  412 do{\
  413         bus_space_write_1(sc->sc_iot, sc->p3xr_h, 3, (u_char)reg);\
  414         ret = bus_space_read_2(sc->sc_iot, sc->p3xr_h, 4);\
  415 } while (0)\
  416 
  417 
  418 #endif /* INTERWAVEREG_H */

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