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sys/dev/ic/lsi64854.c
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1 /* $NetBSD: lsi64854.c,v 1.27 2005/12/11 12:21:27 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: lsi64854.c,v 1.27 2005/12/11 12:21:27 christos Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/errno.h> 46 #include <sys/device.h> 47 #include <sys/malloc.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <machine/bus.h> 52 #include <machine/autoconf.h> 53 #include <machine/cpu.h> 54 55 #include <dev/scsipi/scsi_all.h> 56 #include <dev/scsipi/scsipi_all.h> 57 #include <dev/scsipi/scsiconf.h> 58 59 #include <dev/ic/lsi64854reg.h> 60 #include <dev/ic/lsi64854var.h> 61 62 #include <dev/ic/ncr53c9xreg.h> 63 #include <dev/ic/ncr53c9xvar.h> 64 65 void lsi64854_reset(struct lsi64854_softc *); 66 int lsi64854_setup(struct lsi64854_softc *, caddr_t *, size_t *, 67 int, size_t *); 68 int lsi64854_setup_pp(struct lsi64854_softc *, caddr_t *, size_t *, 69 int, size_t *); 70 71 #ifdef DEBUG 72 #define LDB_SCSI 1 73 #define LDB_ENET 2 74 #define LDB_PP 4 75 #define LDB_ANY 0xff 76 int lsi64854debug = 0; 77 #define DPRINTF(a,x) do { if (lsi64854debug & (a)) printf x ; } while (0) 78 #else 79 #define DPRINTF(a,x) 80 #endif 81 82 #define MAX_DMA_SZ (16*1024*1024) 83 84 /* 85 * Finish attaching this DMA device. 86 * Front-end must fill in these fields: 87 * sc_bustag 88 * sc_dmatag 89 * sc_regs 90 * sc_burst 91 * sc_channel (one of SCSI, ENET, PP) 92 * sc_client (one of SCSI, ENET, PP `soft_c' pointers) 93 */ 94 void 95 lsi64854_attach(sc) 96 struct lsi64854_softc *sc; 97 { 98 u_int32_t csr; 99 100 /* Indirect functions */ 101 switch (sc->sc_channel) { 102 case L64854_CHANNEL_SCSI: 103 sc->intr = lsi64854_scsi_intr; 104 sc->setup = lsi64854_setup; 105 break; 106 case L64854_CHANNEL_ENET: 107 sc->intr = lsi64854_enet_intr; 108 break; 109 case L64854_CHANNEL_PP: 110 sc->setup = lsi64854_setup_pp; 111 break; 112 default: 113 printf("%s: unknown channel\n", sc->sc_dev.dv_xname); 114 } 115 sc->reset = lsi64854_reset; 116 117 /* Allocate a dmamap */ 118 if (bus_dmamap_create(sc->sc_dmatag, MAX_DMA_SZ, 1, MAX_DMA_SZ, 119 0, BUS_DMA_WAITOK, &sc->sc_dmamap) != 0) { 120 printf("%s: DMA map create failed\n", sc->sc_dev.dv_xname); 121 return; 122 } 123 124 csr = L64854_GCSR(sc); 125 sc->sc_rev = csr & L64854_DEVID; 126 if (sc->sc_rev == DMAREV_HME) { 127 return; 128 } 129 printf(": DMA rev "); 130 switch (sc->sc_rev) { 131 case DMAREV_0: 132 printf(""); 133 break; 134 case DMAREV_ESC: 135 printf("esc"); 136 break; 137 case DMAREV_1: 138 printf("1"); 139 break; 140 case DMAREV_PLUS: 141 printf("1+"); 142 break; 143 case DMAREV_2: 144 printf("2"); 145 break; 146 default: 147 printf("unknown (0x%x)", sc->sc_rev); 148 } 149 150 DPRINTF(LDB_ANY, (", burst 0x%x, csr 0x%x", sc->sc_burst, csr)); 151 printf("\n"); 152 } 153 154 /* 155 * DMAWAIT waits while condition is true 156 */ 157 #define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \ 158 int count = 500000; \ 159 while ((COND) && --count > 0) DELAY(1); \ 160 if (count == 0) { \ 161 printf("%s: line %d: CSR = 0x%lx\n", __FILE__, __LINE__, \ 162 (u_long)L64854_GCSR(SC)); \ 163 if (DONTPANIC) \ 164 printf(MSG); \ 165 else \ 166 panic(MSG); \ 167 } \ 168 } while (0) 169 170 #define DMA_DRAIN(sc, dontpanic) do { \ 171 u_int32_t _csr; \ 172 /* \ 173 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 174 * and "drain" bits while it is still thinking about a \ 175 * request. \ 176 * other revs: D_ESC_R_PEND bit reads as 0 \ 177 */ \ 178 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 179 if (sc->sc_rev != DMAREV_HME) { \ 180 /* \ 181 * Select drain bit based on revision \ 182 * also clears errors and D_TC flag \ 183 */ \ 184 _csr = L64854_GCSR(sc); \ 185 if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \ 186 _csr |= D_ESC_DRAIN; \ 187 else \ 188 _csr |= L64854_INVALIDATE; \ 189 \ 190 L64854_SCSR(sc,_csr); \ 191 } \ 192 /* \ 193 * Wait for draining to finish \ 194 * rev0 & rev1 call this PACKCNT \ 195 */ \ 196 DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", dontpanic);\ 197 } while(0) 198 199 #define DMA_FLUSH(sc, dontpanic) do { \ 200 u_int32_t _csr; \ 201 /* \ 202 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 203 * and "drain" bits while it is still thinking about a \ 204 * request. \ 205 * other revs: D_ESC_R_PEND bit reads as 0 \ 206 */ \ 207 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 208 _csr = L64854_GCSR(sc); \ 209 _csr &= ~(L64854_WRITE|L64854_EN_DMA); /* no-ops on ENET */ \ 210 _csr |= L64854_INVALIDATE; /* XXX FAS ? */ \ 211 L64854_SCSR(sc,_csr); \ 212 } while(0) 213 214 void 215 lsi64854_reset(sc) 216 struct lsi64854_softc *sc; 217 { 218 u_int32_t csr; 219 220 DMA_FLUSH(sc, 1); 221 csr = L64854_GCSR(sc); 222 223 DPRINTF(LDB_ANY, ("lsi64854_reset: csr 0x%x\n", csr)); 224 225 /* 226 * XXX is sync needed? 227 */ 228 if (sc->sc_dmamap->dm_nsegs > 0) 229 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 230 231 if (sc->sc_rev == DMAREV_HME) 232 L64854_SCSR(sc, csr | D_HW_RESET_FAS366); 233 234 235 csr |= L64854_RESET; /* reset DMA */ 236 L64854_SCSR(sc, csr); 237 DELAY(200); /* > 10 Sbus clocks(?) */ 238 239 /*DMAWAIT1(sc); why was this here? */ 240 csr = L64854_GCSR(sc); 241 csr &= ~L64854_RESET; /* de-assert reset line */ 242 L64854_SCSR(sc, csr); 243 DELAY(5); /* allow a few ticks to settle */ 244 245 csr = L64854_GCSR(sc); 246 csr |= L64854_INT_EN; /* enable interrupts */ 247 if (sc->sc_rev > DMAREV_1 && sc->sc_channel == L64854_CHANNEL_SCSI) { 248 if (sc->sc_rev == DMAREV_HME) 249 csr |= D_TWO_CYCLE; 250 else 251 csr |= D_FASTER; 252 } 253 254 /* Set burst */ 255 switch (sc->sc_rev) { 256 case DMAREV_HME: 257 case DMAREV_2: 258 csr &= ~L64854_BURST_SIZE; 259 if (sc->sc_burst == 32) { 260 csr |= L64854_BURST_32; 261 } else if (sc->sc_burst == 16) { 262 csr |= L64854_BURST_16; 263 } else { 264 csr |= L64854_BURST_0; 265 } 266 break; 267 case DMAREV_ESC: 268 csr |= D_ESC_AUTODRAIN; /* Auto-drain */ 269 if (sc->sc_burst == 32) { 270 csr &= ~D_ESC_BURST; 271 } else 272 csr |= D_ESC_BURST; 273 break; 274 default: 275 break; 276 } 277 L64854_SCSR(sc, csr); 278 279 if (sc->sc_rev == DMAREV_HME) { 280 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 0); 281 sc->sc_dmactl = csr; 282 } 283 sc->sc_active = 0; 284 285 DPRINTF(LDB_ANY, ("lsi64854_reset: done, csr 0x%x\n", csr)); 286 } 287 288 289 #define DMAMAX(a) (MAX_DMA_SZ - ((a) & (MAX_DMA_SZ-1))) 290 /* 291 * setup a DMA transfer 292 */ 293 int 294 lsi64854_setup(sc, addr, len, datain, dmasize) 295 struct lsi64854_softc *sc; 296 caddr_t *addr; 297 size_t *len; 298 int datain; 299 size_t *dmasize; /* IN-OUT */ 300 { 301 u_int32_t csr; 302 303 DMA_FLUSH(sc, 0); 304 305 #if 0 306 DMACSR(sc) &= ~D_INT_EN; 307 #endif 308 sc->sc_dmaaddr = addr; 309 sc->sc_dmalen = len; 310 311 /* 312 * the rules say we cannot transfer more than the limit 313 * of this DMA chip (64k for old and 16Mb for new), 314 * and we cannot cross a 16Mb boundary. 315 */ 316 *dmasize = sc->sc_dmasize = 317 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 318 319 DPRINTF(LDB_ANY, ("dma_setup: dmasize = %ld\n", (long)sc->sc_dmasize)); 320 321 /* 322 * XXX what length? 323 */ 324 if (sc->sc_rev == DMAREV_HME) { 325 326 L64854_SCSR(sc, sc->sc_dmactl | L64854_RESET); 327 L64854_SCSR(sc, sc->sc_dmactl); 328 329 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, *dmasize); 330 } 331 332 /* Program the DMA address */ 333 if (sc->sc_dmasize) { 334 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 335 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, 336 *sc->sc_dmaaddr, sc->sc_dmasize, 337 NULL /* kernel address */, 338 BUS_DMA_NOWAIT | BUS_DMA_STREAMING)) 339 panic("%s: cannot allocate DVMA address", 340 sc->sc_dev.dv_xname); 341 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 342 datain 343 ? BUS_DMASYNC_PREREAD 344 : BUS_DMASYNC_PREWRITE); 345 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 346 sc->sc_dmamap->dm_segs[0].ds_addr); 347 } 348 349 if (sc->sc_rev == DMAREV_ESC) { 350 /* DMA ESC chip bug work-around */ 351 long bcnt = sc->sc_dmasize; 352 long eaddr = bcnt + (long)*sc->sc_dmaaddr; 353 if ((eaddr & PGOFSET) != 0) 354 bcnt = roundup(bcnt, PAGE_SIZE); 355 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, 356 bcnt); 357 } 358 359 /* Setup DMA control register */ 360 csr = L64854_GCSR(sc); 361 362 if (datain) 363 csr |= L64854_WRITE; 364 else 365 csr &= ~L64854_WRITE; 366 csr |= L64854_INT_EN; 367 368 if (sc->sc_rev == DMAREV_HME) { 369 csr |= (D_DSBL_SCSI_DRN | D_EN_DMA); 370 } 371 372 L64854_SCSR(sc, csr); 373 374 return (0); 375 } 376 377 /* 378 * Pseudo (chained) interrupt from the esp driver to kick the 379 * current running DMA transfer. Called from ncr53c9x_intr() 380 * for now. 381 * 382 * return 1 if it was a DMA continue. 383 */ 384 int 385 lsi64854_scsi_intr(arg) 386 void *arg; 387 { 388 struct lsi64854_softc *sc = arg; 389 struct ncr53c9x_softc *nsc = sc->sc_client; 390 char bits[64]; 391 int trans, resid; 392 u_int32_t csr; 393 394 csr = L64854_GCSR(sc); 395 396 DPRINTF(LDB_SCSI, ("%s: dmaintr: addr 0x%x, csr %s\n", sc->sc_dev.dv_xname, 397 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR), 398 bitmask_snprintf(csr, DDMACSR_BITS, bits, sizeof(bits)))); 399 400 if (csr & (D_ERR_PEND|D_SLAVE_ERR)) { 401 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, 402 bitmask_snprintf(csr, DDMACSR_BITS, bits,sizeof(bits))); 403 csr &= ~D_EN_DMA; /* Stop DMA */ 404 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 405 csr |= D_INVALIDATE|D_SLAVE_ERR; 406 L64854_SCSR(sc, csr); 407 return (-1); 408 } 409 410 /* This is an "assertion" :) */ 411 if (sc->sc_active == 0) 412 panic("dmaintr: DMA wasn't active"); 413 414 DMA_DRAIN(sc, 0); 415 416 /* DMA has stopped */ 417 csr &= ~D_EN_DMA; 418 L64854_SCSR(sc, csr); 419 sc->sc_active = 0; 420 421 if (sc->sc_dmasize == 0) { 422 /* A "Transfer Pad" operation completed */ 423 DPRINTF(LDB_SCSI, ("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 424 NCR_READ_REG(nsc, NCR_TCL) | 425 (NCR_READ_REG(nsc, NCR_TCM) << 8), 426 NCR_READ_REG(nsc, NCR_TCL), 427 NCR_READ_REG(nsc, NCR_TCM))); 428 return 0; 429 } 430 431 resid = 0; 432 /* 433 * If a transfer onto the SCSI bus gets interrupted by the device 434 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 435 * as residual since the NCR53C9X counter registers get decremented 436 * as bytes are clocked into the FIFO. 437 */ 438 if (!(csr & D_WRITE) && 439 (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 440 DPRINTF(LDB_SCSI, ("dmaintr: empty esp FIFO of %d ", resid)); 441 if (nsc->sc_rev == NCR_VARIANT_FAS366 && 442 (NCR_READ_REG(nsc, NCR_CFG3) & NCRFASCFG3_EWIDE)) 443 resid <<= 1; 444 } 445 446 if ((nsc->sc_espstat & NCRSTAT_TC) == 0) { 447 /* 448 * `Terminal count' is off, so read the residue 449 * out of the NCR53C9X counter registers. 450 */ 451 resid += (NCR_READ_REG(nsc, NCR_TCL) | 452 (NCR_READ_REG(nsc, NCR_TCM) << 8) | 453 ((nsc->sc_cfg2 & NCRCFG2_FE) 454 ? (NCR_READ_REG(nsc, NCR_TCH) << 16) 455 : 0)); 456 457 if (resid == 0 && sc->sc_dmasize == 65536 && 458 (nsc->sc_cfg2 & NCRCFG2_FE) == 0) 459 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 460 resid = 65536; 461 } 462 463 trans = sc->sc_dmasize - resid; 464 if (trans < 0) { /* transferred < 0 ? */ 465 #if 0 466 /* 467 * This situation can happen in perfectly normal operation 468 * if the ESP is reselected while using DMA to select 469 * another target. As such, don't print the warning. 470 */ 471 printf("%s: xfer (%d) > req (%d)\n", 472 sc->sc_dev.dv_xname, trans, sc->sc_dmasize); 473 #endif 474 trans = sc->sc_dmasize; 475 } 476 477 DPRINTF(LDB_SCSI, ("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 478 NCR_READ_REG(nsc, NCR_TCL), 479 NCR_READ_REG(nsc, NCR_TCM), 480 (nsc->sc_cfg2 & NCRCFG2_FE) 481 ? NCR_READ_REG(nsc, NCR_TCH) : 0, 482 trans, resid)); 483 484 if (sc->sc_dmamap->dm_nsegs > 0) { 485 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 486 (csr & D_WRITE) != 0 487 ? BUS_DMASYNC_POSTREAD 488 : BUS_DMASYNC_POSTWRITE); 489 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 490 } 491 492 *sc->sc_dmalen -= trans; 493 *sc->sc_dmaaddr += trans; 494 495 #if 0 /* this is not normal operation just yet */ 496 if (*sc->sc_dmalen == 0 || 497 nsc->sc_phase != nsc->sc_prevphase) 498 return 0; 499 500 /* and again */ 501 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE); 502 return 1; 503 #endif 504 return 0; 505 } 506 507 /* 508 * Pseudo (chained) interrupt to le driver to handle DMA errors. 509 */ 510 int 511 lsi64854_enet_intr(arg) 512 void *arg; 513 { 514 struct lsi64854_softc *sc = arg; 515 char bits[64]; 516 u_int32_t csr; 517 static int dodrain = 0; 518 int rv; 519 520 csr = L64854_GCSR(sc); 521 522 /* If the DMA logic shows an interrupt, claim it */ 523 rv = ((csr & E_INT_PEND) != 0) ? 1 : 0; 524 525 if (csr & (E_ERR_PEND|E_SLAVE_ERR)) { 526 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, 527 bitmask_snprintf(csr, EDMACSR_BITS, bits,sizeof(bits))); 528 csr &= ~L64854_EN_DMA; /* Stop DMA */ 529 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 530 csr |= E_INVALIDATE|E_SLAVE_ERR; 531 L64854_SCSR(sc, csr); 532 DMA_RESET(sc); 533 dodrain = 1; 534 return (1); 535 } 536 537 if (dodrain) { /* XXX - is this necessary with D_DSBL_WRINVAL on? */ 538 int i = 10; 539 csr |= E_DRAIN; 540 L64854_SCSR(sc, csr); 541 while (i-- > 0 && (L64854_GCSR(sc) & D_DRAINING)) 542 delay(1); 543 } 544 545 return (rv | (*sc->sc_intrchain)(sc->sc_intrchainarg)); 546 } 547 548 /* 549 * setup a DMA transfer 550 */ 551 int 552 lsi64854_setup_pp(sc, addr, len, datain, dmasize) 553 struct lsi64854_softc *sc; 554 caddr_t *addr; 555 size_t *len; 556 int datain; 557 size_t *dmasize; /* IN-OUT */ 558 { 559 u_int32_t csr; 560 561 DMA_FLUSH(sc, 0); 562 563 sc->sc_dmaaddr = addr; 564 sc->sc_dmalen = len; 565 566 DPRINTF(LDB_PP, ("%s: pp start %ld@%p,%d\n", sc->sc_dev.dv_xname, 567 (long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0)); 568 569 /* 570 * the rules say we cannot transfer more than the limit 571 * of this DMA chip (64k for old and 16Mb for new), 572 * and we cannot cross a 16Mb boundary. 573 */ 574 *dmasize = sc->sc_dmasize = 575 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 576 577 DPRINTF(LDB_PP, ("dma_setup_pp: dmasize = %ld\n", (long)sc->sc_dmasize)); 578 579 /* Program the DMA address */ 580 if (sc->sc_dmasize) { 581 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 582 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, 583 *sc->sc_dmaaddr, sc->sc_dmasize, 584 NULL /* kernel address */, 585 BUS_DMA_NOWAIT/*|BUS_DMA_COHERENT*/)) 586 panic("%s: pp cannot allocate DVMA address", 587 sc->sc_dev.dv_xname); 588 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 589 datain 590 ? BUS_DMASYNC_PREREAD 591 : BUS_DMASYNC_PREWRITE); 592 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 593 sc->sc_dmamap->dm_segs[0].ds_addr); 594 595 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, 596 sc->sc_dmasize); 597 } 598 599 /* Setup DMA control register */ 600 csr = L64854_GCSR(sc); 601 csr &= ~L64854_BURST_SIZE; 602 if (sc->sc_burst == 32) { 603 csr |= L64854_BURST_32; 604 } else if (sc->sc_burst == 16) { 605 csr |= L64854_BURST_16; 606 } else { 607 csr |= L64854_BURST_0; 608 } 609 csr |= P_EN_DMA|P_INT_EN|P_EN_CNT; 610 #if 0 611 /* This bit is read-only in PP csr register */ 612 if (datain) 613 csr |= P_WRITE; 614 else 615 csr &= ~P_WRITE; 616 #endif 617 L64854_SCSR(sc, csr); 618 619 return (0); 620 } 621 /* 622 * Parallel port DMA interrupt. 623 */ 624 int 625 lsi64854_pp_intr(arg) 626 void *arg; 627 { 628 struct lsi64854_softc *sc = arg; 629 char bits[64]; 630 int ret, trans, resid = 0; 631 u_int32_t csr; 632 633 csr = L64854_GCSR(sc); 634 635 DPRINTF(LDB_PP, ("%s: pp intr: addr 0x%x, csr %s\n", sc->sc_dev.dv_xname, 636 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR), 637 bitmask_snprintf(csr, PDMACSR_BITS, bits, sizeof(bits)))); 638 639 if (csr & (P_ERR_PEND|P_SLAVE_ERR)) { 640 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs, 641 L64854_REG_CNT); 642 printf("%s: pp error: resid %d csr=%s\n", sc->sc_dev.dv_xname, 643 resid, 644 bitmask_snprintf(csr, PDMACSR_BITS, bits,sizeof(bits))); 645 csr &= ~P_EN_DMA; /* Stop DMA */ 646 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 647 csr |= P_INVALIDATE|P_SLAVE_ERR; 648 L64854_SCSR(sc, csr); 649 return (1); 650 } 651 652 ret = (csr & P_INT_PEND) != 0; 653 654 if (sc->sc_active != 0) { 655 DMA_DRAIN(sc, 0); 656 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs, 657 L64854_REG_CNT); 658 } 659 660 /* DMA has stopped */ 661 csr &= ~D_EN_DMA; 662 L64854_SCSR(sc, csr); 663 sc->sc_active = 0; 664 665 trans = sc->sc_dmasize - resid; 666 if (trans < 0) { /* transferred < 0 ? */ 667 trans = sc->sc_dmasize; 668 } 669 *sc->sc_dmalen -= trans; 670 *sc->sc_dmaaddr += trans; 671 672 if (sc->sc_dmamap->dm_nsegs > 0) { 673 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 674 (csr & D_WRITE) != 0 675 ? BUS_DMASYNC_POSTREAD 676 : BUS_DMASYNC_POSTWRITE); 677 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 678 } 679 680 return (ret != 0); 681 }
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