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sys/dev/ic/mb89352.c
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1 /* $NetBSD: mb89352.c,v 1.26.2.1 2004/08/12 04:19:08 jmc Exp $ */ 2 /* NecBSD: mb89352.c,v 1.4 1998/03/14 07:31:20 kmatsuda Exp */ 3 4 /*- 5 * Copyright (c) 1996,97,98,99 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Charles M. Hannum, Masaru Oki and Kouichi Matsuda. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Charles M. Hannum. 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * Copyright (c) 1994 Jarle Greipsland 26 * All rights reserved. 27 * 28 * Redistribution and use in source and binary forms, with or without 29 * modification, are permitted provided that the following conditions 30 * are met: 31 * 1. Redistributions of source code must retain the above copyright 32 * notice, this list of conditions and the following disclaimer. 33 * 2. Redistributions in binary form must reproduce the above copyright 34 * notice, this list of conditions and the following disclaimer in the 35 * documentation and/or other materials provided with the distribution. 36 * 3. The name of the author may not be used to endorse or promote products 37 * derived from this software without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 40 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 41 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 42 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 43 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 44 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 45 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 46 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 47 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 48 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 49 * POSSIBILITY OF SUCH DAMAGE. 50 */ 51 /* 52 * [NetBSD for NEC PC-98 series] 53 * Copyright (c) 1996, 1997, 1998 54 * NetBSD/pc98 porting staff. All rights reserved. 55 * Copyright (c) 1996, 1997, 1998 56 * Kouichi Matsuda. All rights reserved. 57 */ 58 59 /* 60 * Acknowledgements: Many of the algorithms used in this driver are 61 * inspired by the work of Julian Elischer (julian@tfs.com) and 62 * Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million! 63 */ 64 65 /* TODO list: 66 * 1) Get the DMA stuff working. 67 * 2) Get the iov/uio stuff working. Is this a good thing ??? 68 * 3) Get the synch stuff working. 69 * 4) Rewrite it to use malloc for the acb structs instead of static alloc.? 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: mb89352.c,v 1.26.2.1 2004/08/12 04:19:08 jmc Exp $"); 74 75 #ifdef DDB 76 #define integrate 77 #else 78 #define integrate __inline static 79 #endif 80 81 /* 82 * A few customizable items: 83 */ 84 85 /* Synchronous data transfers? */ 86 #define SPC_USE_SYNCHRONOUS 0 87 #define SPC_SYNC_REQ_ACK_OFS 8 88 89 /* Wide data transfers? */ 90 #define SPC_USE_WIDE 0 91 #define SPC_MAX_WIDTH 0 92 93 /* Max attempts made to transmit a message */ 94 #define SPC_MSG_MAX_ATTEMPT 3 /* Not used now XXX */ 95 96 /* 97 * Some spin loop parameters (essentially how long to wait some places) 98 * The problem(?) is that sometimes we expect either to be able to transmit a 99 * byte or to get a new one from the SCSI bus pretty soon. In order to avoid 100 * returning from the interrupt just to get yanked back for the next byte we 101 * may spin in the interrupt routine waiting for this byte to come. How long? 102 * This is really (SCSI) device and processor dependent. Tuneable, I guess. 103 */ 104 #define SPC_MSGIN_SPIN 1 /* Will spinwait upto ?ms for a new msg byte */ 105 #define SPC_MSGOUT_SPIN 1 106 107 /* 108 * Include debug functions? At the end of this file there are a bunch of 109 * functions that will print out various information regarding queued SCSI 110 * commands, driver state and chip contents. You can call them from the 111 * kernel debugger. If you set SPC_DEBUG to 0 they are not included (the 112 * kernel uses less memory) but you lose the debugging facilities. 113 */ 114 #if 0 115 #define SPC_DEBUG 1 116 #endif 117 118 #define SPC_ABORT_TIMEOUT 2000 /* time to wait for abort */ 119 120 /* threshold length for DMA transfer */ 121 #define SPC_MIN_DMA_LEN 32 122 123 #ifdef x68k /* XXX it seems x68k SPC SCSI hardware has some quirks */ 124 #define NEED_DREQ_ON_HARDWARE_XFER 125 #define NO_MANUAL_XFER 126 #endif 127 128 /* End of customizable parameters */ 129 130 /* 131 * MB89352 SCSI Protocol Controller (SPC) routines. 132 */ 133 134 #include "opt_ddb.h" 135 136 #include <sys/param.h> 137 #include <sys/systm.h> 138 #include <sys/kernel.h> 139 #include <sys/errno.h> 140 #include <sys/ioctl.h> 141 #include <sys/device.h> 142 #include <sys/buf.h> 143 #include <sys/proc.h> 144 #include <sys/user.h> 145 #include <sys/queue.h> 146 147 #include <machine/intr.h> 148 #include <machine/bus.h> 149 150 #include <dev/scsipi/scsi_all.h> 151 #include <dev/scsipi/scsipi_all.h> 152 #include <dev/scsipi/scsi_message.h> 153 #include <dev/scsipi/scsiconf.h> 154 155 #include <dev/ic/mb89352reg.h> 156 #include <dev/ic/mb89352var.h> 157 158 #ifndef DDB 159 #define Debugger() panic("should call debugger here (mb89352.c)") 160 #endif /* ! DDB */ 161 162 #if SPC_DEBUG 163 int spc_debug = 0x00; /* SPC_SHOWSTART|SPC_SHOWMISC|SPC_SHOWTRACE; */ 164 #endif 165 166 void spc_done __P((struct spc_softc *, struct spc_acb *)); 167 void spc_dequeue __P((struct spc_softc *, struct spc_acb *)); 168 void spc_scsipi_request __P((struct scsipi_channel *, 169 scsipi_adapter_req_t, void *)); 170 int spc_poll __P((struct spc_softc *, struct scsipi_xfer *, int)); 171 integrate void spc_sched_msgout __P((struct spc_softc *, u_char)); 172 integrate void spc_setsync __P((struct spc_softc *, struct spc_tinfo *)); 173 void spc_select __P((struct spc_softc *, struct spc_acb *)); 174 void spc_timeout __P((void *)); 175 void spc_scsi_reset __P((struct spc_softc *)); 176 void spc_reset __P((struct spc_softc *)); 177 void spc_free_acb __P((struct spc_softc *, struct spc_acb *, int)); 178 struct spc_acb* spc_get_acb __P((struct spc_softc *)); 179 int spc_reselect __P((struct spc_softc *, int)); 180 void spc_msgin __P((struct spc_softc *)); 181 void spc_abort __P((struct spc_softc *, struct spc_acb *)); 182 void spc_msgout __P((struct spc_softc *)); 183 int spc_dataout_pio __P((struct spc_softc *, u_char *, int)); 184 int spc_datain_pio __P((struct spc_softc *, u_char *, int)); 185 #if SPC_DEBUG 186 void spc_print_acb __P((struct spc_acb *)); 187 void spc_dump_driver __P((struct spc_softc *)); 188 void spc_dump89352 __P((struct spc_softc *)); 189 void spc_show_scsi_cmd __P((struct spc_acb *)); 190 void spc_print_active_acb __P((void)); 191 #endif 192 193 extern struct cfdriver spc_cd; 194 195 /* 196 * INITIALIZATION ROUTINES (probe, attach ++) 197 */ 198 199 /* 200 * Do the real search-for-device. 201 * Prerequisite: sc->sc_iobase should be set to the proper value 202 */ 203 int 204 spc_find(iot, ioh, bdid) 205 bus_space_tag_t iot; 206 bus_space_handle_t ioh; 207 int bdid; 208 { 209 long timeout = SPC_ABORT_TIMEOUT; 210 211 SPC_TRACE(("spc: probing for spc-chip\n")); 212 /* 213 * Disable interrupts then reset the FUJITSU chip. 214 */ 215 bus_space_write_1(iot, ioh, SCTL, SCTL_DISABLE | SCTL_CTRLRST); 216 bus_space_write_1(iot, ioh, SCMD, 0); 217 bus_space_write_1(iot, ioh, PCTL, 0); 218 bus_space_write_1(iot, ioh, TEMP, 0); 219 bus_space_write_1(iot, ioh, TCH, 0); 220 bus_space_write_1(iot, ioh, TCM, 0); 221 bus_space_write_1(iot, ioh, TCL, 0); 222 bus_space_write_1(iot, ioh, INTS, 0); 223 bus_space_write_1(iot, ioh, SCTL, 224 SCTL_DISABLE | SCTL_ABRT_ENAB | SCTL_PARITY_ENAB | SCTL_RESEL_ENAB); 225 bus_space_write_1(iot, ioh, BDID, bdid); 226 delay(400); 227 bus_space_write_1(iot, ioh, SCTL, 228 bus_space_read_1(iot, ioh, SCTL) & ~SCTL_DISABLE); 229 230 /* The following detection is derived from spc.c 231 * (by Takahide Matsutsuka) in FreeBSD/pccard-test. 232 */ 233 while (bus_space_read_1(iot, ioh, PSNS) && timeout) { 234 timeout--; 235 DELAY(1); 236 } 237 if (timeout == 0) { 238 printf("spc: find failed\n"); 239 return 0; 240 } 241 242 SPC_START(("SPC found")); 243 return 1; 244 } 245 246 void 247 spc_attach(sc) 248 struct spc_softc *sc; 249 { 250 251 SPC_TRACE(("spc_attach ")); 252 sc->sc_state = SPC_INIT; 253 254 sc->sc_freq = 20; /* XXXX Assume 20 MHz. */ 255 256 #if SPC_USE_SYNCHRONOUS 257 /* 258 * These are the bounds of the sync period, based on the frequency of 259 * the chip's clock input and the size and offset of the sync period 260 * register. 261 * 262 * For a 20MHz clock, this gives us 25, or 100nS, or 10MB/s, as a 263 * maximum transfer rate, and 112.5, or 450nS, or 2.22MB/s, as a 264 * minimum transfer rate. 265 */ 266 sc->sc_minsync = (2 * 250) / sc->sc_freq; 267 sc->sc_maxsync = (9 * 250) / sc->sc_freq; 268 #endif 269 270 spc_init(sc); /* Init chip and driver */ 271 272 /* 273 * Fill in the adapter. 274 */ 275 sc->sc_adapter.adapt_dev = &sc->sc_dev; 276 sc->sc_adapter.adapt_nchannels = 1; 277 sc->sc_adapter.adapt_openings = 7; 278 sc->sc_adapter.adapt_max_periph = 1; 279 sc->sc_adapter.adapt_minphys = minphys; 280 sc->sc_adapter.adapt_request = spc_scsipi_request; 281 282 sc->sc_channel.chan_adapter = &sc->sc_adapter; 283 sc->sc_channel.chan_bustype = &scsi_bustype; 284 sc->sc_channel.chan_channel = 0; 285 sc->sc_channel.chan_ntargets = 8; 286 sc->sc_channel.chan_nluns = 8; 287 sc->sc_channel.chan_id = sc->sc_initiator; 288 289 /* 290 * ask the adapter what subunits are present 291 */ 292 config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 293 } 294 295 /* 296 * Initialize MB89352 chip itself 297 * The following conditions should hold: 298 * spc_isa_probe should have succeeded, i.e. the iobase address in spc_softc 299 * must be valid. 300 */ 301 void 302 spc_reset(sc) 303 struct spc_softc *sc; 304 { 305 bus_space_tag_t iot = sc->sc_iot; 306 bus_space_handle_t ioh = sc->sc_ioh; 307 308 SPC_TRACE(("spc_reset ")); 309 /* 310 * Disable interrupts then reset the FUJITSU chip. 311 */ 312 bus_space_write_1(iot, ioh, SCTL, SCTL_DISABLE | SCTL_CTRLRST); 313 bus_space_write_1(iot, ioh, SCMD, 0); 314 bus_space_write_1(iot, ioh, TMOD, 0); 315 bus_space_write_1(iot, ioh, PCTL, 0); 316 bus_space_write_1(iot, ioh, TEMP, 0); 317 bus_space_write_1(iot, ioh, TCH, 0); 318 bus_space_write_1(iot, ioh, TCM, 0); 319 bus_space_write_1(iot, ioh, TCL, 0); 320 bus_space_write_1(iot, ioh, INTS, 0); 321 bus_space_write_1(iot, ioh, SCTL, 322 SCTL_DISABLE | SCTL_ABRT_ENAB | SCTL_PARITY_ENAB | SCTL_RESEL_ENAB); 323 bus_space_write_1(iot, ioh, BDID, sc->sc_initiator); 324 delay(400); 325 bus_space_write_1(iot, ioh, SCTL, 326 bus_space_read_1(iot, ioh, SCTL) & ~SCTL_DISABLE); 327 } 328 329 330 /* 331 * Pull the SCSI RST line for 500us. 332 */ 333 void 334 spc_scsi_reset(sc) 335 struct spc_softc *sc; 336 { 337 bus_space_tag_t iot = sc->sc_iot; 338 bus_space_handle_t ioh = sc->sc_ioh; 339 340 SPC_TRACE(("spc_scsi_reset ")); 341 bus_space_write_1(iot, ioh, SCMD, 342 bus_space_read_1(iot, ioh, SCMD) | SCMD_RST); 343 delay(500); 344 bus_space_write_1(iot, ioh, SCMD, 345 bus_space_read_1(iot, ioh, SCMD) & ~SCMD_RST); 346 delay(50); 347 } 348 349 /* 350 * Initialize spc SCSI driver. 351 */ 352 void 353 spc_init(sc) 354 struct spc_softc *sc; 355 { 356 struct spc_acb *acb; 357 int r; 358 359 SPC_TRACE(("spc_init ")); 360 spc_reset(sc); 361 spc_scsi_reset(sc); 362 spc_reset(sc); 363 364 if (sc->sc_state == SPC_INIT) { 365 /* First time through; initialize. */ 366 TAILQ_INIT(&sc->ready_list); 367 TAILQ_INIT(&sc->nexus_list); 368 TAILQ_INIT(&sc->free_list); 369 sc->sc_nexus = NULL; 370 acb = sc->sc_acb; 371 memset(acb, 0, sizeof(sc->sc_acb)); 372 for (r = 0; r < sizeof(sc->sc_acb) / sizeof(*acb); r++) { 373 TAILQ_INSERT_TAIL(&sc->free_list, acb, chain); 374 acb++; 375 } 376 memset(&sc->sc_tinfo, 0, sizeof(sc->sc_tinfo)); 377 } else { 378 /* Cancel any active commands. */ 379 sc->sc_state = SPC_CLEANING; 380 if ((acb = sc->sc_nexus) != NULL) { 381 acb->xs->error = XS_DRIVER_STUFFUP; 382 callout_stop(&acb->xs->xs_callout); 383 spc_done(sc, acb); 384 } 385 while ((acb = TAILQ_FIRST(&sc->nexus_list)) != NULL) { 386 acb->xs->error = XS_DRIVER_STUFFUP; 387 callout_stop(&acb->xs->xs_callout); 388 spc_done(sc, acb); 389 } 390 } 391 392 sc->sc_prevphase = PH_INVALID; 393 for (r = 0; r < 8; r++) { 394 struct spc_tinfo *ti = &sc->sc_tinfo[r]; 395 396 ti->flags = 0; 397 #if SPC_USE_SYNCHRONOUS 398 ti->flags |= DO_SYNC; 399 ti->period = sc->sc_minsync; 400 ti->offset = SPC_SYNC_REQ_ACK_OFS; 401 #else 402 ti->period = ti->offset = 0; 403 #endif 404 #if SPC_USE_WIDE 405 ti->flags |= DO_WIDE; 406 ti->width = SPC_MAX_WIDTH; 407 #else 408 ti->width = 0; 409 #endif 410 } 411 412 sc->sc_state = SPC_IDLE; 413 bus_space_write_1(sc->sc_iot, sc->sc_ioh, SCTL, 414 bus_space_read_1(sc->sc_iot, sc->sc_ioh, SCTL) | SCTL_INTR_ENAB); 415 } 416 417 void 418 spc_free_acb(sc, acb, flags) 419 struct spc_softc *sc; 420 struct spc_acb *acb; 421 int flags; 422 { 423 int s; 424 425 SPC_TRACE(("spc_free_acb ")); 426 s = splbio(); 427 428 acb->flags = 0; 429 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 430 splx(s); 431 } 432 433 struct spc_acb * 434 spc_get_acb(sc) 435 struct spc_softc *sc; 436 { 437 struct spc_acb *acb; 438 int s; 439 440 SPC_TRACE(("spc_get_acb ")); 441 s = splbio(); 442 acb = TAILQ_FIRST(&sc->free_list); 443 if (acb != NULL) { 444 TAILQ_REMOVE(&sc->free_list, acb, chain); 445 acb->flags |= ACB_ALLOC; 446 } 447 splx(s); 448 return acb; 449 } 450 451 /* 452 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 453 */ 454 455 /* 456 * Expected sequence: 457 * 1) Command inserted into ready list 458 * 2) Command selected for execution 459 * 3) Command won arbitration and has selected target device 460 * 4) Send message out (identify message, eventually also sync.negotiations) 461 * 5) Send command 462 * 5a) Receive disconnect message, disconnect. 463 * 5b) Reselected by target 464 * 5c) Receive identify message from target. 465 * 6) Send or receive data 466 * 7) Receive status 467 * 8) Receive message (command complete etc.) 468 */ 469 470 /* 471 * Start a SCSI-command 472 * This function is called by the higher level SCSI-driver to queue/run 473 * SCSI-commands. 474 */ 475 void 476 spc_scsipi_request(chan, req, arg) 477 struct scsipi_channel *chan; 478 scsipi_adapter_req_t req; 479 void *arg; 480 { 481 struct scsipi_xfer *xs; 482 struct scsipi_periph *periph; 483 struct spc_softc *sc = (void *)chan->chan_adapter->adapt_dev; 484 struct spc_acb *acb; 485 int s, flags; 486 487 switch (req) { 488 case ADAPTER_REQ_RUN_XFER: 489 xs = arg; 490 periph = xs->xs_periph; 491 SPC_TRACE(("spc_scsipi_request ")); 492 SPC_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 493 periph->periph_target)); 494 495 flags = xs->xs_control; 496 acb = spc_get_acb(sc); 497 #ifdef DIAGNOSTIC 498 /* 499 * This should nerver happen as we track the resources 500 * in the mid-layer. 501 */ 502 if (acb == NULL) { 503 scsipi_printaddr(periph); 504 printf("unable to allocate acb\n"); 505 panic("spc_scsipi_request"); 506 } 507 #endif 508 509 /* Initialize acb */ 510 acb->xs = xs; 511 acb->timeout = xs->timeout; 512 513 if (xs->xs_control & XS_CTL_RESET) { 514 acb->flags |= ACB_RESET; 515 acb->scsipi_cmd_length = 0; 516 acb->data_length = 0; 517 } else { 518 memcpy(&acb->scsipi_cmd, xs->cmd, xs->cmdlen); 519 acb->scsipi_cmd_length = xs->cmdlen; 520 acb->data_addr = xs->data; 521 acb->data_length = xs->datalen; 522 } 523 acb->target_stat = 0; 524 525 s = splbio(); 526 527 TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain); 528 /* 529 * Start scheduling unless a queue process is in progress. 530 */ 531 if (sc->sc_state == SPC_IDLE) 532 spc_sched(sc); 533 /* 534 * After successful sending, check if we should return just now. 535 * If so, return SUCCESSFULLY_QUEUED. 536 */ 537 538 splx(s); 539 540 if ((flags & XS_CTL_POLL) == 0) 541 return; 542 543 /* Not allowed to use interrupts, use polling instead */ 544 s = splbio(); 545 if (spc_poll(sc, xs, acb->timeout)) { 546 spc_timeout(acb); 547 if (spc_poll(sc, xs, acb->timeout)) 548 spc_timeout(acb); 549 } 550 splx(s); 551 return; 552 case ADAPTER_REQ_GROW_RESOURCES: 553 /* XXX Not supported. */ 554 return; 555 case ADAPTER_REQ_SET_XFER_MODE: 556 { 557 /* 558 * We don't support Sync, Wide, or Tagged Command Queuing. 559 * Just callback now, to report this. 560 */ 561 struct scsipi_xfer_mode *xm = arg; 562 563 xm->xm_mode = 0; 564 xm->xm_period = 0; 565 xm->xm_offset = 0; 566 scsipi_async_event(chan, ASYNC_EVENT_XFER_MODE, xm); 567 return; 568 } 569 } 570 } 571 572 /* 573 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 574 */ 575 int 576 spc_poll(sc, xs, count) 577 struct spc_softc *sc; 578 struct scsipi_xfer *xs; 579 int count; 580 { 581 bus_space_tag_t iot = sc->sc_iot; 582 bus_space_handle_t ioh = sc->sc_ioh; 583 584 SPC_TRACE(("spc_poll ")); 585 while (count) { 586 /* 587 * If we had interrupts enabled, would we 588 * have got an interrupt? 589 */ 590 if (bus_space_read_1(iot, ioh, INTS) != 0) 591 spc_intr(sc); 592 if ((xs->xs_status & XS_STS_DONE) != 0) 593 return 0; 594 delay(1000); 595 count--; 596 } 597 return 1; 598 } 599 600 /* 601 * LOW LEVEL SCSI UTILITIES 602 */ 603 604 integrate void 605 spc_sched_msgout(sc, m) 606 struct spc_softc *sc; 607 u_char m; 608 { 609 bus_space_tag_t iot = sc->sc_iot; 610 bus_space_handle_t ioh = sc->sc_ioh; 611 612 SPC_TRACE(("spc_sched_msgout ")); 613 if (sc->sc_msgpriq == 0) 614 bus_space_write_1(iot, ioh, SCMD, SCMD_SET_ATN); 615 sc->sc_msgpriq |= m; 616 } 617 618 /* 619 * Set synchronous transfer offset and period. 620 */ 621 integrate void 622 spc_setsync(sc, ti) 623 struct spc_softc *sc; 624 struct spc_tinfo *ti; 625 { 626 #if SPC_USE_SYNCHRONOUS 627 bus_space_tag_t iot = sc->sc_iot; 628 bus_space_handle_t ioh = sc->sc_ioh; 629 630 SPC_TRACE(("spc_setsync ")); 631 if (ti->offset != 0) 632 bus_space_write_1(iot, ioh, TMOD, 633 ((ti->period * sc->sc_freq) / 250 - 2) << 4 | ti->offset); 634 else 635 bus_space_write_1(iot, ioh, TMOD, 0); 636 #endif 637 } 638 639 /* 640 * Start a selection. This is used by spc_sched() to select an idle target. 641 */ 642 void 643 spc_select(sc, acb) 644 struct spc_softc *sc; 645 struct spc_acb *acb; 646 { 647 struct scsipi_periph *periph = acb->xs->xs_periph; 648 int target = periph->periph_target; 649 struct spc_tinfo *ti = &sc->sc_tinfo[target]; 650 bus_space_tag_t iot = sc->sc_iot; 651 bus_space_handle_t ioh = sc->sc_ioh; 652 653 SPC_TRACE(("spc_select ")); 654 spc_setsync(sc, ti); 655 656 #if 0 657 bus_space_write_1(iot, ioh, SCMD, SCMD_SET_ATN); 658 #endif 659 660 bus_space_write_1(iot, ioh, PCTL, 0); 661 bus_space_write_1(iot, ioh, TEMP, 662 (1 << sc->sc_initiator) | (1 << target)); 663 /* 664 * Setup BSY timeout (selection timeout). 665 * 250ms according to the SCSI specification. 666 * T = (X * 256 + 15) * Tclf * 2 (Tclf = 200ns on x68k) 667 * To setup 256ms timeout, 668 * 128000ns/200ns = X * 256 + 15 669 * 640 - 15 = X * 256 670 * X = 625 / 256 671 * X = 2 + 113 / 256 672 * ==> tch = 2, tcm = 113 (correct?) 673 */ 674 /* Time to the information transfer phase start. */ 675 /* XXX These values should be calculated from sc_freq */ 676 bus_space_write_1(iot, ioh, TCH, 2); 677 bus_space_write_1(iot, ioh, TCM, 113); 678 bus_space_write_1(iot, ioh, TCL, 3); 679 bus_space_write_1(iot, ioh, SCMD, SCMD_SELECT); 680 681 sc->sc_state = SPC_SELECTING; 682 } 683 684 int 685 spc_reselect(sc, message) 686 struct spc_softc *sc; 687 int message; 688 { 689 u_char selid, target, lun; 690 struct spc_acb *acb; 691 struct scsipi_periph *periph; 692 struct spc_tinfo *ti; 693 694 SPC_TRACE(("spc_reselect ")); 695 /* 696 * The SCSI chip made a snapshot of the data bus while the reselection 697 * was being negotiated. This enables us to determine which target did 698 * the reselect. 699 */ 700 selid = sc->sc_selid & ~(1 << sc->sc_initiator); 701 if (selid & (selid - 1)) { 702 printf("%s: reselect with invalid selid %02x; " 703 "sending DEVICE RESET\n", sc->sc_dev.dv_xname, selid); 704 SPC_BREAK(); 705 goto reset; 706 } 707 708 /* 709 * Search wait queue for disconnected cmd 710 * The list should be short, so I haven't bothered with 711 * any more sophisticated structures than a simple 712 * singly linked list. 713 */ 714 target = ffs(selid) - 1; 715 lun = message & 0x07; 716 TAILQ_FOREACH(acb, &sc->nexus_list, chain) { 717 periph = acb->xs->xs_periph; 718 if (periph->periph_target == target && 719 periph->periph_lun == lun) 720 break; 721 } 722 if (acb == NULL) { 723 printf("%s: reselect from target %d lun %d with no nexus; " 724 "sending ABORT\n", sc->sc_dev.dv_xname, target, lun); 725 SPC_BREAK(); 726 goto abort; 727 } 728 729 /* Make this nexus active again. */ 730 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 731 sc->sc_state = SPC_CONNECTED; 732 sc->sc_nexus = acb; 733 ti = &sc->sc_tinfo[target]; 734 ti->lubusy |= (1 << lun); 735 spc_setsync(sc, ti); 736 737 if (acb->flags & ACB_RESET) 738 spc_sched_msgout(sc, SEND_DEV_RESET); 739 else if (acb->flags & ACB_ABORT) 740 spc_sched_msgout(sc, SEND_ABORT); 741 742 /* Do an implicit RESTORE POINTERS. */ 743 sc->sc_dp = acb->data_addr; 744 sc->sc_dleft = acb->data_length; 745 sc->sc_cp = (u_char *)&acb->scsipi_cmd; 746 sc->sc_cleft = acb->scsipi_cmd_length; 747 748 return (0); 749 750 reset: 751 spc_sched_msgout(sc, SEND_DEV_RESET); 752 return (1); 753 754 abort: 755 spc_sched_msgout(sc, SEND_ABORT); 756 return (1); 757 } 758 759 /* 760 * Schedule a SCSI operation. This has now been pulled out of the interrupt 761 * handler so that we may call it from spc_scsi_cmd and spc_done. This may 762 * save us an unnecessary interrupt just to get things going. Should only be 763 * called when state == SPC_IDLE and at bio pl. 764 */ 765 void 766 spc_sched(sc) 767 struct spc_softc *sc; 768 { 769 struct spc_acb *acb; 770 struct scsipi_periph *periph; 771 struct spc_tinfo *ti; 772 773 /* missing the hw, just return and wait for our hw */ 774 if (sc->sc_flags & SPC_INACTIVE) 775 return; 776 SPC_TRACE(("spc_sched ")); 777 /* 778 * Find first acb in ready queue that is for a target/lunit pair that 779 * is not busy. 780 */ 781 TAILQ_FOREACH(acb, &sc->ready_list, chain) { 782 periph = acb->xs->xs_periph; 783 ti = &sc->sc_tinfo[periph->periph_target]; 784 if ((ti->lubusy & (1 << periph->periph_lun)) == 0) { 785 SPC_MISC(("selecting %d:%d ", 786 periph->periph_target, periph->periph_lun)); 787 TAILQ_REMOVE(&sc->ready_list, acb, chain); 788 sc->sc_nexus = acb; 789 spc_select(sc, acb); 790 return; 791 } else 792 SPC_MISC(("%d:%d busy\n", 793 periph->periph_target, periph->periph_lun)); 794 } 795 SPC_MISC(("idle ")); 796 /* Nothing to start; just enable reselections and wait. */ 797 } 798 799 /* 800 * POST PROCESSING OF SCSI_CMD (usually current) 801 */ 802 void 803 spc_done(sc, acb) 804 struct spc_softc *sc; 805 struct spc_acb *acb; 806 { 807 struct scsipi_xfer *xs = acb->xs; 808 struct scsipi_periph *periph = xs->xs_periph; 809 struct spc_tinfo *ti = &sc->sc_tinfo[periph->periph_target]; 810 811 SPC_TRACE(("spc_done ")); 812 813 if (xs->error == XS_NOERROR) { 814 if (acb->flags & ACB_ABORT) { 815 xs->error = XS_DRIVER_STUFFUP; 816 } else { 817 switch (acb->target_stat) { 818 case SCSI_CHECK: 819 /* First, save the return values */ 820 xs->resid = acb->data_length; 821 /* FALLTHROUGH */ 822 case SCSI_BUSY: 823 xs->status = acb->target_stat; 824 xs->error = XS_BUSY; 825 break; 826 case SCSI_OK: 827 xs->resid = acb->data_length; 828 break; 829 default: 830 xs->error = XS_DRIVER_STUFFUP; 831 #if SPC_DEBUG 832 printf("%s: spc_done: bad stat 0x%x\n", 833 sc->sc_dev.dv_xname, acb->target_stat); 834 #endif 835 break; 836 } 837 } 838 } 839 840 #if SPC_DEBUG 841 if ((spc_debug & SPC_SHOWMISC) != 0) { 842 if (xs->resid != 0) 843 printf("resid=%d ", xs->resid); 844 else 845 printf("error=%d\n", xs->error); 846 } 847 #endif 848 849 /* 850 * Remove the ACB from whatever queue it happens to be on. 851 */ 852 if (acb->flags & ACB_NEXUS) 853 ti->lubusy &= ~(1 << periph->periph_lun); 854 if (acb == sc->sc_nexus) { 855 sc->sc_nexus = NULL; 856 sc->sc_state = SPC_IDLE; 857 spc_sched(sc); 858 } else 859 spc_dequeue(sc, acb); 860 861 spc_free_acb(sc, acb, xs->xs_control); 862 ti->cmds++; 863 scsipi_done(xs); 864 } 865 866 void 867 spc_dequeue(sc, acb) 868 struct spc_softc *sc; 869 struct spc_acb *acb; 870 { 871 872 SPC_TRACE(("spc_dequeue ")); 873 if (acb->flags & ACB_NEXUS) 874 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 875 else 876 TAILQ_REMOVE(&sc->ready_list, acb, chain); 877 } 878 879 /* 880 * INTERRUPT/PROTOCOL ENGINE 881 */ 882 883 /* 884 * Precondition: 885 * The SCSI bus is already in the MSGI phase and there is a message byte 886 * on the bus, along with an asserted REQ signal. 887 */ 888 void 889 spc_msgin(sc) 890 struct spc_softc *sc; 891 { 892 bus_space_tag_t iot = sc->sc_iot; 893 bus_space_handle_t ioh = sc->sc_ioh; 894 int n; 895 u_int8_t msg; 896 897 SPC_TRACE(("spc_msgin ")); 898 899 if (sc->sc_prevphase == PH_MSGIN) { 900 /* This is a continuation of the previous message. */ 901 n = sc->sc_imp - sc->sc_imess; 902 goto nextbyte; 903 } 904 905 /* This is a new MESSAGE IN phase. Clean up our state. */ 906 sc->sc_flags &= ~SPC_DROP_MSGIN; 907 908 nextmsg: 909 n = 0; 910 sc->sc_imp = &sc->sc_imess[n]; 911 912 nextbyte: 913 /* 914 * Read a whole message, but don't ack the last byte. If we reject the 915 * message, we have to assert ATN during the message transfer phase 916 * itself. 917 */ 918 for (;;) { 919 #ifdef NO_MANUAL_XFER /* XXX */ 920 if (bus_space_read_1(iot, ioh, INTS) != 0) { 921 /* 922 * Target left MESSAGE IN, probably because it 923 * a) noticed our ATN signal, or 924 * b) ran out of messages. 925 */ 926 goto out; 927 } 928 #endif 929 /* If parity error, just dump everything on the floor. */ 930 if ((bus_space_read_1(iot, ioh, SERR) & 931 (SERR_SCSI_PAR|SERR_SPC_PAR)) != 0) { 932 sc->sc_flags |= SPC_DROP_MSGIN; 933 spc_sched_msgout(sc, SEND_PARITY_ERROR); 934 } 935 936 #ifdef NO_MANUAL_XFER /* XXX */ 937 /* send TRANSFER command. */ 938 bus_space_write_1(iot, ioh, TCH, 0); 939 bus_space_write_1(iot, ioh, TCM, 0); 940 bus_space_write_1(iot, ioh, TCL, 1); 941 bus_space_write_1(iot, ioh, PCTL, 942 sc->sc_phase | PCTL_BFINT_ENAB); 943 #ifdef NEED_DREQ_ON_HARDWARE_XFER 944 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); 945 #else 946 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR | SCMD_PROG_XFR); 947 #endif 948 for (;;) { 949 if ((bus_space_read_1(iot, ioh, SSTS) & 950 SSTS_DREG_EMPTY) == 0) 951 break; 952 if (bus_space_read_1(iot, ioh, INTS) != 0) 953 goto out; 954 } 955 msg = bus_space_read_1(iot, ioh, DREG); 956 #else 957 if ((bus_space_read_1(iot, ioh, PSNS) & PSNS_ATN) != 0) 958 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ATN); 959 960 while ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) == 0) { 961 /* XXX needs timeout */ 962 if ((bus_space_read_1(iot, ioh, PSNS) & PH_MASK) 963 != PH_MSGIN) 964 /* 965 * Target left MESSAGE IN, probably because it 966 * a) noticed our ATN signal, or 967 * b) ran out of messages. 968 */ 969 goto out; 970 } 971 972 bus_space_write_1(iot, ioh, PCTL, PH_MSGIN); 973 msg = bus_space_read_1(iot, ioh, TEMP); 974 #endif 975 976 /* Gather incoming message bytes if needed. */ 977 if ((sc->sc_flags & SPC_DROP_MSGIN) == 0) { 978 if (n >= SPC_MAX_MSG_LEN) { 979 sc->sc_flags |= SPC_DROP_MSGIN; 980 spc_sched_msgout(sc, SEND_REJECT); 981 } else { 982 *sc->sc_imp++ = msg; 983 n++; 984 /* 985 * This testing is suboptimal, but most 986 * messages will be of the one byte variety, so 987 * it should not affect performance 988 * significantly. 989 */ 990 if (n == 1 && MSG_IS1BYTE(sc->sc_imess[0])) 991 break; 992 if (n == 2 && MSG_IS2BYTE(sc->sc_imess[0])) 993 break; 994 if (n >= 3 && MSG_ISEXTENDED(sc->sc_imess[0]) && 995 n == sc->sc_imess[1] + 2) 996 break; 997 } 998 } 999 /* 1000 * If we reach this spot we're either: 1001 * a) in the middle of a multi-byte message, or 1002 * b) dropping bytes. 1003 */ 1004 1005 #ifndef NO_MANUAL_XFER /* XXX */ 1006 /* Ack the last byte read. */ 1007 bus_space_write_1(iot, ioh, SCMD, SCMD_SET_ACK); 1008 while ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) != 0) 1009 continue; /* XXX needs timeout */ 1010 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ACK); 1011 #endif 1012 } 1013 1014 SPC_MISC(("n=%d imess=0x%02x ", n, sc->sc_imess[0])); 1015 1016 /* We now have a complete message. Parse it. */ 1017 switch (sc->sc_state) { 1018 struct spc_acb *acb; 1019 struct scsipi_periph *periph; 1020 struct spc_tinfo *ti; 1021 1022 case SPC_CONNECTED: 1023 SPC_ASSERT(sc->sc_nexus != NULL); 1024 acb = sc->sc_nexus; 1025 ti = &sc->sc_tinfo[acb->xs->xs_periph->periph_target]; 1026 1027 switch (sc->sc_imess[0]) { 1028 case MSG_CMDCOMPLETE: 1029 if (sc->sc_dleft < 0) { 1030 periph = acb->xs->xs_periph; 1031 printf("%s: %d extra bytes from %d:%d\n", 1032 sc->sc_dev.dv_xname, -sc->sc_dleft, 1033 periph->periph_target, periph->periph_lun); 1034 sc->sc_dleft = 0; 1035 } 1036 acb->xs->resid = acb->data_length = sc->sc_dleft; 1037 sc->sc_state = SPC_CMDCOMPLETE; 1038 break; 1039 1040 case MSG_PARITY_ERROR: 1041 /* Resend the last message. */ 1042 spc_sched_msgout(sc, sc->sc_lastmsg); 1043 break; 1044 1045 case MSG_MESSAGE_REJECT: 1046 SPC_MISC(("message rejected %02x ", sc->sc_lastmsg)); 1047 switch (sc->sc_lastmsg) { 1048 #if SPC_USE_SYNCHRONOUS + SPC_USE_WIDE 1049 case SEND_IDENTIFY: 1050 ti->flags &= ~(DO_SYNC | DO_WIDE); 1051 ti->period = ti->offset = 0; 1052 spc_setsync(sc, ti); 1053 ti->width = 0; 1054 break; 1055 #endif 1056 #if SPC_USE_SYNCHRONOUS 1057 case SEND_SDTR: 1058 ti->flags &= ~DO_SYNC; 1059 ti->period = ti->offset = 0; 1060 spc_setsync(sc, ti); 1061 break; 1062 #endif 1063 #if SPC_USE_WIDE 1064 case SEND_WDTR: 1065 ti->flags &= ~DO_WIDE; 1066 ti->width = 0; 1067 break; 1068 #endif 1069 case SEND_INIT_DET_ERR: 1070 spc_sched_msgout(sc, SEND_ABORT); 1071 break; 1072 } 1073 break; 1074 1075 case MSG_NOOP: 1076 break; 1077 1078 case MSG_DISCONNECT: 1079 ti->dconns++; 1080 sc->sc_state = SPC_DISCONNECT; 1081 break; 1082 1083 case MSG_SAVEDATAPOINTER: 1084 acb->data_addr = sc->sc_dp; 1085 acb->data_length = sc->sc_dleft; 1086 break; 1087 1088 case MSG_RESTOREPOINTERS: 1089 sc->sc_dp = acb->data_addr; 1090 sc->sc_dleft = acb->data_length; 1091 sc->sc_cp = (u_char *)&acb->scsipi_cmd; 1092 sc->sc_cleft = acb->scsipi_cmd_length; 1093 break; 1094 1095 case MSG_EXTENDED: 1096 switch (sc->sc_imess[2]) { 1097 #if SPC_USE_SYNCHRONOUS 1098 case MSG_EXT_SDTR: 1099 if (sc->sc_imess[1] != 3) 1100 goto reject; 1101 ti->period = sc->sc_imess[3]; 1102 ti->offset = sc->sc_imess[4]; 1103 ti->flags &= ~DO_SYNC; 1104 if (ti->offset == 0) { 1105 } else if (ti->period < sc->sc_minsync || 1106 ti->period > sc->sc_maxsync || 1107 ti->offset > 8) { 1108 ti->period = ti->offset = 0; 1109 spc_sched_msgout(sc, SEND_SDTR); 1110 } else { 1111 scsipi_printaddr(acb->xs->xs_periph); 1112 printf("sync, offset %d, " 1113 "period %dnsec\n", 1114 ti->offset, ti->period * 4); 1115 } 1116 spc_setsync(sc, ti); 1117 break; 1118 #endif 1119 1120 #if SPC_USE_WIDE 1121 case MSG_EXT_WDTR: 1122 if (sc->sc_imess[1] != 2) 1123 goto reject; 1124 ti->width = sc->sc_imess[3]; 1125 ti->flags &= ~DO_WIDE; 1126 if (ti->width == 0) { 1127 } else if (ti->width > SPC_MAX_WIDTH) { 1128 ti->width = 0; 1129 spc_sched_msgout(sc, SEND_WDTR); 1130 } else { 1131 scsipi_printaddr(acb->xs->xs_periph); 1132 printf("wide, width %d\n", 1133 1 << (3 + ti->width)); 1134 } 1135 break; 1136 #endif 1137 1138 default: 1139 printf("%s: unrecognized MESSAGE EXTENDED; " 1140 "sending REJECT\n", sc->sc_dev.dv_xname); 1141 SPC_BREAK(); 1142 goto reject; 1143 } 1144 break; 1145 1146 default: 1147 printf("%s: unrecognized MESSAGE; sending REJECT\n", 1148 sc->sc_dev.dv_xname); 1149 SPC_BREAK(); 1150 reject: 1151 spc_sched_msgout(sc, SEND_REJECT); 1152 break; 1153 } 1154 break; 1155 1156 case SPC_RESELECTED: 1157 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1158 printf("%s: reselect without IDENTIFY; " 1159 "sending DEVICE RESET\n", sc->sc_dev.dv_xname); 1160 SPC_BREAK(); 1161 goto reset; 1162 } 1163 1164 (void) spc_reselect(sc, sc->sc_imess[0]); 1165 break; 1166 1167 default: 1168 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n", 1169 sc->sc_dev.dv_xname); 1170 SPC_BREAK(); 1171 reset: 1172 spc_sched_msgout(sc, SEND_DEV_RESET); 1173 break; 1174 1175 #ifdef notdef 1176 abort: 1177 spc_sched_msgout(sc, SEND_ABORT); 1178 break; 1179 #endif 1180 } 1181 1182 #ifndef NO_MANUAL_XFER /* XXX */ 1183 /* Ack the last message byte. */ 1184 bus_space_write_1(iot, ioh, SCMD, SCMD_SET_ACK); 1185 while ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) != 0) 1186 continue; /* XXX needs timeout */ 1187 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ACK); 1188 #endif 1189 1190 /* Go get the next message, if any. */ 1191 goto nextmsg; 1192 1193 out: 1194 #ifdef NO_MANUAL_XFER /* XXX */ 1195 /* Ack the last message byte. */ 1196 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ACK); 1197 #endif 1198 SPC_MISC(("n=%d imess=0x%02x ", n, sc->sc_imess[0])); 1199 } 1200 1201 /* 1202 * Send the highest priority, scheduled message. 1203 */ 1204 void 1205 spc_msgout(sc) 1206 struct spc_softc *sc; 1207 { 1208 bus_space_tag_t iot = sc->sc_iot; 1209 bus_space_handle_t ioh = sc->sc_ioh; 1210 #if SPC_USE_SYNCHRONOUS 1211 struct spc_tinfo *ti; 1212 #endif 1213 int n; 1214 1215 SPC_TRACE(("spc_msgout ")); 1216 1217 if (sc->sc_prevphase == PH_MSGOUT) { 1218 if (sc->sc_omp == sc->sc_omess) { 1219 /* 1220 * This is a retransmission. 1221 * 1222 * We get here if the target stayed in MESSAGE OUT 1223 * phase. Section 5.1.9.2 of the SCSI 2 spec indicates 1224 * that all of the previously transmitted messages must 1225 * be sent again, in the same order. Therefore, we 1226 * requeue all the previously transmitted messages, and 1227 * start again from the top. Our simple priority 1228 * scheme keeps the messages in the right order. 1229 */ 1230 SPC_MISC(("retransmitting ")); 1231 sc->sc_msgpriq |= sc->sc_msgoutq; 1232 /* 1233 * Set ATN. If we're just sending a trivial 1-byte 1234 * message, we'll clear ATN later on anyway. 1235 */ 1236 bus_space_write_1(iot, ioh, SCMD, 1237 SCMD_SET_ATN); /* XXX? */ 1238 } else { 1239 /* This is a continuation of the previous message. */ 1240 n = sc->sc_omp - sc->sc_omess; 1241 goto nextbyte; 1242 } 1243 } 1244 1245 /* No messages transmitted so far. */ 1246 sc->sc_msgoutq = 0; 1247 sc->sc_lastmsg = 0; 1248 1249 nextmsg: 1250 /* Pick up highest priority message. */ 1251 sc->sc_currmsg = sc->sc_msgpriq & -sc->sc_msgpriq; 1252 sc->sc_msgpriq &= ~sc->sc_currmsg; 1253 sc->sc_msgoutq |= sc->sc_currmsg; 1254 1255 /* Build the outgoing message data. */ 1256 switch (sc->sc_currmsg) { 1257 case SEND_IDENTIFY: 1258 SPC_ASSERT(sc->sc_nexus != NULL); 1259 sc->sc_omess[0] = 1260 MSG_IDENTIFY(sc->sc_nexus->xs->xs_periph->periph_lun, 1); 1261 n = 1; 1262 break; 1263 1264 #if SPC_USE_SYNCHRONOUS 1265 case SEND_SDTR: 1266 SPC_ASSERT(sc->sc_nexus != NULL); 1267 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target]; 1268 sc->sc_omess[4] = MSG_EXTENDED; 1269 sc->sc_omess[3] = MSG_EXT_SDTR_LEN; 1270 sc->sc_omess[2] = MSG_EXT_SDTR; 1271 sc->sc_omess[1] = ti->period >> 2; 1272 sc->sc_omess[0] = ti->offset; 1273 n = 5; 1274 break; 1275 #endif 1276 1277 #if SPC_USE_WIDE 1278 case SEND_WDTR: 1279 SPC_ASSERT(sc->sc_nexus != NULL); 1280 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target]; 1281 sc->sc_omess[3] = MSG_EXTENDED; 1282 sc->sc_omess[2] = MSG_EXT_WDTR_LEN; 1283 sc->sc_omess[1] = MSG_EXT_WDTR; 1284 sc->sc_omess[0] = ti->width; 1285 n = 4; 1286 break; 1287 #endif 1288 1289 case SEND_DEV_RESET: 1290 sc->sc_flags |= SPC_ABORTING; 1291 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1292 n = 1; 1293 break; 1294 1295 case SEND_REJECT: 1296 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1297 n = 1; 1298 break; 1299 1300 case SEND_PARITY_ERROR: 1301 sc->sc_omess[0] = MSG_PARITY_ERROR; 1302 n = 1; 1303 break; 1304 1305 case SEND_INIT_DET_ERR: 1306 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1307 n = 1; 1308 break; 1309 1310 case SEND_ABORT: 1311 sc->sc_flags |= SPC_ABORTING; 1312 sc->sc_omess[0] = MSG_ABORT; 1313 n = 1; 1314 break; 1315 1316 default: 1317 printf("%s: unexpected MESSAGE OUT; sending NOOP\n", 1318 sc->sc_dev.dv_xname); 1319 SPC_BREAK(); 1320 sc->sc_omess[0] = MSG_NOOP; 1321 n = 1; 1322 break; 1323 } 1324 sc->sc_omp = &sc->sc_omess[n]; 1325 1326 nextbyte: 1327 /* Send message bytes. */ 1328 /* send TRANSFER command. */ 1329 bus_space_write_1(iot, ioh, TCH, n >> 16); 1330 bus_space_write_1(iot, ioh, TCM, n >> 8); 1331 bus_space_write_1(iot, ioh, TCL, n); 1332 bus_space_write_1(iot, ioh, PCTL, sc->sc_phase | PCTL_BFINT_ENAB); 1333 #ifdef NEED_DREQ_ON_HARDWARE_XFER 1334 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); /* XXX */ 1335 #else 1336 bus_space_write_1(iot, ioh, SCMD, 1337 SCMD_XFR | SCMD_PROG_XFR); 1338 #endif 1339 for (;;) { 1340 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_BUSY) != 0) 1341 break; 1342 if (bus_space_read_1(iot, ioh, INTS) != 0) 1343 goto out; 1344 } 1345 for (;;) { 1346 #if 0 1347 for (;;) { 1348 if ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) != 0) 1349 break; 1350 /* Wait for REQINIT. XXX Need timeout. */ 1351 } 1352 #endif 1353 if (bus_space_read_1(iot, ioh, INTS) != 0) { 1354 /* 1355 * Target left MESSAGE OUT, possibly to reject 1356 * our message. 1357 * 1358 * If this is the last message being sent, then we 1359 * deassert ATN, since either the target is going to 1360 * ignore this message, or it's going to ask for a 1361 * retransmission via MESSAGE PARITY ERROR (in which 1362 * case we reassert ATN anyway). 1363 */ 1364 #if 0 1365 if (sc->sc_msgpriq == 0) 1366 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ATN); 1367 #endif 1368 goto out; 1369 } 1370 1371 #if 0 1372 /* Clear ATN before last byte if this is the last message. */ 1373 if (n == 1 && sc->sc_msgpriq == 0) 1374 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ATN); 1375 #endif 1376 1377 while ((bus_space_read_1(iot, ioh, SSTS) & SSTS_DREG_FULL) != 0) 1378 ; 1379 /* Send message byte. */ 1380 bus_space_write_1(iot, ioh, DREG, *--sc->sc_omp); 1381 --n; 1382 /* Keep track of the last message we've sent any bytes of. */ 1383 sc->sc_lastmsg = sc->sc_currmsg; 1384 #if 0 1385 /* Wait for ACK to be negated. XXX Need timeout. */ 1386 while ((bus_space_read_1(iot, ioh, PSNS) & ACKI) != 0) 1387 ; 1388 #endif 1389 1390 if (n == 0) 1391 break; 1392 } 1393 1394 /* We get here only if the entire message has been transmitted. */ 1395 if (sc->sc_msgpriq != 0) { 1396 /* There are more outgoing messages. */ 1397 goto nextmsg; 1398 } 1399 1400 /* 1401 * The last message has been transmitted. We need to remember the last 1402 * message transmitted (in case the target switches to MESSAGE IN phase 1403 * and sends a MESSAGE REJECT), and the list of messages transmitted 1404 * this time around (in case the target stays in MESSAGE OUT phase to 1405 * request a retransmit). 1406 */ 1407 1408 out: 1409 /* Disable REQ/ACK protocol. */ 1410 return; 1411 } 1412 1413 /* 1414 * spc_dataout_pio: perform a data transfer using the FIFO datapath in the spc 1415 * Precondition: The SCSI bus should be in the DOUT phase, with REQ asserted 1416 * and ACK deasserted (i.e. waiting for a data byte) 1417 * 1418 * This new revision has been optimized (I tried) to make the common case fast, 1419 * and the rarer cases (as a result) somewhat more comlex 1420 */ 1421 int 1422 spc_dataout_pio(sc, p, n) 1423 struct spc_softc *sc; 1424 u_char *p; 1425 int n; 1426 { 1427 bus_space_tag_t iot = sc->sc_iot; 1428 bus_space_handle_t ioh = sc->sc_ioh; 1429 u_char intstat = 0; 1430 int out = 0; 1431 #define DOUTAMOUNT 8 /* Full FIFO */ 1432 1433 SPC_TRACE(("spc_dataout_pio ")); 1434 /* send TRANSFER command. */ 1435 bus_space_write_1(iot, ioh, TCH, n >> 16); 1436 bus_space_write_1(iot, ioh, TCM, n >> 8); 1437 bus_space_write_1(iot, ioh, TCL, n); 1438 bus_space_write_1(iot, ioh, PCTL, sc->sc_phase | PCTL_BFINT_ENAB); 1439 #ifdef NEED_DREQ_ON_HARDWARE_XFER 1440 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); /* XXX */ 1441 #else 1442 bus_space_write_1(iot, ioh, SCMD, 1443 SCMD_XFR | SCMD_PROG_XFR); /* XXX */ 1444 #endif 1445 for (;;) { 1446 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_BUSY) != 0) 1447 break; 1448 if (bus_space_read_1(iot, ioh, INTS) != 0) 1449 break; 1450 } 1451 1452 /* 1453 * I have tried to make the main loop as tight as possible. This 1454 * means that some of the code following the loop is a bit more 1455 * complex than otherwise. 1456 */ 1457 while (n > 0) { 1458 int xfer; 1459 1460 for (;;) { 1461 intstat = bus_space_read_1(iot, ioh, INTS); 1462 /* Wait till buffer is empty. */ 1463 if ((bus_space_read_1(iot, ioh, SSTS) & 1464 SSTS_DREG_EMPTY) != 0) 1465 break; 1466 /* Break on interrupt. */ 1467 if (intstat != 0) 1468 goto phasechange; 1469 } 1470 1471 xfer = min(DOUTAMOUNT, n); 1472 1473 SPC_MISC(("%d> ", xfer)); 1474 1475 n -= xfer; 1476 out += xfer; 1477 1478 bus_space_write_multi_1(iot, ioh, DREG, p, xfer); 1479 p += xfer; 1480 } 1481 1482 if (out == 0) { 1483 for (;;) { 1484 if (bus_space_read_1(iot, ioh, INTS) != 0) 1485 break; 1486 } 1487 SPC_MISC(("extra data ")); 1488 } else { 1489 /* See the bytes off chip */ 1490 for (;;) { 1491 /* Wait till buffer is empty. */ 1492 if ((bus_space_read_1(iot, ioh, SSTS) & 1493 SSTS_DREG_EMPTY) != 0) 1494 break; 1495 intstat = bus_space_read_1(iot, ioh, INTS); 1496 /* Break on interrupt. */ 1497 if (intstat != 0) 1498 goto phasechange; 1499 } 1500 } 1501 1502 phasechange: 1503 /* Stop the FIFO data path. */ 1504 1505 if (intstat != 0) { 1506 /* Some sort of phase change. */ 1507 int amount; 1508 1509 amount = (bus_space_read_1(iot, ioh, TCH) << 16) | 1510 (bus_space_read_1(iot, ioh, TCM) << 8) | 1511 bus_space_read_1(iot, ioh, TCL); 1512 if (amount > 0) { 1513 out -= amount; 1514 SPC_MISC(("+%d ", amount)); 1515 } 1516 } 1517 1518 return out; 1519 } 1520 1521 /* 1522 * spc_datain_pio: perform data transfers using the FIFO datapath in the spc 1523 * Precondition: The SCSI bus should be in the DIN phase, with REQ asserted 1524 * and ACK deasserted (i.e. at least one byte is ready). 1525 * 1526 * For now, uses a pretty dumb algorithm, hangs around until all data has been 1527 * transferred. This, is OK for fast targets, but not so smart for slow 1528 * targets which don't disconnect or for huge transfers. 1529 */ 1530 int 1531 spc_datain_pio(sc, p, n) 1532 struct spc_softc *sc; 1533 u_char *p; 1534 int n; 1535 { 1536 bus_space_tag_t iot = sc->sc_iot; 1537 bus_space_handle_t ioh = sc->sc_ioh; 1538 int in = 0; 1539 u_int8_t intstat, sstat; 1540 #define DINAMOUNT 8 /* Full FIFO */ 1541 1542 SPC_TRACE(("spc_datain_pio ")); 1543 /* send TRANSFER command. */ 1544 bus_space_write_1(iot, ioh, TCH, n >> 16); 1545 bus_space_write_1(iot, ioh, TCM, n >> 8); 1546 bus_space_write_1(iot, ioh, TCL, n); 1547 bus_space_write_1(iot, ioh, PCTL, sc->sc_phase | PCTL_BFINT_ENAB); 1548 #ifdef NEED_DREQ_ON_HARDWARE_XFER 1549 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); /* XXX */ 1550 #else 1551 bus_space_write_1(iot, ioh, SCMD, 1552 SCMD_XFR | SCMD_PROG_XFR); /* XXX */ 1553 #endif 1554 for (;;) { 1555 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_BUSY) != 0) 1556 break; 1557 if (bus_space_read_1(iot, ioh, INTS) != 0) 1558 goto phasechange; 1559 } 1560 1561 /* 1562 * We leave this loop if one or more of the following is true: 1563 * a) phase != PH_DATAIN && FIFOs are empty 1564 * b) reset has occurred or busfree is detected. 1565 */ 1566 while (n > 0) { 1567 int xfer; 1568 1569 /* Wait for fifo half full or phase mismatch */ 1570 for (;;) { 1571 /* XXX needs timeout */ 1572 intstat = bus_space_read_1(iot, ioh, INTS); 1573 sstat = bus_space_read_1(iot, ioh, SSTS); 1574 if (intstat != 0 || 1575 (sstat & SSTS_DREG_EMPTY) == 0) 1576 break; 1577 } 1578 1579 #ifdef NEED_DREQ_ON_HARDWARE_XFER 1580 if (intstat != 0) 1581 goto phasechange; 1582 #endif 1583 1584 if (sstat & SSTS_DREG_FULL) { 1585 xfer = DINAMOUNT; 1586 n -= xfer; 1587 in += xfer; 1588 bus_space_read_multi_1(iot, ioh, DREG, p, xfer); 1589 p += xfer; 1590 } 1591 while (n > 0 && 1592 (bus_space_read_1(iot, ioh, SSTS) & SSTS_DREG_EMPTY) == 0) { 1593 n--; 1594 in++; 1595 *p++ = bus_space_read_1(iot, ioh, DREG); 1596 } 1597 1598 if (intstat != 0) 1599 goto phasechange; 1600 } 1601 1602 /* 1603 * Some SCSI-devices are rude enough to transfer more data than what 1604 * was requested, e.g. 2048 bytes from a CD-ROM instead of the 1605 * requested 512. Test for progress, i.e. real transfers. If no real 1606 * transfers have been performed (n is probably already zero) and the 1607 * FIFO is not empty, waste some bytes.... 1608 */ 1609 if (in == 0) { 1610 for (;;) { 1611 /* XXX needs timeout */ 1612 if (bus_space_read_1(iot, ioh, INTS) != 0) 1613 break; 1614 } 1615 SPC_MISC(("extra data ")); 1616 } 1617 1618 phasechange: 1619 /* Stop the FIFO data path. */ 1620 1621 return in; 1622 } 1623 1624 /* 1625 * Catch an interrupt from the adaptor 1626 */ 1627 /* 1628 * This is the workhorse routine of the driver. 1629 * Deficiencies (for now): 1630 * 1) always uses programmed I/O 1631 */ 1632 int 1633 spc_intr(arg) 1634 void *arg; 1635 { 1636 struct spc_softc *sc = arg; 1637 bus_space_tag_t iot = sc->sc_iot; 1638 bus_space_handle_t ioh = sc->sc_ioh; 1639 u_char ints; 1640 struct spc_acb *acb; 1641 struct scsipi_periph *periph; 1642 struct spc_tinfo *ti; 1643 int n; 1644 1645 /* 1646 * Disable interrupt. 1647 */ 1648 bus_space_write_1(iot, ioh, SCTL, 1649 bus_space_read_1(iot, ioh, SCTL) & ~SCTL_INTR_ENAB); 1650 1651 SPC_TRACE(("spc_intr ")); 1652 1653 ints = bus_space_read_1(iot, ioh, INTS); 1654 if (ints == 0) 1655 goto out; 1656 1657 if (sc->sc_dma_done != NULL && 1658 sc->sc_state == SPC_CONNECTED && 1659 (sc->sc_flags & SPC_DOINGDMA) != 0 && 1660 (sc->sc_phase == PH_DATAOUT || sc->sc_phase == PH_DATAIN)) { 1661 (*sc->sc_dma_done)(sc); 1662 } 1663 1664 loop: 1665 /* 1666 * Loop until transfer completion. 1667 */ 1668 /* 1669 * First check for abnormal conditions, such as reset. 1670 */ 1671 ints = bus_space_read_1(iot, ioh, INTS); 1672 SPC_MISC(("ints = 0x%x ", ints)); 1673 1674 if ((ints & INTS_RST) != 0) { 1675 printf("%s: SCSI bus reset\n", sc->sc_dev.dv_xname); 1676 goto reset; 1677 } 1678 1679 /* 1680 * Check for less serious errors. 1681 */ 1682 if ((bus_space_read_1(iot, ioh, SERR) & (SERR_SCSI_PAR|SERR_SPC_PAR)) 1683 != 0) { 1684 printf("%s: SCSI bus parity error\n", sc->sc_dev.dv_xname); 1685 if (sc->sc_prevphase == PH_MSGIN) { 1686 sc->sc_flags |= SPC_DROP_MSGIN; 1687 spc_sched_msgout(sc, SEND_PARITY_ERROR); 1688 } else 1689 spc_sched_msgout(sc, SEND_INIT_DET_ERR); 1690 } 1691 1692 /* 1693 * If we're not already busy doing something test for the following 1694 * conditions: 1695 * 1) We have been reselected by something 1696 * 2) We have selected something successfully 1697 * 3) Our selection process has timed out 1698 * 4) This is really a bus free interrupt just to get a new command 1699 * going? 1700 * 5) Spurious interrupt? 1701 */ 1702 switch (sc->sc_state) { 1703 case SPC_IDLE: 1704 case SPC_SELECTING: 1705 SPC_MISC(("ints:0x%02x ", ints)); 1706 1707 if ((ints & INTS_SEL) != 0) { 1708 /* 1709 * We don't currently support target mode. 1710 */ 1711 printf("%s: target mode selected; going to BUS FREE\n", 1712 sc->sc_dev.dv_xname); 1713 1714 goto sched; 1715 } else if ((ints & INTS_RESEL) != 0) { 1716 SPC_MISC(("reselected ")); 1717 1718 /* 1719 * If we're trying to select a target ourselves, 1720 * push our command back into the ready list. 1721 */ 1722 if (sc->sc_state == SPC_SELECTING) { 1723 SPC_MISC(("backoff selector ")); 1724 SPC_ASSERT(sc->sc_nexus != NULL); 1725 acb = sc->sc_nexus; 1726 sc->sc_nexus = NULL; 1727 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 1728 } 1729 1730 /* Save reselection ID. */ 1731 sc->sc_selid = bus_space_read_1(iot, ioh, TEMP); 1732 1733 sc->sc_state = SPC_RESELECTED; 1734 } else if ((ints & INTS_CMD_DONE) != 0) { 1735 SPC_MISC(("selected ")); 1736 1737 /* 1738 * We have selected a target. Things to do: 1739 * a) Determine what message(s) to send. 1740 * b) Verify that we're still selecting the target. 1741 * c) Mark device as busy. 1742 */ 1743 if (sc->sc_state != SPC_SELECTING) { 1744 printf("%s: selection out while idle; " 1745 "resetting\n", sc->sc_dev.dv_xname); 1746 SPC_BREAK(); 1747 goto reset; 1748 } 1749 SPC_ASSERT(sc->sc_nexus != NULL); 1750 acb = sc->sc_nexus; 1751 periph = acb->xs->xs_periph; 1752 ti = &sc->sc_tinfo[periph->periph_target]; 1753 1754 sc->sc_msgpriq = SEND_IDENTIFY; 1755 if (acb->flags & ACB_RESET) 1756 sc->sc_msgpriq |= SEND_DEV_RESET; 1757 else if (acb->flags & ACB_ABORT) 1758 sc->sc_msgpriq |= SEND_ABORT; 1759 else { 1760 #if SPC_USE_SYNCHRONOUS 1761 if ((ti->flags & DO_SYNC) != 0) 1762 sc->sc_msgpriq |= SEND_SDTR; 1763 #endif 1764 #if SPC_USE_WIDE 1765 if ((ti->flags & DO_WIDE) != 0) 1766 sc->sc_msgpriq |= SEND_WDTR; 1767 #endif 1768 } 1769 1770 acb->flags |= ACB_NEXUS; 1771 ti->lubusy |= (1 << periph->periph_lun); 1772 1773 /* Do an implicit RESTORE POINTERS. */ 1774 sc->sc_dp = acb->data_addr; 1775 sc->sc_dleft = acb->data_length; 1776 sc->sc_cp = (u_char *)&acb->scsipi_cmd; 1777 sc->sc_cleft = acb->scsipi_cmd_length; 1778 1779 /* On our first connection, schedule a timeout. */ 1780 if ((acb->xs->xs_control & XS_CTL_POLL) == 0) 1781 callout_reset(&acb->xs->xs_callout, 1782 mstohz(acb->timeout), spc_timeout, acb); 1783 1784 sc->sc_state = SPC_CONNECTED; 1785 } else if ((ints & INTS_TIMEOUT) != 0) { 1786 SPC_MISC(("selection timeout ")); 1787 1788 if (sc->sc_state != SPC_SELECTING) { 1789 printf("%s: selection timeout while idle; " 1790 "resetting\n", sc->sc_dev.dv_xname); 1791 SPC_BREAK(); 1792 goto reset; 1793 } 1794 SPC_ASSERT(sc->sc_nexus != NULL); 1795 acb = sc->sc_nexus; 1796 1797 delay(250); 1798 1799 acb->xs->error = XS_SELTIMEOUT; 1800 goto finish; 1801 } else { 1802 if (sc->sc_state != SPC_IDLE) { 1803 printf("%s: BUS FREE while not idle; " 1804 "state=%d\n", 1805 sc->sc_dev.dv_xname, sc->sc_state); 1806 SPC_BREAK(); 1807 goto out; 1808 } 1809 1810 goto sched; 1811 } 1812 1813 /* 1814 * Turn off selection stuff, and prepare to catch bus free 1815 * interrupts, parity errors, and phase changes. 1816 */ 1817 1818 sc->sc_flags = 0; 1819 sc->sc_prevphase = PH_INVALID; 1820 goto dophase; 1821 } 1822 1823 if ((ints & INTS_DISCON) != 0) { 1824 /* We've gone to BUS FREE phase. */ 1825 /* disable disconnect interrupt */ 1826 bus_space_write_1(iot, ioh, PCTL, 1827 bus_space_read_1(iot, ioh, PCTL) & ~PCTL_BFINT_ENAB); 1828 /* XXX reset interrput */ 1829 bus_space_write_1(iot, ioh, INTS, ints); 1830 1831 switch (sc->sc_state) { 1832 case SPC_RESELECTED: 1833 goto sched; 1834 1835 case SPC_CONNECTED: 1836 SPC_ASSERT(sc->sc_nexus != NULL); 1837 acb = sc->sc_nexus; 1838 1839 #if SPC_USE_SYNCHRONOUS + SPC_USE_WIDE 1840 if (sc->sc_prevphase == PH_MSGOUT) { 1841 /* 1842 * If the target went to BUS FREE phase during 1843 * or immediately after sending a SDTR or WDTR 1844 * message, disable negotiation. 1845 */ 1846 periph = acb->xs->xs_periph; 1847 ti = &sc->sc_tinfo[periph->periph_target]; 1848 switch (sc->sc_lastmsg) { 1849 #if SPC_USE_SYNCHRONOUS 1850 case SEND_SDTR: 1851 ti->flags &= ~DO_SYNC; 1852 ti->period = ti->offset = 0; 1853 break; 1854 #endif 1855 #if SPC_USE_WIDE 1856 case SEND_WDTR: 1857 ti->flags &= ~DO_WIDE; 1858 ti->width = 0; 1859 break; 1860 #endif 1861 } 1862 } 1863 #endif 1864 1865 if ((sc->sc_flags & SPC_ABORTING) == 0) { 1866 /* 1867 * Section 5.1.1 of the SCSI 2 spec suggests 1868 * issuing a REQUEST SENSE following an 1869 * unexpected disconnect. Some devices go into 1870 * a contingent allegiance condition when 1871 * disconnecting, and this is necessary to 1872 * clean up their state. 1873 */ 1874 printf("%s: unexpected disconnect; " 1875 "sending REQUEST SENSE\n", 1876 sc->sc_dev.dv_xname); 1877 SPC_BREAK(); 1878 acb->target_stat = SCSI_CHECK; 1879 acb->xs->error = XS_NOERROR; 1880 goto finish; 1881 } 1882 1883 acb->xs->error = XS_DRIVER_STUFFUP; 1884 goto finish; 1885 1886 case SPC_DISCONNECT: 1887 SPC_ASSERT(sc->sc_nexus != NULL); 1888 acb = sc->sc_nexus; 1889 TAILQ_INSERT_HEAD(&sc->nexus_list, acb, chain); 1890 sc->sc_nexus = NULL; 1891 goto sched; 1892 1893 case SPC_CMDCOMPLETE: 1894 SPC_ASSERT(sc->sc_nexus != NULL); 1895 acb = sc->sc_nexus; 1896 goto finish; 1897 } 1898 } 1899 else if ((ints & INTS_CMD_DONE) != 0 && 1900 sc->sc_prevphase == PH_MSGIN && 1901 sc->sc_state != SPC_CONNECTED) 1902 goto out; 1903 1904 dophase: 1905 #if 0 1906 if ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) == 0) { 1907 /* Wait for REQINIT. */ 1908 goto out; 1909 } 1910 #else 1911 bus_space_write_1(iot, ioh, INTS, ints); 1912 ints = 0; 1913 while ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) == 0) 1914 delay(1); /* need timeout XXX */ 1915 #endif 1916 1917 /* 1918 * State transition. 1919 */ 1920 sc->sc_phase = bus_space_read_1(iot, ioh, PSNS) & PH_MASK; 1921 #if 0 1922 bus_space_write_1(iot, ioh, PCTL, sc->sc_phase); 1923 #endif 1924 1925 SPC_MISC(("phase=%d\n", sc->sc_phase)); 1926 switch (sc->sc_phase) { 1927 case PH_MSGOUT: 1928 if (sc->sc_state != SPC_CONNECTED && 1929 sc->sc_state != SPC_RESELECTED) 1930 break; 1931 spc_msgout(sc); 1932 sc->sc_prevphase = PH_MSGOUT; 1933 goto loop; 1934 1935 case PH_MSGIN: 1936 if (sc->sc_state != SPC_CONNECTED && 1937 sc->sc_state != SPC_RESELECTED) 1938 break; 1939 spc_msgin(sc); 1940 sc->sc_prevphase = PH_MSGIN; 1941 goto loop; 1942 1943 case PH_CMD: 1944 if (sc->sc_state != SPC_CONNECTED) 1945 break; 1946 #if SPC_DEBUG 1947 if ((spc_debug & SPC_SHOWMISC) != 0) { 1948 SPC_ASSERT(sc->sc_nexus != NULL); 1949 acb = sc->sc_nexus; 1950 printf("cmd=0x%02x+%d ", 1951 acb->scsipi_cmd.opcode, acb->scsipi_cmd_length - 1); 1952 } 1953 #endif 1954 n = spc_dataout_pio(sc, sc->sc_cp, sc->sc_cleft); 1955 sc->sc_cp += n; 1956 sc->sc_cleft -= n; 1957 sc->sc_prevphase = PH_CMD; 1958 goto loop; 1959 1960 case PH_DATAOUT: 1961 if (sc->sc_state != SPC_CONNECTED) 1962 break; 1963 SPC_MISC(("dataout dleft=%d ", sc->sc_dleft)); 1964 if (sc->sc_dma_start != NULL && 1965 sc->sc_dleft > SPC_MIN_DMA_LEN) { 1966 (*sc->sc_dma_start)(sc, sc->sc_dp, sc->sc_dleft, 0); 1967 sc->sc_prevphase = PH_DATAOUT; 1968 goto out; 1969 } 1970 n = spc_dataout_pio(sc, sc->sc_dp, sc->sc_dleft); 1971 sc->sc_dp += n; 1972 sc->sc_dleft -= n; 1973 sc->sc_prevphase = PH_DATAOUT; 1974 goto loop; 1975 1976 case PH_DATAIN: 1977 if (sc->sc_state != SPC_CONNECTED) 1978 break; 1979 SPC_MISC(("datain ")); 1980 if (sc->sc_dma_start != NULL && 1981 sc->sc_dleft > SPC_MIN_DMA_LEN) { 1982 (*sc->sc_dma_start)(sc, sc->sc_dp, sc->sc_dleft, 1); 1983 sc->sc_prevphase = PH_DATAIN; 1984 goto out; 1985 } 1986 n = spc_datain_pio(sc, sc->sc_dp, sc->sc_dleft); 1987 sc->sc_dp += n; 1988 sc->sc_dleft -= n; 1989 sc->sc_prevphase = PH_DATAIN; 1990 goto loop; 1991 1992 case PH_STAT: 1993 if (sc->sc_state != SPC_CONNECTED) 1994 break; 1995 SPC_ASSERT(sc->sc_nexus != NULL); 1996 acb = sc->sc_nexus; 1997 1998 #ifdef NO_MANUAL_XFER 1999 spc_datain_pio(sc, &acb->target_stat, 1); 2000 #else 2001 if ((bus_space_read_1(iot, ioh, PSNS) & PSNS_ATN) != 0) 2002 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ATN); 2003 while ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) == 0) 2004 continue; /* XXX needs timeout */ 2005 bus_space_write_1(iot, ioh, PCTL, PH_STAT); 2006 acb->target_stat = bus_space_read_1(iot, ioh, TEMP); 2007 bus_space_write_1(iot, ioh, SCMD, SCMD_SET_ACK); 2008 while ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) != 0) 2009 continue; /* XXX needs timeout */ 2010 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ACK); 2011 #endif 2012 2013 SPC_MISC(("target_stat=0x%02x ", acb->target_stat)); 2014 sc->sc_prevphase = PH_STAT; 2015 goto loop; 2016 } 2017 2018 printf("%s: unexpected bus phase; resetting\n", sc->sc_dev.dv_xname); 2019 SPC_BREAK(); 2020 reset: 2021 spc_init(sc); 2022 return 1; 2023 2024 finish: 2025 callout_stop(&acb->xs->xs_callout); 2026 bus_space_write_1(iot, ioh, INTS, ints); 2027 ints = 0; 2028 spc_done(sc, acb); 2029 goto out; 2030 2031 sched: 2032 sc->sc_state = SPC_IDLE; 2033 spc_sched(sc); 2034 goto out; 2035 2036 out: 2037 if (ints) 2038 bus_space_write_1(iot, ioh, INTS, ints); 2039 bus_space_write_1(iot, ioh, SCTL, 2040 bus_space_read_1(iot, ioh, SCTL) | SCTL_INTR_ENAB); 2041 return 1; 2042 } 2043 2044 void 2045 spc_abort(sc, acb) 2046 struct spc_softc *sc; 2047 struct spc_acb *acb; 2048 { 2049 2050 /* 2 secs for the abort */ 2051 acb->timeout = SPC_ABORT_TIMEOUT; 2052 acb->flags |= ACB_ABORT; 2053 2054 if (acb == sc->sc_nexus) { 2055 /* 2056 * If we're still selecting, the message will be scheduled 2057 * after selection is complete. 2058 */ 2059 if (sc->sc_state == SPC_CONNECTED) 2060 spc_sched_msgout(sc, SEND_ABORT); 2061 } else { 2062 spc_dequeue(sc, acb); 2063 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 2064 if (sc->sc_state == SPC_IDLE) 2065 spc_sched(sc); 2066 } 2067 } 2068 2069 void 2070 spc_timeout(arg) 2071 void *arg; 2072 { 2073 struct spc_acb *acb = arg; 2074 struct scsipi_xfer *xs = acb->xs; 2075 struct scsipi_periph *periph = xs->xs_periph; 2076 struct spc_softc *sc; 2077 int s; 2078 2079 sc = (void *)periph->periph_channel->chan_adapter->adapt_dev; 2080 scsipi_printaddr(periph); 2081 printf("timed out"); 2082 2083 s = splbio(); 2084 2085 if (acb->flags & ACB_ABORT) { 2086 /* abort timed out */ 2087 printf(" AGAIN\n"); 2088 /* XXX Must reset! */ 2089 } else { 2090 /* abort the operation that has timed out */ 2091 printf("\n"); 2092 acb->xs->error = XS_TIMEOUT; 2093 spc_abort(sc, acb); 2094 } 2095 2096 splx(s); 2097 } 2098 2099 #ifdef SPC_DEBUG 2100 /* 2101 * The following functions are mostly used for debugging purposes, either 2102 * directly called from the driver or from the kernel debugger. 2103 */ 2104 2105 void 2106 spc_show_scsi_cmd(acb) 2107 struct spc_acb *acb; 2108 { 2109 u_char *b = (u_char *)&acb->scsipi_cmd; 2110 int i; 2111 2112 scsipi_printaddr(acb->xs->xs_periph); 2113 if ((acb->xs->xs_control & XS_CTL_RESET) == 0) { 2114 for (i = 0; i < acb->scsipi_cmd_length; i++) { 2115 if (i) 2116 printf(","); 2117 printf("%x", b[i]); 2118 } 2119 printf("\n"); 2120 } else 2121 printf("RESET\n"); 2122 } 2123 2124 void 2125 spc_print_acb(acb) 2126 struct spc_acb *acb; 2127 { 2128 2129 printf("acb@%p xs=%p flags=%x", acb, acb->xs, acb->flags); 2130 printf(" dp=%p dleft=%d target_stat=%x\n", 2131 acb->data_addr, acb->data_length, acb->target_stat); 2132 spc_show_scsi_cmd(acb); 2133 } 2134 2135 void 2136 spc_print_active_acb() 2137 { 2138 struct spc_acb *acb; 2139 struct spc_softc *sc = spc_cd.cd_devs[0]; /* XXX */ 2140 2141 printf("ready list:\n"); 2142 TAILQ_FOREACH(acb, &sc->ready_list, chain) 2143 spc_print_acb(acb); 2144 printf("nexus:\n"); 2145 if (sc->sc_nexus != NULL) 2146 spc_print_acb(sc->sc_nexus); 2147 printf("nexus list:\n"); 2148 TAILQ_FOREACH(acb, &sc->nexus_list, chain) 2149 spc_print_acb(acb); 2150 } 2151 2152 void 2153 spc_dump89352(sc) 2154 struct spc_softc *sc; 2155 { 2156 bus_space_tag_t iot = sc->sc_iot; 2157 bus_space_handle_t ioh = sc->sc_ioh; 2158 2159 printf("mb89352: BDID=%x SCTL=%x SCMD=%x TMOD=%x\n", 2160 bus_space_read_1(iot, ioh, BDID), 2161 bus_space_read_1(iot, ioh, SCTL), 2162 bus_space_read_1(iot, ioh, SCMD), 2163 bus_space_read_1(iot, ioh, TMOD)); 2164 printf(" INTS=%x PSNS=%x SSTS=%x SERR=%x PCTL=%x\n", 2165 bus_space_read_1(iot, ioh, INTS), 2166 bus_space_read_1(iot, ioh, PSNS), 2167 bus_space_read_1(iot, ioh, SSTS), 2168 bus_space_read_1(iot, ioh, SERR), 2169 bus_space_read_1(iot, ioh, PCTL)); 2170 printf(" MBC=%x DREG=%x TEMP=%x TCH=%x TCM=%x\n", 2171 bus_space_read_1(iot, ioh, MBC), 2172 #if 0 2173 bus_space_read_1(iot, ioh, DREG), 2174 #else 2175 0, 2176 #endif 2177 bus_space_read_1(iot, ioh, TEMP), 2178 bus_space_read_1(iot, ioh, TCH), 2179 bus_space_read_1(iot, ioh, TCM)); 2180 printf(" TCL=%x EXBF=%x\n", 2181 bus_space_read_1(iot, ioh, TCL), 2182 bus_space_read_1(iot, ioh, EXBF)); 2183 } 2184 2185 void 2186 spc_dump_driver(sc) 2187 struct spc_softc *sc; 2188 { 2189 struct spc_tinfo *ti; 2190 int i; 2191 2192 printf("nexus=%p prevphase=%x\n", sc->sc_nexus, sc->sc_prevphase); 2193 printf("state=%x msgin=%x msgpriq=%x msgoutq=%x lastmsg=%x " 2194 "currmsg=%x\n", sc->sc_state, sc->sc_imess[0], 2195 sc->sc_msgpriq, sc->sc_msgoutq, sc->sc_lastmsg, sc->sc_currmsg); 2196 for (i = 0; i < 7; i++) { 2197 ti = &sc->sc_tinfo[i]; 2198 printf("tinfo%d: %d cmds %d disconnects %d timeouts", 2199 i, ti->cmds, ti->dconns, ti->touts); 2200 printf(" %d senses flags=%x\n", ti->senses, ti->flags); 2201 } 2202 } 2203 #endif
Cache object: 05f5e471aea281480a708d6b0347e146
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