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sys/dev/ic/mb89352.c
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1 /* $NetBSD: mb89352.c,v 1.45 2006/11/16 01:32:51 christos Exp $ */ 2 /* NecBSD: mb89352.c,v 1.4 1998/03/14 07:31:20 kmatsuda Exp */ 3 4 /*- 5 * Copyright (c) 1996,97,98,99,2004 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Charles M. Hannum, Masaru Oki and Kouichi Matsuda. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Charles M. Hannum. 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * Copyright (c) 1994 Jarle Greipsland 26 * All rights reserved. 27 * 28 * Redistribution and use in source and binary forms, with or without 29 * modification, are permitted provided that the following conditions 30 * are met: 31 * 1. Redistributions of source code must retain the above copyright 32 * notice, this list of conditions and the following disclaimer. 33 * 2. Redistributions in binary form must reproduce the above copyright 34 * notice, this list of conditions and the following disclaimer in the 35 * documentation and/or other materials provided with the distribution. 36 * 3. The name of the author may not be used to endorse or promote products 37 * derived from this software without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 40 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 41 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 42 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 43 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 44 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 45 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 46 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 47 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 48 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 49 * POSSIBILITY OF SUCH DAMAGE. 50 */ 51 /* 52 * [NetBSD for NEC PC-98 series] 53 * Copyright (c) 1996, 1997, 1998 54 * NetBSD/pc98 porting staff. All rights reserved. 55 * Copyright (c) 1996, 1997, 1998 56 * Kouichi Matsuda. All rights reserved. 57 */ 58 59 /* 60 * Acknowledgements: Many of the algorithms used in this driver are 61 * inspired by the work of Julian Elischer (julian@tfs.com) and 62 * Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million! 63 */ 64 65 /* TODO list: 66 * 1) Get the DMA stuff working. 67 * 2) Get the iov/uio stuff working. Is this a good thing ??? 68 * 3) Get the synch stuff working. 69 * 4) Rewrite it to use malloc for the acb structs instead of static alloc.? 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: mb89352.c,v 1.45 2006/11/16 01:32:51 christos Exp $"); 74 75 #ifdef DDB 76 #define integrate 77 #else 78 #define integrate inline static 79 #endif 80 81 /* 82 * A few customizable items: 83 */ 84 85 /* Synchronous data transfers? */ 86 #define SPC_USE_SYNCHRONOUS 0 87 #define SPC_SYNC_REQ_ACK_OFS 8 88 89 /* Wide data transfers? */ 90 #define SPC_USE_WIDE 0 91 #define SPC_MAX_WIDTH 0 92 93 /* Max attempts made to transmit a message */ 94 #define SPC_MSG_MAX_ATTEMPT 3 /* Not used now XXX */ 95 96 /* 97 * Some spin loop parameters (essentially how long to wait some places) 98 * The problem(?) is that sometimes we expect either to be able to transmit a 99 * byte or to get a new one from the SCSI bus pretty soon. In order to avoid 100 * returning from the interrupt just to get yanked back for the next byte we 101 * may spin in the interrupt routine waiting for this byte to come. How long? 102 * This is really (SCSI) device and processor dependent. Tuneable, I guess. 103 */ 104 #define SPC_MSGIN_SPIN 1 /* Will spinwait upto ?ms for a new msg byte */ 105 #define SPC_MSGOUT_SPIN 1 106 107 /* 108 * Include debug functions? At the end of this file there are a bunch of 109 * functions that will print out various information regarding queued SCSI 110 * commands, driver state and chip contents. You can call them from the 111 * kernel debugger. If you set SPC_DEBUG to 0 they are not included (the 112 * kernel uses less memory) but you lose the debugging facilities. 113 */ 114 #if 0 115 #define SPC_DEBUG 1 116 #endif 117 118 #define SPC_ABORT_TIMEOUT 2000 /* time to wait for abort */ 119 120 /* threshold length for DMA transfer */ 121 #define SPC_MIN_DMA_LEN 32 122 123 #ifdef x68k /* XXX it seems x68k SPC SCSI hardware has some quirks */ 124 #define NEED_DREQ_ON_HARDWARE_XFER 125 #define NO_MANUAL_XFER 126 #endif 127 128 /* End of customizable parameters */ 129 130 /* 131 * MB89352 SCSI Protocol Controller (SPC) routines. 132 */ 133 134 #include "opt_ddb.h" 135 136 #include <sys/param.h> 137 #include <sys/systm.h> 138 #include <sys/kernel.h> 139 #include <sys/errno.h> 140 #include <sys/ioctl.h> 141 #include <sys/device.h> 142 #include <sys/buf.h> 143 #include <sys/proc.h> 144 #include <sys/user.h> 145 #include <sys/queue.h> 146 147 #include <machine/intr.h> 148 #include <machine/bus.h> 149 150 #include <dev/scsipi/scsi_all.h> 151 #include <dev/scsipi/scsipi_all.h> 152 #include <dev/scsipi/scsi_message.h> 153 #include <dev/scsipi/scsiconf.h> 154 155 #include <dev/ic/mb89352reg.h> 156 #include <dev/ic/mb89352var.h> 157 158 #ifndef DDB 159 #define Debugger() panic("should call debugger here (mb89352.c)") 160 #endif /* ! DDB */ 161 162 #if SPC_DEBUG 163 int spc_debug = 0x00; /* SPC_SHOWSTART|SPC_SHOWMISC|SPC_SHOWTRACE; */ 164 #endif 165 166 void spc_done(struct spc_softc *, struct spc_acb *); 167 void spc_dequeue(struct spc_softc *, struct spc_acb *); 168 void spc_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, 169 void *); 170 int spc_poll(struct spc_softc *, struct scsipi_xfer *, int); 171 integrate void spc_sched_msgout(struct spc_softc *, u_char); 172 integrate void spc_setsync(struct spc_softc *, struct spc_tinfo *); 173 void spc_select(struct spc_softc *, struct spc_acb *); 174 void spc_timeout(void *); 175 void spc_scsi_reset(struct spc_softc *); 176 void spc_reset(struct spc_softc *); 177 void spc_free_acb(struct spc_softc *, struct spc_acb *, int); 178 struct spc_acb* spc_get_acb(struct spc_softc *); 179 int spc_reselect(struct spc_softc *, int); 180 void spc_msgin(struct spc_softc *); 181 void spc_abort(struct spc_softc *, struct spc_acb *); 182 void spc_msgout(struct spc_softc *); 183 int spc_dataout_pio(struct spc_softc *, u_char *, int); 184 int spc_datain_pio(struct spc_softc *, u_char *, int); 185 #if SPC_DEBUG 186 void spc_print_acb(struct spc_acb *); 187 void spc_dump_driver(struct spc_softc *); 188 void spc_dump89352(struct spc_softc *); 189 void spc_show_scsi_cmd(struct spc_acb *); 190 void spc_print_active_acb(void); 191 #endif 192 193 extern struct cfdriver spc_cd; 194 195 /* 196 * INITIALIZATION ROUTINES (probe, attach ++) 197 */ 198 199 /* 200 * Do the real search-for-device. 201 * Prerequisite: sc->sc_iobase should be set to the proper value 202 */ 203 int 204 spc_find(bus_space_tag_t iot, bus_space_handle_t ioh, int bdid) 205 { 206 long timeout = SPC_ABORT_TIMEOUT; 207 208 SPC_TRACE(("spc: probing for spc-chip\n")); 209 /* 210 * Disable interrupts then reset the FUJITSU chip. 211 */ 212 bus_space_write_1(iot, ioh, SCTL, SCTL_DISABLE | SCTL_CTRLRST); 213 bus_space_write_1(iot, ioh, SCMD, 0); 214 bus_space_write_1(iot, ioh, PCTL, 0); 215 bus_space_write_1(iot, ioh, TEMP, 0); 216 bus_space_write_1(iot, ioh, TCH, 0); 217 bus_space_write_1(iot, ioh, TCM, 0); 218 bus_space_write_1(iot, ioh, TCL, 0); 219 bus_space_write_1(iot, ioh, INTS, 0); 220 bus_space_write_1(iot, ioh, SCTL, 221 SCTL_DISABLE | SCTL_ABRT_ENAB | SCTL_PARITY_ENAB | SCTL_RESEL_ENAB); 222 bus_space_write_1(iot, ioh, BDID, bdid); 223 delay(400); 224 bus_space_write_1(iot, ioh, SCTL, 225 bus_space_read_1(iot, ioh, SCTL) & ~SCTL_DISABLE); 226 227 /* The following detection is derived from spc.c 228 * (by Takahide Matsutsuka) in FreeBSD/pccard-test. 229 */ 230 while (bus_space_read_1(iot, ioh, PSNS) && timeout) { 231 timeout--; 232 DELAY(1); 233 } 234 if (timeout == 0) { 235 printf("spc: find failed\n"); 236 return 0; 237 } 238 239 SPC_START(("SPC found")); 240 return 1; 241 } 242 243 void 244 spc_attach(struct spc_softc *sc) 245 { 246 struct scsipi_adapter *adapt = &sc->sc_adapter; 247 struct scsipi_channel *chan = &sc->sc_channel; 248 249 SPC_TRACE(("spc_attach ")); 250 sc->sc_state = SPC_INIT; 251 252 sc->sc_freq = 20; /* XXXX Assume 20 MHz. */ 253 254 #if SPC_USE_SYNCHRONOUS 255 /* 256 * These are the bounds of the sync period, based on the frequency of 257 * the chip's clock input and the size and offset of the sync period 258 * register. 259 * 260 * For a 20MHz clock, this gives us 25, or 100nS, or 10MB/s, as a 261 * maximum transfer rate, and 112.5, or 450nS, or 2.22MB/s, as a 262 * minimum transfer rate. 263 */ 264 sc->sc_minsync = (2 * 250) / sc->sc_freq; 265 sc->sc_maxsync = (9 * 250) / sc->sc_freq; 266 #endif 267 268 /* 269 * Fill in the adapter. 270 */ 271 adapt->adapt_dev = &sc->sc_dev; 272 adapt->adapt_nchannels = 1; 273 adapt->adapt_openings = 7; 274 adapt->adapt_max_periph = 1; 275 adapt->adapt_request = spc_scsipi_request; 276 adapt->adapt_minphys = minphys; 277 278 chan->chan_adapter = &sc->sc_adapter; 279 chan->chan_bustype = &scsi_bustype; 280 chan->chan_channel = 0; 281 chan->chan_ntargets = 8; 282 chan->chan_nluns = 8; 283 chan->chan_id = sc->sc_initiator; 284 285 /* 286 * Add reference to adapter so that we drop the reference after 287 * config_found() to make sure the adatper is disabled. 288 */ 289 if (scsipi_adapter_addref(adapt) != 0) { 290 printf("%s: unable to enable controller\n", 291 sc->sc_dev.dv_xname); 292 return; 293 } 294 295 spc_init(sc, 1); /* Init chip and driver */ 296 297 /* 298 * ask the adapter what subunits are present 299 */ 300 sc->sc_child = config_found(&sc->sc_dev, chan, scsiprint); 301 scsipi_adapter_delref(adapt); 302 } 303 304 int 305 spc_activate(struct device *self, enum devact act) 306 { 307 struct spc_softc *sc = (void *)self; 308 int s, rv = 0; 309 310 s = splhigh(); 311 switch (act) { 312 case DVACT_ACTIVATE: 313 rv = EOPNOTSUPP; 314 break; 315 316 case DVACT_DEACTIVATE: 317 if (sc->sc_child != NULL) 318 rv = config_deactivate(sc->sc_child); 319 break; 320 } 321 splx(s); 322 323 return (rv); 324 } 325 326 int 327 spc_detach(struct device *self, int flags) 328 { 329 struct spc_softc *sc = (void *)self; 330 int rv = 0; 331 332 if (sc->sc_child != NULL) 333 rv = config_detach(sc->sc_child, flags); 334 335 return (rv); 336 } 337 338 /* 339 * Initialize MB89352 chip itself 340 * The following conditions should hold: 341 * spc_isa_probe should have succeeded, i.e. the iobase address in spc_softc 342 * must be valid. 343 */ 344 void 345 spc_reset(struct spc_softc *sc) 346 { 347 bus_space_tag_t iot = sc->sc_iot; 348 bus_space_handle_t ioh = sc->sc_ioh; 349 350 SPC_TRACE(("spc_reset ")); 351 /* 352 * Disable interrupts then reset the FUJITSU chip. 353 */ 354 bus_space_write_1(iot, ioh, SCTL, SCTL_DISABLE | SCTL_CTRLRST); 355 bus_space_write_1(iot, ioh, SCMD, 0); 356 bus_space_write_1(iot, ioh, TMOD, 0); 357 bus_space_write_1(iot, ioh, PCTL, 0); 358 bus_space_write_1(iot, ioh, TEMP, 0); 359 bus_space_write_1(iot, ioh, TCH, 0); 360 bus_space_write_1(iot, ioh, TCM, 0); 361 bus_space_write_1(iot, ioh, TCL, 0); 362 bus_space_write_1(iot, ioh, INTS, 0); 363 bus_space_write_1(iot, ioh, SCTL, 364 SCTL_DISABLE | SCTL_ABRT_ENAB | SCTL_PARITY_ENAB | SCTL_RESEL_ENAB); 365 bus_space_write_1(iot, ioh, BDID, sc->sc_initiator); 366 delay(400); 367 bus_space_write_1(iot, ioh, SCTL, 368 bus_space_read_1(iot, ioh, SCTL) & ~SCTL_DISABLE); 369 } 370 371 372 /* 373 * Pull the SCSI RST line for 500us. 374 */ 375 void 376 spc_scsi_reset(struct spc_softc *sc) 377 { 378 bus_space_tag_t iot = sc->sc_iot; 379 bus_space_handle_t ioh = sc->sc_ioh; 380 381 SPC_TRACE(("spc_scsi_reset ")); 382 bus_space_write_1(iot, ioh, SCMD, 383 bus_space_read_1(iot, ioh, SCMD) | SCMD_RST); 384 delay(500); 385 bus_space_write_1(iot, ioh, SCMD, 386 bus_space_read_1(iot, ioh, SCMD) & ~SCMD_RST); 387 delay(50); 388 } 389 390 /* 391 * Initialize spc SCSI driver. 392 */ 393 void 394 spc_init(struct spc_softc *sc, int bus_reset) 395 { 396 struct spc_acb *acb; 397 int r; 398 399 SPC_TRACE(("spc_init ")); 400 if (bus_reset) { 401 spc_reset(sc); 402 spc_scsi_reset(sc); 403 } 404 spc_reset(sc); 405 406 if (sc->sc_state == SPC_INIT) { 407 /* First time through; initialize. */ 408 TAILQ_INIT(&sc->ready_list); 409 TAILQ_INIT(&sc->nexus_list); 410 TAILQ_INIT(&sc->free_list); 411 sc->sc_nexus = NULL; 412 acb = sc->sc_acb; 413 memset(acb, 0, sizeof(sc->sc_acb)); 414 for (r = 0; r < sizeof(sc->sc_acb) / sizeof(*acb); r++) { 415 TAILQ_INSERT_TAIL(&sc->free_list, acb, chain); 416 acb++; 417 } 418 memset(&sc->sc_tinfo, 0, sizeof(sc->sc_tinfo)); 419 } else { 420 /* Cancel any active commands. */ 421 sc->sc_state = SPC_CLEANING; 422 if ((acb = sc->sc_nexus) != NULL) { 423 acb->xs->error = XS_DRIVER_STUFFUP; 424 callout_stop(&acb->xs->xs_callout); 425 spc_done(sc, acb); 426 } 427 while ((acb = TAILQ_FIRST(&sc->nexus_list)) != NULL) { 428 acb->xs->error = XS_DRIVER_STUFFUP; 429 callout_stop(&acb->xs->xs_callout); 430 spc_done(sc, acb); 431 } 432 } 433 434 sc->sc_prevphase = PH_INVALID; 435 for (r = 0; r < 8; r++) { 436 struct spc_tinfo *ti = &sc->sc_tinfo[r]; 437 438 ti->flags = 0; 439 #if SPC_USE_SYNCHRONOUS 440 ti->flags |= DO_SYNC; 441 ti->period = sc->sc_minsync; 442 ti->offset = SPC_SYNC_REQ_ACK_OFS; 443 #else 444 ti->period = ti->offset = 0; 445 #endif 446 #if SPC_USE_WIDE 447 ti->flags |= DO_WIDE; 448 ti->width = SPC_MAX_WIDTH; 449 #else 450 ti->width = 0; 451 #endif 452 } 453 454 sc->sc_state = SPC_IDLE; 455 bus_space_write_1(sc->sc_iot, sc->sc_ioh, SCTL, 456 bus_space_read_1(sc->sc_iot, sc->sc_ioh, SCTL) | SCTL_INTR_ENAB); 457 } 458 459 void 460 spc_free_acb(struct spc_softc *sc, struct spc_acb *acb, int flags) 461 { 462 int s; 463 464 SPC_TRACE(("spc_free_acb ")); 465 s = splbio(); 466 467 acb->flags = 0; 468 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 469 splx(s); 470 } 471 472 struct spc_acb * 473 spc_get_acb(struct spc_softc *sc) 474 { 475 struct spc_acb *acb; 476 int s; 477 478 SPC_TRACE(("spc_get_acb ")); 479 s = splbio(); 480 acb = TAILQ_FIRST(&sc->free_list); 481 if (acb != NULL) { 482 TAILQ_REMOVE(&sc->free_list, acb, chain); 483 acb->flags |= ACB_ALLOC; 484 } 485 splx(s); 486 return acb; 487 } 488 489 /* 490 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 491 */ 492 493 /* 494 * Expected sequence: 495 * 1) Command inserted into ready list 496 * 2) Command selected for execution 497 * 3) Command won arbitration and has selected target device 498 * 4) Send message out (identify message, eventually also sync.negotiations) 499 * 5) Send command 500 * 5a) Receive disconnect message, disconnect. 501 * 5b) Reselected by target 502 * 5c) Receive identify message from target. 503 * 6) Send or receive data 504 * 7) Receive status 505 * 8) Receive message (command complete etc.) 506 */ 507 508 /* 509 * Start a SCSI-command 510 * This function is called by the higher level SCSI-driver to queue/run 511 * SCSI-commands. 512 */ 513 void 514 spc_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 515 void *arg) 516 { 517 struct scsipi_xfer *xs; 518 struct scsipi_periph *periph; 519 struct spc_softc *sc = (void *)chan->chan_adapter->adapt_dev; 520 struct spc_acb *acb; 521 int s, flags; 522 523 switch (req) { 524 case ADAPTER_REQ_RUN_XFER: 525 xs = arg; 526 periph = xs->xs_periph; 527 SPC_TRACE(("spc_scsipi_request ")); 528 SPC_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 529 periph->periph_target)); 530 531 flags = xs->xs_control; 532 acb = spc_get_acb(sc); 533 #ifdef DIAGNOSTIC 534 /* 535 * This should nerver happen as we track the resources 536 * in the mid-layer. 537 */ 538 if (acb == NULL) { 539 scsipi_printaddr(periph); 540 printf("unable to allocate acb\n"); 541 panic("spc_scsipi_request"); 542 } 543 #endif 544 545 /* Initialize acb */ 546 acb->xs = xs; 547 acb->timeout = xs->timeout; 548 549 if (xs->xs_control & XS_CTL_RESET) { 550 acb->flags |= ACB_RESET; 551 acb->scsipi_cmd_length = 0; 552 acb->data_length = 0; 553 } else { 554 memcpy(&acb->scsipi_cmd, xs->cmd, xs->cmdlen); 555 acb->scsipi_cmd_length = xs->cmdlen; 556 acb->data_addr = xs->data; 557 acb->data_length = xs->datalen; 558 } 559 acb->target_stat = 0; 560 561 s = splbio(); 562 563 TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain); 564 /* 565 * Start scheduling unless a queue process is in progress. 566 */ 567 if (sc->sc_state == SPC_IDLE) 568 spc_sched(sc); 569 /* 570 * After successful sending, check if we should return just now. 571 * If so, return SUCCESSFULLY_QUEUED. 572 */ 573 574 splx(s); 575 576 if ((flags & XS_CTL_POLL) == 0) 577 return; 578 579 /* Not allowed to use interrupts, use polling instead */ 580 s = splbio(); 581 if (spc_poll(sc, xs, acb->timeout)) { 582 spc_timeout(acb); 583 if (spc_poll(sc, xs, acb->timeout)) 584 spc_timeout(acb); 585 } 586 splx(s); 587 return; 588 case ADAPTER_REQ_GROW_RESOURCES: 589 /* XXX Not supported. */ 590 return; 591 case ADAPTER_REQ_SET_XFER_MODE: 592 { 593 /* 594 * We don't support Sync, Wide, or Tagged Command Queuing. 595 * Just callback now, to report this. 596 */ 597 struct scsipi_xfer_mode *xm = arg; 598 599 xm->xm_mode = 0; 600 xm->xm_period = 0; 601 xm->xm_offset = 0; 602 scsipi_async_event(chan, ASYNC_EVENT_XFER_MODE, xm); 603 return; 604 } 605 } 606 } 607 608 /* 609 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 610 */ 611 int 612 spc_poll(struct spc_softc *sc, struct scsipi_xfer *xs, int count) 613 { 614 bus_space_tag_t iot = sc->sc_iot; 615 bus_space_handle_t ioh = sc->sc_ioh; 616 617 SPC_TRACE(("spc_poll ")); 618 while (count) { 619 /* 620 * If we had interrupts enabled, would we 621 * have got an interrupt? 622 */ 623 if (bus_space_read_1(iot, ioh, INTS) != 0) 624 spc_intr(sc); 625 if ((xs->xs_status & XS_STS_DONE) != 0) 626 return 0; 627 delay(1000); 628 count--; 629 } 630 return 1; 631 } 632 633 /* 634 * LOW LEVEL SCSI UTILITIES 635 */ 636 637 integrate void 638 spc_sched_msgout(struct spc_softc *sc, u_char m) 639 { 640 bus_space_tag_t iot = sc->sc_iot; 641 bus_space_handle_t ioh = sc->sc_ioh; 642 643 SPC_TRACE(("spc_sched_msgout ")); 644 if (sc->sc_msgpriq == 0) 645 bus_space_write_1(iot, ioh, SCMD, SCMD_SET_ATN); 646 sc->sc_msgpriq |= m; 647 } 648 649 /* 650 * Set synchronous transfer offset and period. 651 */ 652 integrate void 653 spc_setsync(struct spc_softc *sc, struct spc_tinfo *ti) 654 { 655 #if SPC_USE_SYNCHRONOUS 656 bus_space_tag_t iot = sc->sc_iot; 657 bus_space_handle_t ioh = sc->sc_ioh; 658 659 SPC_TRACE(("spc_setsync ")); 660 if (ti->offset != 0) 661 bus_space_write_1(iot, ioh, TMOD, 662 ((ti->period * sc->sc_freq) / 250 - 2) << 4 | ti->offset); 663 else 664 bus_space_write_1(iot, ioh, TMOD, 0); 665 #endif 666 } 667 668 /* 669 * Start a selection. This is used by spc_sched() to select an idle target. 670 */ 671 void 672 spc_select(struct spc_softc *sc, struct spc_acb *acb) 673 { 674 struct scsipi_periph *periph = acb->xs->xs_periph; 675 int target = periph->periph_target; 676 struct spc_tinfo *ti = &sc->sc_tinfo[target]; 677 bus_space_tag_t iot = sc->sc_iot; 678 bus_space_handle_t ioh = sc->sc_ioh; 679 680 SPC_TRACE(("spc_select ")); 681 spc_setsync(sc, ti); 682 683 #if 0 684 bus_space_write_1(iot, ioh, SCMD, SCMD_SET_ATN); 685 #endif 686 687 bus_space_write_1(iot, ioh, PCTL, 0); 688 bus_space_write_1(iot, ioh, TEMP, 689 (1 << sc->sc_initiator) | (1 << target)); 690 /* 691 * Setup BSY timeout (selection timeout). 692 * 250ms according to the SCSI specification. 693 * T = (X * 256 + 15) * Tclf * 2 (Tclf = 200ns on x68k) 694 * To setup 256ms timeout, 695 * 128000ns/200ns = X * 256 + 15 696 * 640 - 15 = X * 256 697 * X = 625 / 256 698 * X = 2 + 113 / 256 699 * ==> tch = 2, tcm = 113 (correct?) 700 */ 701 /* Time to the information transfer phase start. */ 702 /* XXX These values should be calculated from sc_freq */ 703 bus_space_write_1(iot, ioh, TCH, 2); 704 bus_space_write_1(iot, ioh, TCM, 113); 705 bus_space_write_1(iot, ioh, TCL, 3); 706 bus_space_write_1(iot, ioh, SCMD, SCMD_SELECT); 707 708 sc->sc_state = SPC_SELECTING; 709 } 710 711 int 712 spc_reselect(struct spc_softc *sc, int message) 713 { 714 u_char selid, target, lun; 715 struct spc_acb *acb; 716 struct scsipi_periph *periph; 717 struct spc_tinfo *ti; 718 719 SPC_TRACE(("spc_reselect ")); 720 /* 721 * The SCSI chip made a snapshot of the data bus while the reselection 722 * was being negotiated. This enables us to determine which target did 723 * the reselect. 724 */ 725 selid = sc->sc_selid & ~(1 << sc->sc_initiator); 726 if (selid & (selid - 1)) { 727 printf("%s: reselect with invalid selid %02x; " 728 "sending DEVICE RESET\n", sc->sc_dev.dv_xname, selid); 729 SPC_BREAK(); 730 goto reset; 731 } 732 733 /* 734 * Search wait queue for disconnected cmd 735 * The list should be short, so I haven't bothered with 736 * any more sophisticated structures than a simple 737 * singly linked list. 738 */ 739 target = ffs(selid) - 1; 740 lun = message & 0x07; 741 TAILQ_FOREACH(acb, &sc->nexus_list, chain) { 742 periph = acb->xs->xs_periph; 743 if (periph->periph_target == target && 744 periph->periph_lun == lun) 745 break; 746 } 747 if (acb == NULL) { 748 printf("%s: reselect from target %d lun %d with no nexus; " 749 "sending ABORT\n", sc->sc_dev.dv_xname, target, lun); 750 SPC_BREAK(); 751 goto abort; 752 } 753 754 /* Make this nexus active again. */ 755 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 756 sc->sc_state = SPC_CONNECTED; 757 sc->sc_nexus = acb; 758 ti = &sc->sc_tinfo[target]; 759 ti->lubusy |= (1 << lun); 760 spc_setsync(sc, ti); 761 762 if (acb->flags & ACB_RESET) 763 spc_sched_msgout(sc, SEND_DEV_RESET); 764 else if (acb->flags & ACB_ABORT) 765 spc_sched_msgout(sc, SEND_ABORT); 766 767 /* Do an implicit RESTORE POINTERS. */ 768 sc->sc_dp = acb->data_addr; 769 sc->sc_dleft = acb->data_length; 770 sc->sc_cp = (u_char *)&acb->scsipi_cmd; 771 sc->sc_cleft = acb->scsipi_cmd_length; 772 773 return (0); 774 775 reset: 776 spc_sched_msgout(sc, SEND_DEV_RESET); 777 return (1); 778 779 abort: 780 spc_sched_msgout(sc, SEND_ABORT); 781 return (1); 782 } 783 784 /* 785 * Schedule a SCSI operation. This has now been pulled out of the interrupt 786 * handler so that we may call it from spc_scsi_cmd and spc_done. This may 787 * save us an unnecessary interrupt just to get things going. Should only be 788 * called when state == SPC_IDLE and at bio pl. 789 */ 790 void 791 spc_sched(struct spc_softc *sc) 792 { 793 struct spc_acb *acb; 794 struct scsipi_periph *periph; 795 struct spc_tinfo *ti; 796 797 /* missing the hw, just return and wait for our hw */ 798 if (sc->sc_flags & SPC_INACTIVE) 799 return; 800 SPC_TRACE(("spc_sched ")); 801 /* 802 * Find first acb in ready queue that is for a target/lunit pair that 803 * is not busy. 804 */ 805 TAILQ_FOREACH(acb, &sc->ready_list, chain) { 806 periph = acb->xs->xs_periph; 807 ti = &sc->sc_tinfo[periph->periph_target]; 808 if ((ti->lubusy & (1 << periph->periph_lun)) == 0) { 809 SPC_MISC(("selecting %d:%d ", 810 periph->periph_target, periph->periph_lun)); 811 TAILQ_REMOVE(&sc->ready_list, acb, chain); 812 sc->sc_nexus = acb; 813 spc_select(sc, acb); 814 return; 815 } else { 816 SPC_MISC(("%d:%d busy\n", 817 periph->periph_target, periph->periph_lun)); 818 } 819 } 820 SPC_MISC(("idle ")); 821 /* Nothing to start; just enable reselections and wait. */ 822 } 823 824 /* 825 * POST PROCESSING OF SCSI_CMD (usually current) 826 */ 827 void 828 spc_done(struct spc_softc *sc, struct spc_acb *acb) 829 { 830 struct scsipi_xfer *xs = acb->xs; 831 struct scsipi_periph *periph = xs->xs_periph; 832 struct spc_tinfo *ti = &sc->sc_tinfo[periph->periph_target]; 833 834 SPC_TRACE(("spc_done ")); 835 836 if (xs->error == XS_NOERROR) { 837 if (acb->flags & ACB_ABORT) { 838 xs->error = XS_DRIVER_STUFFUP; 839 } else { 840 switch (acb->target_stat) { 841 case SCSI_CHECK: 842 /* First, save the return values */ 843 xs->resid = acb->data_length; 844 /* FALLTHROUGH */ 845 case SCSI_BUSY: 846 xs->status = acb->target_stat; 847 xs->error = XS_BUSY; 848 break; 849 case SCSI_OK: 850 xs->resid = acb->data_length; 851 break; 852 default: 853 xs->error = XS_DRIVER_STUFFUP; 854 #if SPC_DEBUG 855 printf("%s: spc_done: bad stat 0x%x\n", 856 sc->sc_dev.dv_xname, acb->target_stat); 857 #endif 858 break; 859 } 860 } 861 } 862 863 #if SPC_DEBUG 864 if ((spc_debug & SPC_SHOWMISC) != 0) { 865 if (xs->resid != 0) 866 printf("resid=%d ", xs->resid); 867 else 868 printf("error=%d\n", xs->error); 869 } 870 #endif 871 872 /* 873 * Remove the ACB from whatever queue it happens to be on. 874 */ 875 if (acb->flags & ACB_NEXUS) 876 ti->lubusy &= ~(1 << periph->periph_lun); 877 if (acb == sc->sc_nexus) { 878 sc->sc_nexus = NULL; 879 sc->sc_state = SPC_IDLE; 880 spc_sched(sc); 881 } else 882 spc_dequeue(sc, acb); 883 884 spc_free_acb(sc, acb, xs->xs_control); 885 ti->cmds++; 886 scsipi_done(xs); 887 } 888 889 void 890 spc_dequeue(struct spc_softc *sc, struct spc_acb *acb) 891 { 892 893 SPC_TRACE(("spc_dequeue ")); 894 if (acb->flags & ACB_NEXUS) 895 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 896 else 897 TAILQ_REMOVE(&sc->ready_list, acb, chain); 898 } 899 900 /* 901 * INTERRUPT/PROTOCOL ENGINE 902 */ 903 904 /* 905 * Precondition: 906 * The SCSI bus is already in the MSGI phase and there is a message byte 907 * on the bus, along with an asserted REQ signal. 908 */ 909 void 910 spc_msgin(struct spc_softc *sc) 911 { 912 bus_space_tag_t iot = sc->sc_iot; 913 bus_space_handle_t ioh = sc->sc_ioh; 914 int n; 915 uint8_t msg; 916 917 SPC_TRACE(("spc_msgin ")); 918 919 if (sc->sc_prevphase == PH_MSGIN) { 920 /* This is a continuation of the previous message. */ 921 n = sc->sc_imp - sc->sc_imess; 922 goto nextbyte; 923 } 924 925 /* This is a new MESSAGE IN phase. Clean up our state. */ 926 sc->sc_flags &= ~SPC_DROP_MSGIN; 927 928 nextmsg: 929 n = 0; 930 sc->sc_imp = &sc->sc_imess[n]; 931 932 nextbyte: 933 /* 934 * Read a whole message, but don't ack the last byte. If we reject the 935 * message, we have to assert ATN during the message transfer phase 936 * itself. 937 */ 938 for (;;) { 939 #ifdef NO_MANUAL_XFER /* XXX */ 940 if (bus_space_read_1(iot, ioh, INTS) != 0) { 941 /* 942 * Target left MESSAGE IN, probably because it 943 * a) noticed our ATN signal, or 944 * b) ran out of messages. 945 */ 946 goto out; 947 } 948 #endif 949 /* If parity error, just dump everything on the floor. */ 950 if ((bus_space_read_1(iot, ioh, SERR) & 951 (SERR_SCSI_PAR|SERR_SPC_PAR)) != 0) { 952 sc->sc_flags |= SPC_DROP_MSGIN; 953 spc_sched_msgout(sc, SEND_PARITY_ERROR); 954 } 955 956 #ifdef NO_MANUAL_XFER /* XXX */ 957 /* send TRANSFER command. */ 958 bus_space_write_1(iot, ioh, TCH, 0); 959 bus_space_write_1(iot, ioh, TCM, 0); 960 bus_space_write_1(iot, ioh, TCL, 1); 961 bus_space_write_1(iot, ioh, PCTL, 962 sc->sc_phase | PCTL_BFINT_ENAB); 963 #ifdef NEED_DREQ_ON_HARDWARE_XFER 964 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); 965 #else 966 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR | SCMD_PROG_XFR); 967 #endif 968 for (;;) { 969 if ((bus_space_read_1(iot, ioh, SSTS) & 970 SSTS_DREG_EMPTY) == 0) 971 break; 972 if (bus_space_read_1(iot, ioh, INTS) != 0) 973 goto out; 974 } 975 msg = bus_space_read_1(iot, ioh, DREG); 976 #else 977 if ((bus_space_read_1(iot, ioh, PSNS) & PSNS_ATN) != 0) 978 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ATN); 979 bus_space_write_1(iot, ioh, PCTL, PCTL_BFINT_ENAB | PH_MSGIN); 980 981 while ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) == 0) { 982 if ((bus_space_read_1(iot, ioh, PSNS) & PH_MASK) 983 != PH_MSGIN || 984 bus_space_read_1(iot, ioh, INTS) != 0) 985 /* 986 * Target left MESSAGE IN, probably because it 987 * a) noticed our ATN signal, or 988 * b) ran out of messages. 989 */ 990 goto out; 991 DELAY(1); /* XXX needs timeout */ 992 } 993 994 msg = bus_space_read_1(iot, ioh, TEMP); 995 #endif 996 997 /* Gather incoming message bytes if needed. */ 998 if ((sc->sc_flags & SPC_DROP_MSGIN) == 0) { 999 if (n >= SPC_MAX_MSG_LEN) { 1000 sc->sc_flags |= SPC_DROP_MSGIN; 1001 spc_sched_msgout(sc, SEND_REJECT); 1002 } else { 1003 *sc->sc_imp++ = msg; 1004 n++; 1005 /* 1006 * This testing is suboptimal, but most 1007 * messages will be of the one byte variety, so 1008 * it should not affect performance 1009 * significantly. 1010 */ 1011 if (n == 1 && MSG_IS1BYTE(sc->sc_imess[0])) 1012 break; 1013 if (n == 2 && MSG_IS2BYTE(sc->sc_imess[0])) 1014 break; 1015 if (n >= 3 && MSG_ISEXTENDED(sc->sc_imess[0]) && 1016 n == sc->sc_imess[1] + 2) 1017 break; 1018 } 1019 } 1020 /* 1021 * If we reach this spot we're either: 1022 * a) in the middle of a multi-byte message, or 1023 * b) dropping bytes. 1024 */ 1025 1026 #ifndef NO_MANUAL_XFER /* XXX */ 1027 /* Ack the last byte read. */ 1028 bus_space_write_1(iot, ioh, SCMD, SCMD_SET_ACK); 1029 while ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) != 0) 1030 DELAY(1); /* XXX needs timeout */ 1031 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ACK); 1032 #endif 1033 } 1034 1035 SPC_MISC(("n=%d imess=0x%02x ", n, sc->sc_imess[0])); 1036 1037 /* We now have a complete message. Parse it. */ 1038 switch (sc->sc_state) { 1039 struct spc_acb *acb; 1040 struct spc_tinfo *ti; 1041 1042 case SPC_CONNECTED: 1043 SPC_ASSERT(sc->sc_nexus != NULL); 1044 acb = sc->sc_nexus; 1045 ti = &sc->sc_tinfo[acb->xs->xs_periph->periph_target]; 1046 1047 switch (sc->sc_imess[0]) { 1048 case MSG_CMDCOMPLETE: 1049 #if 0 1050 if (sc->sc_dleft < 0) { 1051 periph = acb->xs->xs_periph; 1052 printf("%s: %ld extra bytes from %d:%d\n", 1053 sc->sc_dev.dv_xname, (long)-sc->sc_dleft, 1054 periph->periph_target, periph->periph_lun); 1055 sc->sc_dleft = 0; 1056 } 1057 #endif 1058 acb->xs->resid = acb->data_length = sc->sc_dleft; 1059 sc->sc_state = SPC_CMDCOMPLETE; 1060 break; 1061 1062 case MSG_PARITY_ERROR: 1063 /* Resend the last message. */ 1064 spc_sched_msgout(sc, sc->sc_lastmsg); 1065 break; 1066 1067 case MSG_MESSAGE_REJECT: 1068 SPC_MISC(("message rejected %02x ", sc->sc_lastmsg)); 1069 switch (sc->sc_lastmsg) { 1070 #if SPC_USE_SYNCHRONOUS + SPC_USE_WIDE 1071 case SEND_IDENTIFY: 1072 ti->flags &= ~(DO_SYNC | DO_WIDE); 1073 ti->period = ti->offset = 0; 1074 spc_setsync(sc, ti); 1075 ti->width = 0; 1076 break; 1077 #endif 1078 #if SPC_USE_SYNCHRONOUS 1079 case SEND_SDTR: 1080 ti->flags &= ~DO_SYNC; 1081 ti->period = ti->offset = 0; 1082 spc_setsync(sc, ti); 1083 break; 1084 #endif 1085 #if SPC_USE_WIDE 1086 case SEND_WDTR: 1087 ti->flags &= ~DO_WIDE; 1088 ti->width = 0; 1089 break; 1090 #endif 1091 case SEND_INIT_DET_ERR: 1092 spc_sched_msgout(sc, SEND_ABORT); 1093 break; 1094 } 1095 break; 1096 1097 case MSG_NOOP: 1098 break; 1099 1100 case MSG_DISCONNECT: 1101 ti->dconns++; 1102 sc->sc_state = SPC_DISCONNECT; 1103 break; 1104 1105 case MSG_SAVEDATAPOINTER: 1106 acb->data_addr = sc->sc_dp; 1107 acb->data_length = sc->sc_dleft; 1108 break; 1109 1110 case MSG_RESTOREPOINTERS: 1111 sc->sc_dp = acb->data_addr; 1112 sc->sc_dleft = acb->data_length; 1113 sc->sc_cp = (u_char *)&acb->scsipi_cmd; 1114 sc->sc_cleft = acb->scsipi_cmd_length; 1115 break; 1116 1117 case MSG_EXTENDED: 1118 switch (sc->sc_imess[2]) { 1119 #if SPC_USE_SYNCHRONOUS 1120 case MSG_EXT_SDTR: 1121 if (sc->sc_imess[1] != 3) 1122 goto reject; 1123 ti->period = sc->sc_imess[3]; 1124 ti->offset = sc->sc_imess[4]; 1125 ti->flags &= ~DO_SYNC; 1126 if (ti->offset == 0) { 1127 } else if (ti->period < sc->sc_minsync || 1128 ti->period > sc->sc_maxsync || 1129 ti->offset > 8) { 1130 ti->period = ti->offset = 0; 1131 spc_sched_msgout(sc, SEND_SDTR); 1132 } else { 1133 scsipi_printaddr(acb->xs->xs_periph); 1134 printf("sync, offset %d, " 1135 "period %dnsec\n", 1136 ti->offset, ti->period * 4); 1137 } 1138 spc_setsync(sc, ti); 1139 break; 1140 #endif 1141 1142 #if SPC_USE_WIDE 1143 case MSG_EXT_WDTR: 1144 if (sc->sc_imess[1] != 2) 1145 goto reject; 1146 ti->width = sc->sc_imess[3]; 1147 ti->flags &= ~DO_WIDE; 1148 if (ti->width == 0) { 1149 } else if (ti->width > SPC_MAX_WIDTH) { 1150 ti->width = 0; 1151 spc_sched_msgout(sc, SEND_WDTR); 1152 } else { 1153 scsipi_printaddr(acb->xs->xs_periph); 1154 printf("wide, width %d\n", 1155 1 << (3 + ti->width)); 1156 } 1157 break; 1158 #endif 1159 1160 default: 1161 printf("%s: unrecognized MESSAGE EXTENDED; " 1162 "sending REJECT\n", sc->sc_dev.dv_xname); 1163 SPC_BREAK(); 1164 goto reject; 1165 } 1166 break; 1167 1168 default: 1169 printf("%s: unrecognized MESSAGE; sending REJECT\n", 1170 sc->sc_dev.dv_xname); 1171 SPC_BREAK(); 1172 reject: 1173 spc_sched_msgout(sc, SEND_REJECT); 1174 break; 1175 } 1176 break; 1177 1178 case SPC_RESELECTED: 1179 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1180 printf("%s: reselect without IDENTIFY; " 1181 "sending DEVICE RESET\n", sc->sc_dev.dv_xname); 1182 SPC_BREAK(); 1183 goto reset; 1184 } 1185 1186 (void) spc_reselect(sc, sc->sc_imess[0]); 1187 break; 1188 1189 default: 1190 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n", 1191 sc->sc_dev.dv_xname); 1192 SPC_BREAK(); 1193 reset: 1194 spc_sched_msgout(sc, SEND_DEV_RESET); 1195 break; 1196 1197 #ifdef notdef 1198 abort: 1199 spc_sched_msgout(sc, SEND_ABORT); 1200 break; 1201 #endif 1202 } 1203 1204 #ifndef NO_MANUAL_XFER /* XXX */ 1205 /* Ack the last message byte. */ 1206 bus_space_write_1(iot, ioh, SCMD, SCMD_SET_ACK); 1207 while ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) != 0) 1208 DELAY(1); /* XXX needs timeout */ 1209 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ACK); 1210 #endif 1211 1212 /* Go get the next message, if any. */ 1213 goto nextmsg; 1214 1215 out: 1216 #ifdef NO_MANUAL_XFER /* XXX */ 1217 /* Ack the last message byte. */ 1218 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ACK); 1219 #endif 1220 SPC_MISC(("n=%d imess=0x%02x ", n, sc->sc_imess[0])); 1221 } 1222 1223 /* 1224 * Send the highest priority, scheduled message. 1225 */ 1226 void 1227 spc_msgout(struct spc_softc *sc) 1228 { 1229 bus_space_tag_t iot = sc->sc_iot; 1230 bus_space_handle_t ioh = sc->sc_ioh; 1231 #if SPC_USE_SYNCHRONOUS 1232 struct spc_tinfo *ti; 1233 #endif 1234 int n; 1235 1236 SPC_TRACE(("spc_msgout ")); 1237 1238 if (sc->sc_prevphase == PH_MSGOUT) { 1239 if (sc->sc_omp == sc->sc_omess) { 1240 /* 1241 * This is a retransmission. 1242 * 1243 * We get here if the target stayed in MESSAGE OUT 1244 * phase. Section 5.1.9.2 of the SCSI 2 spec indicates 1245 * that all of the previously transmitted messages must 1246 * be sent again, in the same order. Therefore, we 1247 * requeue all the previously transmitted messages, and 1248 * start again from the top. Our simple priority 1249 * scheme keeps the messages in the right order. 1250 */ 1251 SPC_MISC(("retransmitting ")); 1252 sc->sc_msgpriq |= sc->sc_msgoutq; 1253 /* 1254 * Set ATN. If we're just sending a trivial 1-byte 1255 * message, we'll clear ATN later on anyway. 1256 */ 1257 bus_space_write_1(iot, ioh, SCMD, 1258 SCMD_SET_ATN); /* XXX? */ 1259 } else { 1260 /* This is a continuation of the previous message. */ 1261 n = sc->sc_omp - sc->sc_omess; 1262 goto nextbyte; 1263 } 1264 } 1265 1266 /* No messages transmitted so far. */ 1267 sc->sc_msgoutq = 0; 1268 sc->sc_lastmsg = 0; 1269 1270 nextmsg: 1271 /* Pick up highest priority message. */ 1272 sc->sc_currmsg = sc->sc_msgpriq & -sc->sc_msgpriq; 1273 sc->sc_msgpriq &= ~sc->sc_currmsg; 1274 sc->sc_msgoutq |= sc->sc_currmsg; 1275 1276 /* Build the outgoing message data. */ 1277 switch (sc->sc_currmsg) { 1278 case SEND_IDENTIFY: 1279 SPC_ASSERT(sc->sc_nexus != NULL); 1280 sc->sc_omess[0] = 1281 MSG_IDENTIFY(sc->sc_nexus->xs->xs_periph->periph_lun, 1); 1282 n = 1; 1283 break; 1284 1285 #if SPC_USE_SYNCHRONOUS 1286 case SEND_SDTR: 1287 SPC_ASSERT(sc->sc_nexus != NULL); 1288 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target]; 1289 sc->sc_omess[4] = MSG_EXTENDED; 1290 sc->sc_omess[3] = MSG_EXT_SDTR_LEN; 1291 sc->sc_omess[2] = MSG_EXT_SDTR; 1292 sc->sc_omess[1] = ti->period >> 2; 1293 sc->sc_omess[0] = ti->offset; 1294 n = 5; 1295 break; 1296 #endif 1297 1298 #if SPC_USE_WIDE 1299 case SEND_WDTR: 1300 SPC_ASSERT(sc->sc_nexus != NULL); 1301 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target]; 1302 sc->sc_omess[3] = MSG_EXTENDED; 1303 sc->sc_omess[2] = MSG_EXT_WDTR_LEN; 1304 sc->sc_omess[1] = MSG_EXT_WDTR; 1305 sc->sc_omess[0] = ti->width; 1306 n = 4; 1307 break; 1308 #endif 1309 1310 case SEND_DEV_RESET: 1311 sc->sc_flags |= SPC_ABORTING; 1312 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1313 n = 1; 1314 break; 1315 1316 case SEND_REJECT: 1317 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1318 n = 1; 1319 break; 1320 1321 case SEND_PARITY_ERROR: 1322 sc->sc_omess[0] = MSG_PARITY_ERROR; 1323 n = 1; 1324 break; 1325 1326 case SEND_INIT_DET_ERR: 1327 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1328 n = 1; 1329 break; 1330 1331 case SEND_ABORT: 1332 sc->sc_flags |= SPC_ABORTING; 1333 sc->sc_omess[0] = MSG_ABORT; 1334 n = 1; 1335 break; 1336 1337 default: 1338 printf("%s: unexpected MESSAGE OUT; sending NOOP\n", 1339 sc->sc_dev.dv_xname); 1340 SPC_BREAK(); 1341 sc->sc_omess[0] = MSG_NOOP; 1342 n = 1; 1343 break; 1344 } 1345 sc->sc_omp = &sc->sc_omess[n]; 1346 1347 nextbyte: 1348 /* Send message bytes. */ 1349 /* send TRANSFER command. */ 1350 bus_space_write_1(iot, ioh, TCH, n >> 16); 1351 bus_space_write_1(iot, ioh, TCM, n >> 8); 1352 bus_space_write_1(iot, ioh, TCL, n); 1353 bus_space_write_1(iot, ioh, PCTL, sc->sc_phase | PCTL_BFINT_ENAB); 1354 #ifdef NEED_DREQ_ON_HARDWARE_XFER 1355 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); /* XXX */ 1356 #else 1357 bus_space_write_1(iot, ioh, SCMD, 1358 SCMD_XFR | SCMD_PROG_XFR); 1359 #endif 1360 for (;;) { 1361 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_BUSY) != 0) 1362 break; 1363 if (bus_space_read_1(iot, ioh, INTS) != 0) 1364 goto out; 1365 } 1366 for (;;) { 1367 #if 0 1368 for (;;) { 1369 if ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) != 0) 1370 break; 1371 /* Wait for REQINIT. XXX Need timeout. */ 1372 } 1373 #endif 1374 if (bus_space_read_1(iot, ioh, INTS) != 0) { 1375 /* 1376 * Target left MESSAGE OUT, possibly to reject 1377 * our message. 1378 * 1379 * If this is the last message being sent, then we 1380 * deassert ATN, since either the target is going to 1381 * ignore this message, or it's going to ask for a 1382 * retransmission via MESSAGE PARITY ERROR (in which 1383 * case we reassert ATN anyway). 1384 */ 1385 #if 0 1386 if (sc->sc_msgpriq == 0) 1387 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ATN); 1388 #endif 1389 goto out; 1390 } 1391 1392 #if 0 1393 /* Clear ATN before last byte if this is the last message. */ 1394 if (n == 1 && sc->sc_msgpriq == 0) 1395 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ATN); 1396 #endif 1397 1398 while ((bus_space_read_1(iot, ioh, SSTS) & SSTS_DREG_FULL) != 0) 1399 DELAY(1); 1400 /* Send message byte. */ 1401 bus_space_write_1(iot, ioh, DREG, *--sc->sc_omp); 1402 --n; 1403 /* Keep track of the last message we've sent any bytes of. */ 1404 sc->sc_lastmsg = sc->sc_currmsg; 1405 #if 0 1406 /* Wait for ACK to be negated. XXX Need timeout. */ 1407 while ((bus_space_read_1(iot, ioh, PSNS) & ACKI) != 0) 1408 ; 1409 #endif 1410 1411 if (n == 0) 1412 break; 1413 } 1414 1415 /* We get here only if the entire message has been transmitted. */ 1416 if (sc->sc_msgpriq != 0) { 1417 /* There are more outgoing messages. */ 1418 goto nextmsg; 1419 } 1420 1421 /* 1422 * The last message has been transmitted. We need to remember the last 1423 * message transmitted (in case the target switches to MESSAGE IN phase 1424 * and sends a MESSAGE REJECT), and the list of messages transmitted 1425 * this time around (in case the target stays in MESSAGE OUT phase to 1426 * request a retransmit). 1427 */ 1428 1429 out: 1430 /* Disable REQ/ACK protocol. */ 1431 return; 1432 } 1433 1434 /* 1435 * spc_dataout_pio: perform a data transfer using the FIFO datapath in the spc 1436 * Precondition: The SCSI bus should be in the DOUT phase, with REQ asserted 1437 * and ACK deasserted (i.e. waiting for a data byte) 1438 * 1439 * This new revision has been optimized (I tried) to make the common case fast, 1440 * and the rarer cases (as a result) somewhat more comlex 1441 */ 1442 int 1443 spc_dataout_pio(struct spc_softc *sc, u_char *p, int n) 1444 { 1445 bus_space_tag_t iot = sc->sc_iot; 1446 bus_space_handle_t ioh = sc->sc_ioh; 1447 u_char intstat = 0; 1448 int out = 0; 1449 #define DOUTAMOUNT 8 /* Full FIFO */ 1450 1451 SPC_TRACE(("spc_dataout_pio ")); 1452 /* send TRANSFER command. */ 1453 bus_space_write_1(iot, ioh, TCH, n >> 16); 1454 bus_space_write_1(iot, ioh, TCM, n >> 8); 1455 bus_space_write_1(iot, ioh, TCL, n); 1456 bus_space_write_1(iot, ioh, PCTL, sc->sc_phase | PCTL_BFINT_ENAB); 1457 #ifdef NEED_DREQ_ON_HARDWARE_XFER 1458 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); /* XXX */ 1459 #else 1460 bus_space_write_1(iot, ioh, SCMD, 1461 SCMD_XFR | SCMD_PROG_XFR); /* XXX */ 1462 #endif 1463 for (;;) { 1464 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_BUSY) != 0) 1465 break; 1466 if (bus_space_read_1(iot, ioh, INTS) != 0) 1467 break; 1468 } 1469 1470 /* 1471 * I have tried to make the main loop as tight as possible. This 1472 * means that some of the code following the loop is a bit more 1473 * complex than otherwise. 1474 */ 1475 while (n > 0) { 1476 int xfer; 1477 1478 for (;;) { 1479 intstat = bus_space_read_1(iot, ioh, INTS); 1480 /* Wait till buffer is empty. */ 1481 if ((bus_space_read_1(iot, ioh, SSTS) & 1482 SSTS_DREG_EMPTY) != 0) 1483 break; 1484 /* Break on interrupt. */ 1485 if (intstat != 0) 1486 goto phasechange; 1487 DELAY(1); 1488 } 1489 1490 xfer = min(DOUTAMOUNT, n); 1491 1492 SPC_MISC(("%d> ", xfer)); 1493 1494 n -= xfer; 1495 out += xfer; 1496 1497 bus_space_write_multi_1(iot, ioh, DREG, p, xfer); 1498 p += xfer; 1499 } 1500 1501 if (out == 0) { 1502 for (;;) { 1503 if (bus_space_read_1(iot, ioh, INTS) != 0) 1504 break; 1505 DELAY(1); 1506 } 1507 SPC_MISC(("extra data ")); 1508 } else { 1509 /* See the bytes off chip */ 1510 for (;;) { 1511 /* Wait till buffer is empty. */ 1512 if ((bus_space_read_1(iot, ioh, SSTS) & 1513 SSTS_DREG_EMPTY) != 0) 1514 break; 1515 intstat = bus_space_read_1(iot, ioh, INTS); 1516 /* Break on interrupt. */ 1517 if (intstat != 0) 1518 goto phasechange; 1519 DELAY(1); 1520 } 1521 } 1522 1523 phasechange: 1524 /* Stop the FIFO data path. */ 1525 1526 if (intstat != 0) { 1527 /* Some sort of phase change. */ 1528 int amount; 1529 1530 amount = (bus_space_read_1(iot, ioh, TCH) << 16) | 1531 (bus_space_read_1(iot, ioh, TCM) << 8) | 1532 bus_space_read_1(iot, ioh, TCL); 1533 if (amount > 0) { 1534 out -= amount; 1535 SPC_MISC(("+%d ", amount)); 1536 } 1537 } 1538 1539 return out; 1540 } 1541 1542 /* 1543 * spc_datain_pio: perform data transfers using the FIFO datapath in the spc 1544 * Precondition: The SCSI bus should be in the DIN phase, with REQ asserted 1545 * and ACK deasserted (i.e. at least one byte is ready). 1546 * 1547 * For now, uses a pretty dumb algorithm, hangs around until all data has been 1548 * transferred. This, is OK for fast targets, but not so smart for slow 1549 * targets which don't disconnect or for huge transfers. 1550 */ 1551 int 1552 spc_datain_pio(struct spc_softc *sc, u_char *p, int n) 1553 { 1554 bus_space_tag_t iot = sc->sc_iot; 1555 bus_space_handle_t ioh = sc->sc_ioh; 1556 int in = 0; 1557 uint8_t intstat, sstat; 1558 #define DINAMOUNT 8 /* Full FIFO */ 1559 1560 SPC_TRACE(("spc_datain_pio ")); 1561 /* send TRANSFER command. */ 1562 bus_space_write_1(iot, ioh, TCH, n >> 16); 1563 bus_space_write_1(iot, ioh, TCM, n >> 8); 1564 bus_space_write_1(iot, ioh, TCL, n); 1565 bus_space_write_1(iot, ioh, PCTL, sc->sc_phase | PCTL_BFINT_ENAB); 1566 #ifdef NEED_DREQ_ON_HARDWARE_XFER 1567 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); /* XXX */ 1568 #else 1569 bus_space_write_1(iot, ioh, SCMD, 1570 SCMD_XFR | SCMD_PROG_XFR); /* XXX */ 1571 #endif 1572 1573 /* 1574 * We leave this loop if one or more of the following is true: 1575 * a) phase != PH_DATAIN && FIFOs are empty 1576 * b) reset has occurred or busfree is detected. 1577 */ 1578 intstat = 0; 1579 while (n > 0) { 1580 sstat = bus_space_read_1(iot, ioh, SSTS); 1581 if ((sstat & SSTS_DREG_FULL) != 0) { 1582 n -= DINAMOUNT; 1583 in += DINAMOUNT; 1584 bus_space_read_multi_1(iot, ioh, DREG, p, DINAMOUNT); 1585 p += DINAMOUNT; 1586 } else if ((sstat & SSTS_DREG_EMPTY) == 0) { 1587 n--; 1588 in++; 1589 *p++ = bus_space_read_1(iot, ioh, DREG); 1590 } else { 1591 if (intstat != 0) 1592 goto phasechange; 1593 intstat = bus_space_read_1(iot, ioh, INTS); 1594 } 1595 } 1596 1597 /* 1598 * Some SCSI-devices are rude enough to transfer more data than what 1599 * was requested, e.g. 2048 bytes from a CD-ROM instead of the 1600 * requested 512. Test for progress, i.e. real transfers. If no real 1601 * transfers have been performed (n is probably already zero) and the 1602 * FIFO is not empty, waste some bytes.... 1603 */ 1604 if (in == 0) { 1605 for (;;) { 1606 sstat = bus_space_read_1(iot, ioh, SSTS); 1607 if ((sstat & SSTS_DREG_EMPTY) == 0) { 1608 (void) bus_space_read_1(iot, ioh, DREG); 1609 } else { 1610 if (intstat != 0) 1611 goto phasechange; 1612 intstat = bus_space_read_1(iot, ioh, INTS); 1613 } 1614 DELAY(1); 1615 } 1616 SPC_MISC(("extra data ")); 1617 } 1618 1619 phasechange: 1620 /* Stop the FIFO data path. */ 1621 1622 return in; 1623 } 1624 1625 /* 1626 * Catch an interrupt from the adaptor 1627 */ 1628 /* 1629 * This is the workhorse routine of the driver. 1630 * Deficiencies (for now): 1631 * 1) always uses programmed I/O 1632 */ 1633 int 1634 spc_intr(void *arg) 1635 { 1636 struct spc_softc *sc = arg; 1637 bus_space_tag_t iot = sc->sc_iot; 1638 bus_space_handle_t ioh = sc->sc_ioh; 1639 u_char ints; 1640 struct spc_acb *acb; 1641 struct scsipi_periph *periph; 1642 struct spc_tinfo *ti; 1643 int n; 1644 1645 SPC_TRACE(("spc_intr ")); 1646 1647 ints = bus_space_read_1(iot, ioh, INTS); 1648 if (ints == 0) 1649 return 0; 1650 1651 /* 1652 * Disable interrupt. 1653 */ 1654 bus_space_write_1(iot, ioh, SCTL, 1655 bus_space_read_1(iot, ioh, SCTL) & ~SCTL_INTR_ENAB); 1656 1657 if (sc->sc_dma_done != NULL && 1658 sc->sc_state == SPC_CONNECTED && 1659 (sc->sc_flags & SPC_DOINGDMA) != 0 && 1660 (sc->sc_phase == PH_DATAOUT || sc->sc_phase == PH_DATAIN)) { 1661 (*sc->sc_dma_done)(sc); 1662 } 1663 1664 loop: 1665 /* 1666 * Loop until transfer completion. 1667 */ 1668 /* 1669 * First check for abnormal conditions, such as reset. 1670 */ 1671 ints = bus_space_read_1(iot, ioh, INTS); 1672 SPC_MISC(("ints = 0x%x ", ints)); 1673 1674 if ((ints & INTS_RST) != 0) { 1675 printf("%s: SCSI bus reset\n", sc->sc_dev.dv_xname); 1676 goto reset; 1677 } 1678 1679 /* 1680 * Check for less serious errors. 1681 */ 1682 if ((bus_space_read_1(iot, ioh, SERR) & (SERR_SCSI_PAR|SERR_SPC_PAR)) 1683 != 0) { 1684 printf("%s: SCSI bus parity error\n", sc->sc_dev.dv_xname); 1685 if (sc->sc_prevphase == PH_MSGIN) { 1686 sc->sc_flags |= SPC_DROP_MSGIN; 1687 spc_sched_msgout(sc, SEND_PARITY_ERROR); 1688 } else 1689 spc_sched_msgout(sc, SEND_INIT_DET_ERR); 1690 } 1691 1692 /* 1693 * If we're not already busy doing something test for the following 1694 * conditions: 1695 * 1) We have been reselected by something 1696 * 2) We have selected something successfully 1697 * 3) Our selection process has timed out 1698 * 4) This is really a bus free interrupt just to get a new command 1699 * going? 1700 * 5) Spurious interrupt? 1701 */ 1702 switch (sc->sc_state) { 1703 case SPC_IDLE: 1704 case SPC_SELECTING: 1705 SPC_MISC(("ints:0x%02x ", ints)); 1706 1707 if ((ints & INTS_SEL) != 0) { 1708 /* 1709 * We don't currently support target mode. 1710 */ 1711 printf("%s: target mode selected; going to BUS FREE\n", 1712 sc->sc_dev.dv_xname); 1713 1714 goto sched; 1715 } else if ((ints & INTS_RESEL) != 0) { 1716 SPC_MISC(("reselected ")); 1717 1718 /* 1719 * If we're trying to select a target ourselves, 1720 * push our command back into the ready list. 1721 */ 1722 if (sc->sc_state == SPC_SELECTING) { 1723 SPC_MISC(("backoff selector ")); 1724 SPC_ASSERT(sc->sc_nexus != NULL); 1725 acb = sc->sc_nexus; 1726 sc->sc_nexus = NULL; 1727 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 1728 } 1729 1730 /* Save reselection ID. */ 1731 sc->sc_selid = bus_space_read_1(iot, ioh, TEMP); 1732 1733 sc->sc_state = SPC_RESELECTED; 1734 } else if ((ints & INTS_CMD_DONE) != 0) { 1735 SPC_MISC(("selected ")); 1736 1737 /* 1738 * We have selected a target. Things to do: 1739 * a) Determine what message(s) to send. 1740 * b) Verify that we're still selecting the target. 1741 * c) Mark device as busy. 1742 */ 1743 if (sc->sc_state != SPC_SELECTING) { 1744 printf("%s: selection out while idle; " 1745 "resetting\n", sc->sc_dev.dv_xname); 1746 SPC_BREAK(); 1747 goto reset; 1748 } 1749 SPC_ASSERT(sc->sc_nexus != NULL); 1750 acb = sc->sc_nexus; 1751 periph = acb->xs->xs_periph; 1752 ti = &sc->sc_tinfo[periph->periph_target]; 1753 1754 sc->sc_msgpriq = SEND_IDENTIFY; 1755 if (acb->flags & ACB_RESET) 1756 sc->sc_msgpriq |= SEND_DEV_RESET; 1757 else if (acb->flags & ACB_ABORT) 1758 sc->sc_msgpriq |= SEND_ABORT; 1759 else { 1760 #if SPC_USE_SYNCHRONOUS 1761 if ((ti->flags & DO_SYNC) != 0) 1762 sc->sc_msgpriq |= SEND_SDTR; 1763 #endif 1764 #if SPC_USE_WIDE 1765 if ((ti->flags & DO_WIDE) != 0) 1766 sc->sc_msgpriq |= SEND_WDTR; 1767 #endif 1768 } 1769 1770 acb->flags |= ACB_NEXUS; 1771 ti->lubusy |= (1 << periph->periph_lun); 1772 1773 /* Do an implicit RESTORE POINTERS. */ 1774 sc->sc_dp = acb->data_addr; 1775 sc->sc_dleft = acb->data_length; 1776 sc->sc_cp = (u_char *)&acb->scsipi_cmd; 1777 sc->sc_cleft = acb->scsipi_cmd_length; 1778 1779 /* On our first connection, schedule a timeout. */ 1780 if ((acb->xs->xs_control & XS_CTL_POLL) == 0) 1781 callout_reset(&acb->xs->xs_callout, 1782 mstohz(acb->timeout), spc_timeout, acb); 1783 1784 sc->sc_state = SPC_CONNECTED; 1785 } else if ((ints & INTS_TIMEOUT) != 0) { 1786 SPC_MISC(("selection timeout ")); 1787 1788 if (sc->sc_state != SPC_SELECTING) { 1789 printf("%s: selection timeout while idle; " 1790 "resetting\n", sc->sc_dev.dv_xname); 1791 SPC_BREAK(); 1792 goto reset; 1793 } 1794 SPC_ASSERT(sc->sc_nexus != NULL); 1795 acb = sc->sc_nexus; 1796 1797 delay(250); 1798 1799 acb->xs->error = XS_SELTIMEOUT; 1800 goto finish; 1801 } else { 1802 if (sc->sc_state != SPC_IDLE) { 1803 printf("%s: BUS FREE while not idle; " 1804 "state=%d\n", 1805 sc->sc_dev.dv_xname, sc->sc_state); 1806 SPC_BREAK(); 1807 goto out; 1808 } 1809 1810 goto sched; 1811 } 1812 1813 /* 1814 * Turn off selection stuff, and prepare to catch bus free 1815 * interrupts, parity errors, and phase changes. 1816 */ 1817 1818 sc->sc_flags = 0; 1819 sc->sc_prevphase = PH_INVALID; 1820 goto dophase; 1821 } 1822 1823 if ((ints & INTS_DISCON) != 0) { 1824 /* We've gone to BUS FREE phase. */ 1825 /* disable disconnect interrupt */ 1826 bus_space_write_1(iot, ioh, PCTL, 1827 bus_space_read_1(iot, ioh, PCTL) & ~PCTL_BFINT_ENAB); 1828 /* XXX reset interrput */ 1829 bus_space_write_1(iot, ioh, INTS, ints); 1830 1831 switch (sc->sc_state) { 1832 case SPC_RESELECTED: 1833 goto sched; 1834 1835 case SPC_CONNECTED: 1836 SPC_ASSERT(sc->sc_nexus != NULL); 1837 acb = sc->sc_nexus; 1838 1839 #if SPC_USE_SYNCHRONOUS + SPC_USE_WIDE 1840 if (sc->sc_prevphase == PH_MSGOUT) { 1841 /* 1842 * If the target went to BUS FREE phase during 1843 * or immediately after sending a SDTR or WDTR 1844 * message, disable negotiation. 1845 */ 1846 periph = acb->xs->xs_periph; 1847 ti = &sc->sc_tinfo[periph->periph_target]; 1848 switch (sc->sc_lastmsg) { 1849 #if SPC_USE_SYNCHRONOUS 1850 case SEND_SDTR: 1851 ti->flags &= ~DO_SYNC; 1852 ti->period = ti->offset = 0; 1853 break; 1854 #endif 1855 #if SPC_USE_WIDE 1856 case SEND_WDTR: 1857 ti->flags &= ~DO_WIDE; 1858 ti->width = 0; 1859 break; 1860 #endif 1861 } 1862 } 1863 #endif 1864 1865 if ((sc->sc_flags & SPC_ABORTING) == 0) { 1866 /* 1867 * Section 5.1.1 of the SCSI 2 spec suggests 1868 * issuing a REQUEST SENSE following an 1869 * unexpected disconnect. Some devices go into 1870 * a contingent allegiance condition when 1871 * disconnecting, and this is necessary to 1872 * clean up their state. 1873 */ 1874 printf("%s: unexpected disconnect; " 1875 "sending REQUEST SENSE\n", 1876 sc->sc_dev.dv_xname); 1877 SPC_BREAK(); 1878 acb->target_stat = SCSI_CHECK; 1879 acb->xs->error = XS_NOERROR; 1880 goto finish; 1881 } 1882 1883 acb->xs->error = XS_DRIVER_STUFFUP; 1884 goto finish; 1885 1886 case SPC_DISCONNECT: 1887 SPC_ASSERT(sc->sc_nexus != NULL); 1888 acb = sc->sc_nexus; 1889 TAILQ_INSERT_HEAD(&sc->nexus_list, acb, chain); 1890 sc->sc_nexus = NULL; 1891 goto sched; 1892 1893 case SPC_CMDCOMPLETE: 1894 SPC_ASSERT(sc->sc_nexus != NULL); 1895 acb = sc->sc_nexus; 1896 goto finish; 1897 } 1898 } 1899 else if ((ints & INTS_CMD_DONE) != 0 && 1900 sc->sc_prevphase == PH_MSGIN && 1901 sc->sc_state != SPC_CONNECTED) 1902 goto out; 1903 1904 dophase: 1905 #if 0 1906 if ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) == 0) { 1907 /* Wait for REQINIT. */ 1908 goto out; 1909 } 1910 #else 1911 bus_space_write_1(iot, ioh, INTS, ints); 1912 ints = 0; 1913 while ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) == 0) 1914 delay(1); /* need timeout XXX */ 1915 #endif 1916 1917 /* 1918 * State transition. 1919 */ 1920 sc->sc_phase = bus_space_read_1(iot, ioh, PSNS) & PH_MASK; 1921 #if 0 1922 bus_space_write_1(iot, ioh, PCTL, sc->sc_phase); 1923 #endif 1924 1925 SPC_MISC(("phase=%d\n", sc->sc_phase)); 1926 switch (sc->sc_phase) { 1927 case PH_MSGOUT: 1928 if (sc->sc_state != SPC_CONNECTED && 1929 sc->sc_state != SPC_RESELECTED) 1930 break; 1931 spc_msgout(sc); 1932 sc->sc_prevphase = PH_MSGOUT; 1933 goto loop; 1934 1935 case PH_MSGIN: 1936 if (sc->sc_state != SPC_CONNECTED && 1937 sc->sc_state != SPC_RESELECTED) 1938 break; 1939 spc_msgin(sc); 1940 sc->sc_prevphase = PH_MSGIN; 1941 goto loop; 1942 1943 case PH_CMD: 1944 if (sc->sc_state != SPC_CONNECTED) 1945 break; 1946 #if SPC_DEBUG 1947 if ((spc_debug & SPC_SHOWMISC) != 0) { 1948 SPC_ASSERT(sc->sc_nexus != NULL); 1949 acb = sc->sc_nexus; 1950 printf("cmd=0x%02x+%d ", 1951 acb->scsipi_cmd.opcode, acb->scsipi_cmd_length - 1); 1952 } 1953 #endif 1954 n = spc_dataout_pio(sc, sc->sc_cp, sc->sc_cleft); 1955 sc->sc_cp += n; 1956 sc->sc_cleft -= n; 1957 sc->sc_prevphase = PH_CMD; 1958 goto loop; 1959 1960 case PH_DATAOUT: 1961 if (sc->sc_state != SPC_CONNECTED) 1962 break; 1963 SPC_MISC(("dataout dleft=%d ", sc->sc_dleft)); 1964 if (sc->sc_dma_start != NULL && 1965 sc->sc_dleft > SPC_MIN_DMA_LEN) { 1966 (*sc->sc_dma_start)(sc, sc->sc_dp, sc->sc_dleft, 0); 1967 sc->sc_prevphase = PH_DATAOUT; 1968 goto out; 1969 } 1970 n = spc_dataout_pio(sc, sc->sc_dp, sc->sc_dleft); 1971 sc->sc_dp += n; 1972 sc->sc_dleft -= n; 1973 sc->sc_prevphase = PH_DATAOUT; 1974 goto loop; 1975 1976 case PH_DATAIN: 1977 if (sc->sc_state != SPC_CONNECTED) 1978 break; 1979 SPC_MISC(("datain ")); 1980 if (sc->sc_dma_start != NULL && 1981 sc->sc_dleft > SPC_MIN_DMA_LEN) { 1982 (*sc->sc_dma_start)(sc, sc->sc_dp, sc->sc_dleft, 1); 1983 sc->sc_prevphase = PH_DATAIN; 1984 goto out; 1985 } 1986 n = spc_datain_pio(sc, sc->sc_dp, sc->sc_dleft); 1987 sc->sc_dp += n; 1988 sc->sc_dleft -= n; 1989 sc->sc_prevphase = PH_DATAIN; 1990 goto loop; 1991 1992 case PH_STAT: 1993 if (sc->sc_state != SPC_CONNECTED) 1994 break; 1995 SPC_ASSERT(sc->sc_nexus != NULL); 1996 acb = sc->sc_nexus; 1997 1998 if ((bus_space_read_1(iot, ioh, PSNS) & PSNS_ATN) != 0) 1999 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ATN); 2000 bus_space_write_1(iot, ioh, PCTL, PCTL_BFINT_ENAB | PH_STAT); 2001 while ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) == 0) 2002 DELAY(1); /* XXX needs timeout */ 2003 acb->target_stat = bus_space_read_1(iot, ioh, TEMP); 2004 bus_space_write_1(iot, ioh, SCMD, SCMD_SET_ACK); 2005 while ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) != 0) 2006 DELAY(1); /* XXX needs timeout */ 2007 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ACK); 2008 2009 SPC_MISC(("target_stat=0x%02x ", acb->target_stat)); 2010 sc->sc_prevphase = PH_STAT; 2011 goto loop; 2012 } 2013 2014 printf("%s: unexpected bus phase; resetting\n", sc->sc_dev.dv_xname); 2015 SPC_BREAK(); 2016 reset: 2017 spc_init(sc, 1); 2018 return 1; 2019 2020 finish: 2021 callout_stop(&acb->xs->xs_callout); 2022 bus_space_write_1(iot, ioh, INTS, ints); 2023 ints = 0; 2024 spc_done(sc, acb); 2025 goto out; 2026 2027 sched: 2028 sc->sc_state = SPC_IDLE; 2029 spc_sched(sc); 2030 goto out; 2031 2032 out: 2033 if (ints) 2034 bus_space_write_1(iot, ioh, INTS, ints); 2035 bus_space_write_1(iot, ioh, SCTL, 2036 bus_space_read_1(iot, ioh, SCTL) | SCTL_INTR_ENAB); 2037 return 1; 2038 } 2039 2040 void 2041 spc_abort(struct spc_softc *sc, struct spc_acb *acb) 2042 { 2043 2044 /* 2 secs for the abort */ 2045 acb->timeout = SPC_ABORT_TIMEOUT; 2046 acb->flags |= ACB_ABORT; 2047 2048 if (acb == sc->sc_nexus) { 2049 /* 2050 * If we're still selecting, the message will be scheduled 2051 * after selection is complete. 2052 */ 2053 if (sc->sc_state == SPC_CONNECTED) 2054 spc_sched_msgout(sc, SEND_ABORT); 2055 } else { 2056 spc_dequeue(sc, acb); 2057 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 2058 if (sc->sc_state == SPC_IDLE) 2059 spc_sched(sc); 2060 } 2061 } 2062 2063 void 2064 spc_timeout(void *arg) 2065 { 2066 struct spc_acb *acb = arg; 2067 struct scsipi_xfer *xs = acb->xs; 2068 struct scsipi_periph *periph = xs->xs_periph; 2069 struct spc_softc *sc; 2070 int s; 2071 2072 sc = (void *)periph->periph_channel->chan_adapter->adapt_dev; 2073 scsipi_printaddr(periph); 2074 printf("timed out"); 2075 2076 s = splbio(); 2077 2078 if (acb->flags & ACB_ABORT) { 2079 /* abort timed out */ 2080 printf(" AGAIN\n"); 2081 /* XXX Must reset! */ 2082 } else { 2083 /* abort the operation that has timed out */ 2084 printf("\n"); 2085 acb->xs->error = XS_TIMEOUT; 2086 spc_abort(sc, acb); 2087 } 2088 2089 splx(s); 2090 } 2091 2092 #ifdef SPC_DEBUG 2093 /* 2094 * The following functions are mostly used for debugging purposes, either 2095 * directly called from the driver or from the kernel debugger. 2096 */ 2097 2098 void 2099 spc_show_scsi_cmd(struct spc_acb *acb) 2100 { 2101 u_char *b = (u_char *)&acb->scsipi_cmd; 2102 int i; 2103 2104 scsipi_printaddr(acb->xs->xs_periph); 2105 if ((acb->xs->xs_control & XS_CTL_RESET) == 0) { 2106 for (i = 0; i < acb->scsipi_cmd_length; i++) { 2107 if (i) 2108 printf(","); 2109 printf("%x", b[i]); 2110 } 2111 printf("\n"); 2112 } else 2113 printf("RESET\n"); 2114 } 2115 2116 void 2117 spc_print_acb(struct spc_acb *acb) 2118 { 2119 2120 printf("acb@%p xs=%p flags=%x", acb, acb->xs, acb->flags); 2121 printf(" dp=%p dleft=%d target_stat=%x\n", 2122 acb->data_addr, acb->data_length, acb->target_stat); 2123 spc_show_scsi_cmd(acb); 2124 } 2125 2126 void 2127 spc_print_active_acb(void) 2128 { 2129 struct spc_acb *acb; 2130 struct spc_softc *sc = spc_cd.cd_devs[0]; /* XXX */ 2131 2132 printf("ready list:\n"); 2133 TAILQ_FOREACH(acb, &sc->ready_list, chain) 2134 spc_print_acb(acb); 2135 printf("nexus:\n"); 2136 if (sc->sc_nexus != NULL) 2137 spc_print_acb(sc->sc_nexus); 2138 printf("nexus list:\n"); 2139 TAILQ_FOREACH(acb, &sc->nexus_list, chain) 2140 spc_print_acb(acb); 2141 } 2142 2143 void 2144 spc_dump89352(struct spc_softc *sc) 2145 { 2146 bus_space_tag_t iot = sc->sc_iot; 2147 bus_space_handle_t ioh = sc->sc_ioh; 2148 2149 printf("mb89352: BDID=%x SCTL=%x SCMD=%x TMOD=%x\n", 2150 bus_space_read_1(iot, ioh, BDID), 2151 bus_space_read_1(iot, ioh, SCTL), 2152 bus_space_read_1(iot, ioh, SCMD), 2153 bus_space_read_1(iot, ioh, TMOD)); 2154 printf(" INTS=%x PSNS=%x SSTS=%x SERR=%x PCTL=%x\n", 2155 bus_space_read_1(iot, ioh, INTS), 2156 bus_space_read_1(iot, ioh, PSNS), 2157 bus_space_read_1(iot, ioh, SSTS), 2158 bus_space_read_1(iot, ioh, SERR), 2159 bus_space_read_1(iot, ioh, PCTL)); 2160 printf(" MBC=%x DREG=%x TEMP=%x TCH=%x TCM=%x\n", 2161 bus_space_read_1(iot, ioh, MBC), 2162 #if 0 2163 bus_space_read_1(iot, ioh, DREG), 2164 #else 2165 0, 2166 #endif 2167 bus_space_read_1(iot, ioh, TEMP), 2168 bus_space_read_1(iot, ioh, TCH), 2169 bus_space_read_1(iot, ioh, TCM)); 2170 printf(" TCL=%x EXBF=%x\n", 2171 bus_space_read_1(iot, ioh, TCL), 2172 bus_space_read_1(iot, ioh, EXBF)); 2173 } 2174 2175 void 2176 spc_dump_driver(struct spc_softc *sc) 2177 { 2178 struct spc_tinfo *ti; 2179 int i; 2180 2181 printf("nexus=%p prevphase=%x\n", sc->sc_nexus, sc->sc_prevphase); 2182 printf("state=%x msgin=%x msgpriq=%x msgoutq=%x lastmsg=%x " 2183 "currmsg=%x\n", sc->sc_state, sc->sc_imess[0], 2184 sc->sc_msgpriq, sc->sc_msgoutq, sc->sc_lastmsg, sc->sc_currmsg); 2185 for (i = 0; i < 7; i++) { 2186 ti = &sc->sc_tinfo[i]; 2187 printf("tinfo%d: %d cmds %d disconnects %d timeouts", 2188 i, ti->cmds, ti->dconns, ti->touts); 2189 printf(" %d senses flags=%x\n", ti->senses, ti->flags); 2190 } 2191 } 2192 #endif
Cache object: 94e75cc430662c79e84a89aeecf90f29
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