1 /* $NetBSD: mc68450reg.h,v 1.4 2005/12/11 12:21:27 christos Exp $ */
2
3 /*-
4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Minoura Makoto.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 /*
40 * Motorola MC68450 DMAC register definition.
41 */
42
43 #define DMAC_NCHAN 4 /* Number of channels */
44 #define DMAC_CHAN_SIZE 0x40 /* I/O area size per channes */
45
46 /* register location per channel */
47 #define DMAC_REG_CSR 0x00 /* Channel Status Register */
48 #define DMAC_REG_CER 0x01 /* Channel Error Register */
49 #define DMAC_REG_DCR 0x04 /* Device Control Register */
50 #define DMAC_REG_OCR 0x05 /* Operation Control Register */
51 #define DMAC_REG_SCR 0x06 /* Sequence Control Register */
52 #define DMAC_REG_CCR 0x07 /* Channel Control Register */
53 #define DMAC_REG_MTCR 0x0a /* Memory Transfer Count Register */
54 #define DMAC_REG_MAR 0x0c /* Memory Address Register */
55 #define DMAC_REG_DAR 0x14 /* Device Address Register */
56 #define DMAC_REG_BTCR 0x1a /* Base Transfer Count Register */
57 #define DMAC_REG_BAR 0x1c /* Base Address Register */
58 #define DMAC_REG_NIVR 0x25 /* Normal Interrupt Vector Register */
59 #define DMAC_REG_EIVR 0x27 /* Error Interrupt Vector Register */
60 #define DMAC_REG_MFCR 0x29 /* Memory Function Code Register */
61 #define DMAC_REG_CPR 0x2d /* Channel Priority Register */
62 #define DMAC_REG_DFCR 0x31 /* Device Function Code Register */
63 #define DMAC_REG_BFCR 0x39 /* Base Function Code Register */
64 #define DMAC_REG_GCR 0x3f /* General Control Register */
65
66 /* CSR bits */
67 #define DMAC_CSR_COC 0x80 /* Channel Operation Complete */
68 #define DMAC_CSR_BTC 0x40 /* Block Transfer Complete */
69 #define DMAC_CSR_NDT 0x20 /* Normal Device Termination */
70 #define DMAC_CSR_ERR 0x10 /* Error */
71 #define DMAC_CSR_ACT 0x08 /* Channel Active */
72 #define DMAC_CSR_PCT 0x02 /* PCL Transition */
73 #define DMAC_CSR_PCS 0x01 /* PCL Level */
74
75 /* CER meanings */
76 /*
77 * 0x00: No error
78 * 0x01: Configuration error
79 * 0x02: Operation timing error
80 * 0x05: Address error in memory transfer
81 * 0x06: Address error in device transfer
82 * 0x07: Address error in base address reading
83 * 0x09: Bus error in memory transfer
84 * 0x0a: Bus error in device transfer
85 * 0x0b: Bus error in base address reading
86 * 0x0d: Count error in memory transfer count
87 * 0x0e: Count error in device transfer count
88 * 0x0f: Count error in base address
89 * 0x10: External abort
90 * 0x11: Software abort
91 */
92
93 /* DCR bits */
94 #define DMAC_DCR_XRM_MASK 0xc0
95 #define DMAC_DCR_XRM_BURST 0x00 /* Burst mode */
96 #define DMAC_DCR_XRM_CSWOH 0x80 /* Cycle steal w/o hold */
97 #define DMAC_DCR_XRM_CSWH 0xc0 /* Cycle steal w/ hold */
98 #define DMAC_DCR_OTYP_MASK 0x30
99 #define DMAC_DCR_OTYP_EASYNC 0x00 /* Explicit M68000 */
100 #define DMAC_DCR_OTYP_ESYNC 0x10 /* Explicit M6800 */
101 #define DMAC_DCR_OTYP_IA 0x20 /* Implicit with ack */
102 #define DMAC_DCR_OTYP_IAR 0x30 /* Implicit with ack and rdy */
103 #define DMAC_DCR_OPS_MASK 0x08
104 #define DMAC_DCR_OPS_8BIT 0x00 /* 8bit */
105 #define DMAC_DCR_OPS_16BIT 0x08 /* 16bit */
106 #define DMAC_DCR_PCL_MASK 0x03
107 #define DMAC_DCR_PCL_STATUS 0x00
108 #define DMAC_DCR_PCL_INTERRUPT 0x01
109 #define DMAC_DCR_PCL_STARTPLS 0x02
110 #define DMAC_DCR_PCL_ABORT 0x03
111
112 /* OCR bits */
113 #define DMAC_OCR_DIR_MASK 0x80
114 #define DMAC_OCR_DIR_MTD 0x00 /* Direction: memory to device */
115 #define DMAC_OCR_DIR_DTM 0x80 /* Direction: device to memory */
116 #define DMAC_OCR_SIZE_MASK 0x30
117 #define DMAC_OCR_SIZE_BYTE 0x00 /* Size: byte */
118 #define DMAC_OCR_SIZE_WORD 0x10 /* Size: word */
119 #define DMAC_OCR_SIZE_LONGWORD 0x20 /* Size: longword */
120 #define DMAC_OCR_SIZE_BYTE_NOPACK 0x30 /* Size: byte, no packing */
121 #define DMAC_OCR_CHAIN_MASK 0x0c
122 #define DMAC_OCR_CHAIN_DISABLED 0x00 /* Chain mode disabled */
123 #define DMAC_OCR_CHAIN_ARRAY 0x08 /* Array chain mode */
124 #define DMAC_OCR_CHAIN_LINKARRAY 0x0c /* Linked array chain mode */
125 #define DMAC_OCR_REQG_MASK 0x03
126 #define DMAC_OCR_REQG_LIMITED_RATE 0x00 /* Internal limited rate */
127 #define DMAC_OCR_REQG_MAXIMUM_RATE 0x01 /* Internal maximum rate */
128 #define DMAC_OCR_REQG_EXTERNAL 0x02 /* External */
129 #define DMAC_OCR_REQG_AUTO_START 0x03 /* Auto start, external */
130
131 /* SCR bits */
132 #define DMAC_SCR_MAC_MASK 0x0c
133 #define DMAC_SCR_MAC_NO_COUNT 0x00 /* Fixed memory address */
134 #define DMAC_SCR_MAC_COUNT_UP 0x04 /* Memory address count up */
135 #define DMAC_SCR_MAC_COUNT_DOWN 0x08 /* Memory address count down */
136 #define DMAC_SCR_DAC_MASK 0x03
137 #define DMAC_SCR_DAC_NO_COUNT 0x00 /* Fixed device address */
138 #define DMAC_SCR_DAC_COUNT_UP 0x01 /* Device address count up */
139 #define DMAC_SCR_DAC_COUNT_DOWN 0x02 /* Device address count down */
140
141 /* CCR bits */
142 #define DMAC_CCR_STR 0x80 /* Start channel */
143 #define DMAC_CCR_CNT 0x40 /* Continue operation */
144 #define DMAC_CCR_HLT 0x20 /* Software halt */
145 #define DMAC_CCR_SAB 0x10 /* Software abort */
146 #define DMAC_CCR_INT 0x08 /* Interrupt enable */
147
148 /* GCR bits */
149 #define DMAC_GCR_BT_MASK 0x0c
150 #define DMAC_GCR_BT_16 0x00 /* 16clocks */
151 #define DMAC_GCR_BT_32 0x04 /* 32clocks */
152 #define DMAC_GCR_BT_64 0x08 /* 64clocks */
153 #define DMAC_GCR_BT_128 0x0c /* 128clocks */
154 #define DMAC_GCR_BR_MASK 0x03
155 #define DMAC_GCR_BR_50 0x00 /* 50% bandwidth */
156 #define DMAC_GCR_BR_25 0x01 /* 25% bandwidth */
157 #define DMAC_GCR_BR_12 0x02 /* 12.5% bandwidth */
158 #define DMAC_GCR_BR_6 0x03 /* 6.25% bandwidth */
159
160 /* MFC/DFC function codes */
161 #define DMAC_FC_USER_DATA 0x01
162 #define DMAC_FC_USER_PROGRAM 0x02
163 #define DMAC_FC_KERNEL_DATA 0x05
164 #define DMAC_FC_KERNEL_PROGRAM 0x06
165 #define DMAC_FC_CPU 0x07
166
167 /*
168 * An element of the array used in DMAC scatter-gather transfer
169 * (array chaining mode)
170 */
171 struct dmac_sg_array {
172 u_int32_t da_addr;
173 u_int16_t da_count;
174 };
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