Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/mfireg.h
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1 /* $NetBSD: mfireg.h,v 1.2.2.3 2006/12/21 14:21:24 tron Exp $ */ 2 /* $OpenBSD: mfireg.h,v 1.24 2006/06/19 19:05:45 marco Exp $ */ 3 /* 4 * Copyright (c) 2006 Marco Peereboom <marco@peereboom.us> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* management interface constants */ 20 #define MFI_MGMT_VD 0x01 21 #define MFI_MGMT_SD 0x02 22 23 /* generic constants */ 24 #define MFI_FRAME_SIZE 64 25 #define MFI_SENSE_SIZE 128 26 #define MFI_OSTS_INTR_VALID 0x00000002 /* valid interrupt */ 27 #define MFI_INVALID_CTX 0xffffffff 28 #define MFI_ENABLE_INTR 0x01 29 #define MFI_MAXFER MAXPHYS /* XXX bogus */ 30 31 /* register offsets */ 32 #define MFI_IMSG0 0x10 /* inbound msg 0 */ 33 #define MFI_IMSG1 0x14 /* inbound msg 1 */ 34 #define MFI_OMSG0 0x18 /* outbound msg 0 */ 35 #define MFI_OMSG1 0x1c /* outbound msg 1 */ 36 #define MFI_IDB 0x20 /* inbound doorbell */ 37 #define MFI_ISTS 0x24 /* inbound intr stat */ 38 #define MFI_IMSK 0x28 /* inbound intr mask */ 39 #define MFI_ODB 0x2c /* outbound doorbell */ 40 #define MFI_OSTS 0x30 /* outbound intr stat */ 41 #define MFI_OMSK 0x34 /* outbound inter mask */ 42 #define MFI_IQP 0x40 /* inbound queue port */ 43 #define MFI_OQP 0x44 /* outbound queue port */ 44 45 /* * firmware states */ 46 #define MFI_STATE_MASK 0xf0000000 47 #define MFI_STATE_UNDEFINED 0x00000000 48 #define MFI_STATE_BB_INIT 0x10000000 49 #define MFI_STATE_FW_INIT 0x40000000 50 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 51 #define MFI_STATE_FW_INIT_2 0x70000000 52 #define MFI_STATE_DEVICE_SCAN 0x80000000 53 #define MFI_STATE_FLUSH_CACHE 0xa0000000 54 #define MFI_STATE_READY 0xb0000000 55 #define MFI_STATE_OPERATIONAL 0xc0000000 56 #define MFI_STATE_FAULT 0xf0000000 57 #define MFI_STATE_MAXSGL_MASK 0x00ff0000 58 #define MFI_STATE_MAXCMD_MASK 0x0000ffff 59 60 /* command reset register */ 61 #define MFI_INIT_ABORT 0x00000000 62 #define MFI_INIT_READY 0x00000002 63 #define MFI_INIT_MFIMODE 0x00000004 64 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 65 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE 66 67 /* mfi Frame flags */ 68 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 69 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 70 #define MFI_FRAME_SGL32 0x0000 71 #define MFI_FRAME_SGL64 0x0002 72 #define MFI_FRAME_SENSE32 0x0000 73 #define MFI_FRAME_SENSE64 0x0004 74 #define MFI_FRAME_DIR_NONE 0x0000 75 #define MFI_FRAME_DIR_WRITE 0x0008 76 #define MFI_FRAME_DIR_READ 0x0010 77 #define MFI_FRAME_DIR_BOTH 0x0018 78 79 /* mfi command opcodes */ 80 #define MFI_CMD_INIT 0x00 81 #define MFI_CMD_LD_READ 0x01 82 #define MFI_CMD_LD_WRITE 0x02 83 #define MFI_CMD_LD_SCSI_IO 0x03 84 #define MFI_CMD_PD_SCSI_IO 0x04 85 #define MFI_CMD_DCMD 0x05 86 #define MFI_CMD_ABORT 0x06 87 #define MFI_CMD_SMP 0x07 88 #define MFI_CMD_STP 0x08 89 90 /* direct commands */ 91 #define MR_DCMD_CTRL_GET_INFO 0x01010000 92 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 93 #define MR_FLUSH_CTRL_CACHE 0x01 94 #define MR_FLUSH_DISK_CACHE 0x02 95 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 96 #define MR_ENABLE_DRIVE_SPINDOWN 0x01 97 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 98 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 99 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 100 #define MR_DCMD_PD_GET_LIST 0x02010000 101 #define MR_DCMD_PD_GET_INFO 0x02020000 102 #define MD_DCMD_PD_SET_STATE 0x02030100 103 #define MD_DCMD_PD_REBUILD 0x02040100 104 #define MR_DCMD_PD_BLINK 0x02070100 105 #define MR_DCMD_PD_UNBLINK 0x02070200 106 #define MR_DCMD_LD_GET_LIST 0x03010000 107 #define MR_DCMD_LD_GET_INFO 0x03020000 108 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 109 #define MD_DCMD_CONF_GET 0x04010000 110 #define MR_DCMD_CLUSTER 0x08000000 111 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 112 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 113 114 #define MR_DCMD_SPEAKER_GET 0x01030100 115 #define MR_DCMD_SPEAKER_ENABLE 0x01030200 116 #define MR_DCMD_SPEAKER_DISABLE 0x01030300 117 #define MR_DCMD_SPEAKER_SILENCE 0x01030400 118 #define MR_DCMD_SPEAKER_TEST 0x01030500 119 120 /* mailbox bytes in direct command */ 121 #define MFI_MBOX_SIZE 12 122 123 /* mfi completion codes */ 124 typedef enum { 125 MFI_STAT_OK = 0x00, 126 MFI_STAT_INVALID_CMD = 0x01, 127 MFI_STAT_INVALID_DCMD = 0x02, 128 MFI_STAT_INVALID_PARAMETER = 0x03, 129 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 130 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 131 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 132 MFI_STAT_APP_IN_USE = 0x07, 133 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 134 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 135 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 136 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 137 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 138 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 139 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 140 MFI_STAT_FLASH_BUSY = 0x0f, 141 MFI_STAT_FLASH_ERROR = 0x10, 142 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 143 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 144 MFI_STAT_FLASH_NOT_OPEN = 0x13, 145 MFI_STAT_FLASH_NOT_STARTED = 0x14, 146 MFI_STAT_FLUSH_FAILED = 0x15, 147 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 148 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 149 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 150 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 151 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 152 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 153 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 154 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 155 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 156 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 157 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 158 MFI_STAT_MFC_HW_ERROR = 0x21, 159 MFI_STAT_NO_HW_PRESENT = 0x22, 160 MFI_STAT_NOT_FOUND = 0x23, 161 MFI_STAT_NOT_IN_ENCL = 0x24, 162 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 163 MFI_STAT_PD_TYPE_WRONG = 0x26, 164 MFI_STAT_PR_DISABLED = 0x27, 165 MFI_STAT_ROW_INDEX_INVALID = 0x28, 166 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 167 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 168 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 169 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 170 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 171 MFI_STAT_SCSI_IO_FAILED = 0x2e, 172 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 173 MFI_STAT_SHUTDOWN_FAILED = 0x30, 174 MFI_STAT_TIME_NOT_SET = 0x31, 175 MFI_STAT_WRONG_STATE = 0x32, 176 MFI_STAT_LD_OFFLINE = 0x33, 177 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 178 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 179 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 180 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 181 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 182 MFI_STAT_INVALID_STATUS = 0xff 183 } mfi_status_t; 184 185 typedef enum { 186 MFI_EVT_CLASS_DEBUG = -2, 187 MFI_EVT_CLASS_PROGRESS = -1, 188 MFI_EVT_CLASS_INFO = 0, 189 MFI_EVT_CLASS_WARNING = 1, 190 MFI_EVT_CLASS_CRITICAL = 2, 191 MFI_EVT_CLASS_FATAL = 3, 192 MFI_EVT_CLASS_DEAD = 4 193 } mfi_evt_class_t; 194 195 typedef enum { 196 MFI_EVT_LOCALE_LD = 0x0001, 197 MFI_EVT_LOCALE_PD = 0x0002, 198 MFI_EVT_LOCALE_ENCL = 0x0004, 199 MFI_EVT_LOCALE_BBU = 0x0008, 200 MFI_EVT_LOCALE_SAS = 0x0010, 201 MFI_EVT_LOCALE_CTRL = 0x0020, 202 MFI_EVT_LOCALE_CONFIG = 0x0040, 203 MFI_EVT_LOCALE_CLUSTER = 0x0080, 204 MFI_EVT_LOCALE_ALL = 0xffff 205 } mfi_evt_locale_t; 206 207 typedef enum { 208 MR_EVT_ARGS_NONE = 0x00, 209 MR_EVT_ARGS_CDB_SENSE, 210 MR_EVT_ARGS_LD, 211 MR_EVT_ARGS_LD_COUNT, 212 MR_EVT_ARGS_LD_LBA, 213 MR_EVT_ARGS_LD_OWNER, 214 MR_EVT_ARGS_LD_LBA_PD_LBA, 215 MR_EVT_ARGS_LD_PROG, 216 MR_EVT_ARGS_LD_STATE, 217 MR_EVT_ARGS_LD_STRIP, 218 MR_EVT_ARGS_PD, 219 MR_EVT_ARGS_PD_ERR, 220 MR_EVT_ARGS_PD_LBA, 221 MR_EVT_ARGS_PD_LBA_LD, 222 MR_EVT_ARGS_PD_PROG, 223 MR_EVT_ARGS_PD_STATE, 224 MR_EVT_ARGS_PCI, 225 MR_EVT_ARGS_RATE, 226 MR_EVT_ARGS_STR, 227 MR_EVT_ARGS_TIME, 228 MR_EVT_ARGS_ECC 229 } mfi_evt_args; 230 231 /* driver definitions */ 232 #define MFI_MAX_PD_CHANNELS 2 233 #define MFI_MAX_PD_ARRAY 32 234 #define MFI_MAX_LD_CHANNELS 2 235 #define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 236 #define MFI_MAX_CHANNEL_DEVS 128 237 #define MFI_DEFAULT_ID -1 238 #define MFI_MAX_LUN 8 239 #define MFI_MAX_LD 64 240 #define MFI_MAX_SPAN 8 241 #define MFI_MAX_ARRAY_DEDICATED 16 242 243 /* sense buffer */ 244 struct mfi_sense { 245 uint8_t mse_data[MFI_SENSE_SIZE]; 246 } __packed; 247 248 /* scatter gather elements */ 249 struct mfi_sg32 { 250 uint32_t addr; 251 uint32_t len; 252 } __packed; 253 254 struct mfi_sg64 { 255 uint64_t addr; 256 uint32_t len; 257 } __packed; 258 259 union mfi_sgl { 260 struct mfi_sg32 sg32[1]; 261 struct mfi_sg64 sg64[1]; 262 } __packed; 263 264 /* message frame */ 265 struct mfi_frame_header { 266 uint8_t mfh_cmd; 267 uint8_t mfh_sense_len; 268 uint8_t mfh_cmd_status; 269 uint8_t mfh_scsi_status; 270 uint8_t mfh_target_id; 271 uint8_t mfh_lun_id; 272 uint8_t mfh_cdb_len; 273 uint8_t mfh_sg_count; 274 uint32_t mfh_context; 275 uint32_t mfh_pad0; 276 uint16_t mfh_flags; 277 uint16_t mfh_timeout; 278 uint32_t mfh_data_len; 279 } __packed; 280 281 union mfi_sgl_frame { 282 struct mfi_sg32 sge32[8]; 283 struct mfi_sg64 sge64[5]; 284 285 } __packed; 286 287 struct mfi_init_frame { 288 struct mfi_frame_header mif_header; 289 uint32_t mif_qinfo_new_addr_lo; 290 uint32_t mif_qinfo_new_addr_hi; 291 uint32_t mif_qinfo_old_addr_lo; 292 uint32_t mif_qinfo_old_addr_hi; 293 uint32_t mif_reserved[6]; 294 } __packed; 295 296 /* queue init structure */ 297 struct mfi_init_qinfo { 298 uint32_t miq_flags; 299 uint32_t miq_rq_entries; 300 uint32_t miq_rq_addr_lo; 301 uint32_t miq_rq_addr_hi; 302 uint32_t miq_pi_addr_lo; 303 uint32_t miq_pi_addr_hi; 304 uint32_t miq_ci_addr_lo; 305 uint32_t miq_ci_addr_hi; 306 } __packed; 307 308 #define MFI_IO_FRAME_SIZE 40 309 struct mfi_io_frame { 310 struct mfi_frame_header mif_header; 311 uint32_t mif_sense_addr_lo; 312 uint32_t mif_sense_addr_hi; 313 uint32_t mif_lba_lo; 314 uint32_t mif_lba_hi; 315 union mfi_sgl mif_sgl; 316 } __packed; 317 318 #define MFI_PASS_FRAME_SIZE 48 319 struct mfi_pass_frame { 320 struct mfi_frame_header mpf_header; 321 uint32_t mpf_sense_addr_lo; 322 uint32_t mpf_sense_addr_hi; 323 uint8_t mpf_cdb[16]; 324 union mfi_sgl mpf_sgl; 325 } __packed; 326 327 #define MFI_DCMD_FRAME_SIZE 40 328 struct mfi_dcmd_frame { 329 struct mfi_frame_header mdf_header; 330 uint32_t mdf_opcode; 331 uint8_t mdf_mbox[MFI_MBOX_SIZE]; 332 union mfi_sgl mdf_sgl; 333 } __packed; 334 335 struct mfi_abort_frame { 336 struct mfi_frame_header maf_header; 337 uint32_t maf_abort_context; 338 uint32_t maf_pad; 339 uint32_t maf_abort_mfi_addr_lo; 340 uint32_t maf_abort_mfi_addr_hi; 341 uint32_t maf_reserved[6]; 342 } __packed; 343 344 struct mfi_smp_frame { 345 struct mfi_frame_header msf_header; 346 uint64_t msf_sas_addr; 347 union { 348 struct mfi_sg32 sg32[2]; 349 struct mfi_sg64 sg64[2]; 350 } msf_sgl; 351 } __packed; 352 353 struct mfi_stp_frame { 354 struct mfi_frame_header msf_header; 355 uint16_t msf_fis[10]; 356 uint32_t msf_stp_flags; 357 union { 358 struct mfi_sg32 sg32[2]; 359 struct mfi_sg64 sg64[2]; 360 } msf_sgl; 361 } __packed; 362 363 union mfi_frame { 364 struct mfi_frame_header mfr_header; 365 struct mfi_init_frame mfr_init; 366 struct mfi_io_frame mfr_io; 367 struct mfi_pass_frame mfr_pass; 368 struct mfi_dcmd_frame mfr_dcmd; 369 struct mfi_abort_frame mfr_abort; 370 struct mfi_smp_frame mfr_smp; 371 struct mfi_stp_frame mfr_stp; 372 uint8_t mfr_bytes[MFI_FRAME_SIZE]; 373 }; 374 375 union mfi_evt_class_locale { 376 struct { 377 uint16_t locale; 378 uint8_t reserved; 379 int8_t class; 380 } __packed mec_members; 381 382 uint32_t mec_word; 383 } __packed; 384 385 struct mfi_evt_log_info { 386 uint32_t mel_newest_seq_num; 387 uint32_t mel_oldest_seq_num; 388 uint32_t mel_clear_seq_num; 389 uint32_t mel_shutdown_seq_num; 390 uint32_t mel_boot_seq_num; 391 } __packed; 392 393 struct mfi_progress { 394 uint16_t mp_progress; 395 uint16_t mp_elapsed_seconds; 396 } __packed; 397 398 struct mfi_evtarg_ld { 399 uint16_t mel_target_id; 400 uint8_t mel_ld_index; 401 uint8_t mel_reserved; 402 } __packed; 403 404 struct mfi_evtarg_pd { 405 uint16_t mep_device_id; 406 uint8_t mep_encl_index; 407 uint8_t mep_slot_number; 408 } __packed; 409 410 struct mfi_evt_detail { 411 uint32_t med_seq_num; 412 uint32_t med_time_stamp; 413 uint32_t med_code; 414 union mfi_evt_class_locale med_cl; 415 uint8_t med_arg_type; 416 uint8_t med_reserved1[15]; 417 418 union { 419 struct { 420 struct mfi_evtarg_pd pd; 421 uint8_t cdb_length; 422 uint8_t sense_length; 423 uint8_t reserved[2]; 424 uint8_t cdb[16]; 425 uint8_t sense[64]; 426 } __packed cdb_sense; 427 428 struct mfi_evtarg_ld ld; 429 430 struct { 431 struct mfi_evtarg_ld ld; 432 uint64_t count; 433 } __packed ld_count; 434 435 struct { 436 uint64_t lba; 437 struct mfi_evtarg_ld ld; 438 } __packed ld_lba; 439 440 struct { 441 struct mfi_evtarg_ld ld; 442 uint32_t prev_owner; 443 uint32_t new_owner; 444 } __packed ld_owner; 445 446 struct { 447 uint64_t ld_lba; 448 uint64_t pd_lba; 449 struct mfi_evtarg_ld ld; 450 struct mfi_evtarg_pd pd; 451 } __packed ld_lba_pd_lba; 452 453 struct { 454 struct mfi_evtarg_ld ld; 455 struct mfi_progress prog; 456 } __packed ld_prog; 457 458 struct { 459 struct mfi_evtarg_ld ld; 460 uint32_t prev_state; 461 uint32_t new_state; 462 } __packed ld_state; 463 464 struct { 465 uint64_t strip; 466 struct mfi_evtarg_ld ld; 467 } __packed ld_strip; 468 469 struct mfi_evtarg_pd pd; 470 471 struct { 472 struct mfi_evtarg_pd pd; 473 uint32_t err; 474 } __packed pd_err; 475 476 struct { 477 uint64_t lba; 478 struct mfi_evtarg_pd pd; 479 } __packed pd_lba; 480 481 struct { 482 uint64_t lba; 483 struct mfi_evtarg_pd pd; 484 struct mfi_evtarg_ld ld; 485 } __packed pd_lba_ld; 486 487 struct { 488 struct mfi_evtarg_pd pd; 489 struct mfi_progress prog; 490 } __packed pd_prog; 491 492 struct { 493 struct mfi_evtarg_pd pd; 494 uint32_t prev_state; 495 uint32_t new_state; 496 } __packed pd_state; 497 498 struct { 499 uint16_t vendor_id; 500 uint16_t device_id; 501 uint16_t subvendor_id; 502 uint16_t subdevice_id; 503 } __packed pci; 504 505 uint32_t rate; 506 char str[96]; 507 508 struct { 509 uint32_t rtc; 510 uint32_t elapsed_seconds; 511 } __packed time; 512 513 struct { 514 uint32_t ecar; 515 uint32_t elog; 516 char str[64]; 517 } __packed ecc; 518 519 uint8_t b[96]; 520 uint16_t s[48]; 521 uint32_t w[24]; 522 uint64_t d[12]; 523 } args; 524 525 char med_description[128]; 526 } __packed; 527 528 /* controller properties from mfi_ctrl_info */ 529 struct mfi_ctrl_props { 530 uint16_t mcp_seq_num; 531 uint16_t mcp_pred_fail_poll_interval; 532 uint16_t mcp_intr_throttle_cnt; 533 uint16_t mcp_intr_throttle_timeout; 534 uint8_t mcp_rebuild_rate; 535 uint8_t mcp_patrol_read_rate; 536 uint8_t mcp_bgi_rate; 537 uint8_t mcp_cc_rate; 538 uint8_t mcp_recon_rate; 539 uint8_t mcp_cache_flush_interval; 540 uint8_t mcp_spinup_drv_cnt; 541 uint8_t mcp_spinup_delay; 542 uint8_t mcp_cluster_enable; 543 uint8_t mcp_coercion_mode; 544 uint8_t mcp_alarm_enable; 545 uint8_t mcp_disable_auto_rebuild; 546 uint8_t mcp_disable_battery_warn; 547 uint8_t mcp_ecc_bucket_size; 548 uint16_t mcp_ecc_bucket_leak_rate; 549 uint8_t mcp_restore_hotspare_on_insertion; 550 uint8_t mcp_expose_encl_devices; 551 uint8_t mcp_reserved[38]; 552 } __packed; 553 554 /* pci info */ 555 struct mfi_info_pci { 556 uint16_t mip_vendor; 557 uint16_t mip_device; 558 uint16_t mip_subvendor; 559 uint16_t mip_subdevice; 560 uint8_t mip_reserved[24]; 561 } __packed; 562 563 /* host interface infor */ 564 struct mfi_info_host { 565 uint8_t mih_type; 566 #define MFI_INFO_HOST_PCIX 0x01 567 #define MFI_INFO_HOST_PCIE 0x02 568 #define MFI_INFO_HOST_ISCSI 0x04 569 #define MFI_INFO_HOST_SAS3G 0x08 570 uint8_t mih_reserved[6]; 571 uint8_t mih_port_count; 572 uint64_t mih_port_addr[8]; 573 } __packed; 574 575 /* device interface info */ 576 struct mfi_info_device { 577 uint8_t mid_type; 578 #define MFI_INFO_DEV_SPI 0x01 579 #define MFI_INFO_DEV_SAS3G 0x02 580 #define MFI_INFO_DEV_SATA1 0x04 581 #define MFI_INFO_DEV_SATA3G 0x08 582 uint8_t mid_reserved[6]; 583 uint8_t mid_port_count; 584 uint64_t mid_port_addr[8]; 585 } __packed; 586 587 /* firmware component info */ 588 struct mfi_info_component { 589 char mic_name[8]; 590 char mic_version[32]; 591 char mic_build_date[16]; 592 char mic_build_time[16]; 593 } __packed; 594 595 /* controller info from MFI_DCMD_CTRL_GETINFO. */ 596 struct mfi_ctrl_info { 597 struct mfi_info_pci mci_pci; 598 struct mfi_info_host mci_host; 599 struct mfi_info_device mci_device; 600 601 /* Firmware components that are present and active. */ 602 uint32_t mci_image_check_word; 603 uint32_t mci_image_component_count; 604 struct mfi_info_component mci_image_component[8]; 605 606 /* Firmware components that have been flashed but are inactive */ 607 uint32_t mci_pending_image_component_count; 608 struct mfi_info_component mci_pending_image_component[8]; 609 610 uint8_t mci_max_arms; 611 uint8_t mci_max_spans; 612 uint8_t mci_max_arrays; 613 uint8_t mci_max_lds; 614 char mci_product_name[80]; 615 char mci_serial_number[32]; 616 uint32_t mci_hw_present; 617 #define MFI_INFO_HW_BBU 0x01 618 #define MFI_INFO_HW_ALARM 0x02 619 #define MFI_INFO_HW_NVRAM 0x04 620 #define MFI_INFO_HW_UART 0x08 621 uint32_t mci_current_fw_time; 622 uint16_t mci_max_cmds; 623 uint16_t mci_max_sg_elements; 624 uint32_t mci_max_request_size; 625 uint16_t mci_lds_present; 626 uint16_t mci_lds_degraded; 627 uint16_t mci_lds_offline; 628 uint16_t mci_pd_present; 629 uint16_t mci_pd_disks_present; 630 uint16_t mci_pd_disks_pred_failure; 631 uint16_t mci_pd_disks_failed; 632 uint16_t mci_nvram_size; 633 uint16_t mci_memory_size; 634 uint16_t mci_flash_size; 635 uint16_t mci_ram_correctable_errors; 636 uint16_t mci_ram_uncorrectable_errors; 637 uint8_t mci_cluster_allowed; 638 uint8_t mci_cluster_active; 639 uint16_t mci_max_strips_per_io; 640 641 uint32_t mci_raid_levels; 642 #define MFI_INFO_RAID_0 0x01 643 #define MFI_INFO_RAID_1 0x02 644 #define MFI_INFO_RAID_5 0x04 645 #define MFI_INFO_RAID_1E 0x08 646 #define MFI_INFO_RAID_6 0x10 647 648 uint32_t mci_adapter_ops; 649 #define MFI_INFO_AOPS_RBLD_RATE 0x0001 650 #define MFI_INFO_AOPS_CC_RATE 0x0002 651 #define MFI_INFO_AOPS_BGI_RATE 0x0004 652 #define MFI_INFO_AOPS_RECON_RATE 0x0008 653 #define MFI_INFO_AOPS_PATROL_RATE 0x0010 654 #define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 655 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 656 #define MFI_INFO_AOPS_BBU 0x0080 657 #define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 658 #define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 659 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 660 #define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 661 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 662 #define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 663 #define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 664 665 uint32_t mci_ld_ops; 666 #define MFI_INFO_LDOPS_READ_POLICY 0x01 667 #define MFI_INFO_LDOPS_WRITE_POLICY 0x02 668 #define MFI_INFO_LDOPS_IO_POLICY 0x04 669 #define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 670 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 671 672 struct { 673 uint8_t min; 674 uint8_t max; 675 uint8_t reserved[2]; 676 } __packed mci_stripe_sz_ops; 677 678 uint32_t mci_pd_ops; 679 #define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 680 #define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 681 #define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 682 683 uint32_t mci_pd_mix_support; 684 #define MFI_INFO_PDMIX_SAS 0x01 685 #define MFI_INFO_PDMIX_SATA 0x02 686 #define MFI_INFO_PDMIX_ENCL 0x04 687 #define MFI_INFO_PDMIX_LD 0x08 688 #define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 689 690 uint8_t mci_ecc_bucket_count; 691 uint8_t mci_reserved2[11]; 692 struct mfi_ctrl_props mci_properties; 693 char mci_package_version[0x60]; 694 uint8_t mci_pad[0x800 - 0x6a0]; 695 } __packed; 696 697 /* logical disk info from MR_DCMD_LD_GET_LIST */ 698 struct mfi_ld { 699 uint8_t mld_target; 700 uint8_t mld_res; 701 uint16_t mld_seq; 702 } __packed; 703 704 struct mfi_ld_list { 705 uint32_t mll_no_ld; 706 uint32_t mll_res; 707 struct { 708 struct mfi_ld mll_ld; 709 uint8_t mll_state; 710 #define MFI_LD_OFFLINE 0x00 711 #define MFI_LD_PART_DEGRADED 0x01 712 #define MFI_LD_DEGRADED 0x02 713 #define MFI_LD_ONLINE 0x03 714 uint8_t mll_res2; 715 uint8_t mll_res3; 716 uint8_t mll_res4; 717 u_quad_t mll_size; 718 } mll_list[MFI_MAX_LD]; 719 } __packed; 720 721 /* logicl disk details from MR_DCMD_LD_GET_INFO */ 722 struct mfi_ld_prop { 723 struct mfi_ld mlp_ld; 724 char mlp_name[16]; 725 uint8_t mlp_cache_policy; 726 uint8_t mlp_acces_policy; 727 uint8_t mlp_diskcache_policy; 728 uint8_t mlp_cur_cache_policy; 729 uint8_t mlp_disable_bgi; 730 uint8_t mlp_res[7]; 731 } __packed; 732 733 struct mfi_ld_parm { 734 uint8_t mpa_pri_raid; /* SNIA DDF PRL */ 735 #define MFI_DDF_PRL_RAID0 0x00 736 #define MFI_DDF_PRL_RAID1 0x01 737 #define MFI_DDF_PRL_RAID3 0x03 738 #define MFI_DDF_PRL_RAID4 0x04 739 #define MFI_DDF_PRL_RAID5 0x05 740 #define MFI_DDF_PRL_RAID1E 0x11 741 #define MFI_DDF_PRL_JBOD 0x0f 742 #define MFI_DDF_PRL_CONCAT 0x1f 743 #define MFI_DDF_PRL_RAID5E 0x15 744 #define MFI_DDF_PRL_RAID5EE 0x25 745 #define MFI_DDF_PRL_RAID6 0x16 746 uint8_t mpa_raid_qual; /* SNIA DDF RLQ */ 747 uint8_t mpa_sec_raid; /* SNIA DDF SRL */ 748 #define MFI_DDF_SRL_STRIPED 0x00 749 #define MFI_DDF_SRL_MIRRORED 0x01 750 #define MFI_DDF_SRL_CONCAT 0x02 751 #define MFI_DDF_SRL_SPANNED 0x03 752 uint8_t mpa_stripe_size; 753 uint8_t mpa_no_drv_per_span; 754 uint8_t mpa_span_depth; 755 uint8_t mpa_state; 756 uint8_t mpa_init_state; 757 uint8_t mpa_res[24]; 758 } __packed; 759 760 struct mfi_ld_span { 761 u_quad_t mls_start_block; 762 u_quad_t mls_no_blocks; 763 uint16_t mls_index; 764 uint8_t mls_res[6]; 765 } __packed; 766 767 struct mfi_ld_cfg { 768 struct mfi_ld_prop mlc_prop; 769 struct mfi_ld_parm mlc_parm; 770 struct mfi_ld_span mlc_span[MFI_MAX_SPAN]; 771 } __packed; 772 773 struct mfi_ld_progress { 774 uint32_t mlp_in_prog; 775 #define MFI_LD_PROG_CC 0x01 776 #define MFI_LD_PROG_BGI 0x02 777 #define MFI_LD_PROG_FGI 0x04 778 #define MFI_LD_PROG_RECONSTRUCT 0x08 779 struct mfi_progress mlp_cc; 780 struct mfi_progress mlp_bgi; 781 struct mfi_progress mlp_fgi; 782 struct mfi_progress mlp_reconstruct; 783 struct mfi_progress mlp_res[4]; 784 } __packed; 785 786 struct mfi_ld_details { 787 struct mfi_ld_cfg mld_cfg; 788 u_quad_t mld_size; 789 struct mfi_ld_progress mld_progress; 790 uint16_t mld_clust_own_id; 791 uint8_t mld_res1; 792 uint8_t mld_res2; 793 uint8_t mld_inq_page83[64]; 794 uint8_t mld_res[16]; 795 } __packed; 796 797 /* physical disk info from MR_DCMD_PD_GET_LIST */ 798 struct mfi_pd_address { 799 uint16_t mpa_pd_id; 800 uint16_t mpa_enc_id; 801 uint8_t mpa_enc_index; 802 uint8_t mpa_enc_slot; 803 uint8_t mpa_scsi_type; 804 uint8_t mpa_port; 805 u_quad_t mpa_sas_address[2]; 806 } __packed; 807 808 struct mfi_pd_list { 809 uint32_t mpl_size; 810 uint32_t mpl_no_pd; 811 struct mfi_pd_address mpl_address[1]; 812 } __packed; 813 #define MFI_PD_LIST_SIZE (256 * sizeof(struct mfi_pd_address) + 8) 814 815 struct mfi_pd { 816 uint16_t mfp_id; 817 uint16_t mfp_seq; 818 } __packed; 819 820 struct mfi_pd_progress { 821 uint32_t mfp_in_prog; 822 #define MFI_PD_PROG_RBLD 0x01 823 #define MFI_PD_PROG_PR 0x02 824 #define MFI_PD_PROG_CLEAR 0x04 825 struct mfi_progress mfp_rebuild; 826 struct mfi_progress mfp_patrol_read; 827 struct mfi_progress mfp_clear; 828 struct mfi_progress mfp_res[4]; 829 } __packed; 830 831 struct mfi_pd_details { 832 struct mfi_pd mpd_pd; 833 uint8_t mpd_inq_data[96]; 834 uint8_t mpd_inq_page83[64]; 835 uint8_t mpd_no_support; 836 uint8_t mpd_scsy_type; 837 uint8_t mpd_port; 838 uint8_t mpd_speed; 839 uint32_t mpd_mediaerr_cnt; 840 uint32_t mpd_othererr_cnt; 841 uint32_t mpd_predfail_cnt; 842 uint32_t mpd_last_pred_event; 843 uint16_t mpd_fw_state; 844 uint8_t mpd_rdy_for_remove; 845 uint8_t mpd_link_speed; 846 uint32_t mpd_ddf_state; 847 #define MFI_DDF_GUID_FORCED 0x01 848 #define MFI_DDF_PART_OF_VD 0x02 849 #define MFI_DDF_GLOB_HOTSPARE 0x04 850 #define MFI_DDF_HOTSPARE 0x08 851 #define MFI_DDF_FOREIGN 0x10 852 #define MFI_DDF_TYPE_MASK 0xf000 853 #define MFI_DDF_TYPE_UNKNOWN 0x0000 854 #define MFI_DDF_TYPE_PAR_SCSI 0x1000 855 #define MFI_DDF_TYPE_SAS 0x2000 856 #define MFI_DDF_TYPE_SATA 0x3000 857 #define MFI_DDF_TYPE_FC 0x4000 858 struct { 859 uint8_t mpp_cnt; 860 uint8_t mpp_severed; 861 uint8_t mpp_res[6]; 862 u_quad_t mpp_sas_addr[4]; 863 } __packed mpd_path; 864 u_quad_t mpd_size; 865 u_quad_t mpd_no_coerce_size; 866 u_quad_t mpd_coerce_size; 867 uint16_t mpd_enc_id; 868 uint8_t mpd_enc_idx; 869 uint8_t mpd_enc_slot; 870 struct mfi_pd_progress mpd_progress; 871 uint8_t mpd_bblock_full; 872 uint8_t mpd_unusable; 873 uint8_t mpd_res[218]; /* size is 512 */ 874 } __packed; 875 876 /* array configuration from MD_DCMD_CONF_GET */ 877 struct mfi_array { 878 u_quad_t mar_smallest_pd; 879 uint8_t mar_no_disk; 880 uint8_t mar_res1; 881 uint16_t mar_array_ref; 882 uint8_t mar_res2[20]; 883 struct { 884 struct mfi_pd mar_pd; 885 uint16_t mar_pd_state; 886 #define MFI_PD_UNCONFIG_GOOD 0x00 887 #define MFI_PD_UNCONFIG_BAD 0x01 888 #define MFI_PD_HOTSPARE 0x02 889 #define MFI_PD_OFFLINE 0x10 890 #define MFI_PD_FAILED 0x11 891 #define MFI_PD_REBUILD 0x14 892 #define MFI_PD_ONLINE 0x18 893 uint8_t mar_enc_pd; 894 uint8_t mar_enc_slot; 895 } pd[MFI_MAX_PD_ARRAY]; 896 } __packed; 897 898 struct mfi_hotspare { 899 struct mfi_pd mhs_pd; 900 uint8_t mhs_type; 901 #define MFI_PD_HS_DEDICATED 0x01 902 #define MFI_PD_HS_REVERTIBLE 0x02 903 #define MFI_PD_HS_ENC_AFFINITY 0x04 904 uint8_t mhs_res[2]; 905 uint8_t mhs_array_max; 906 uint16_t mhs_array_ref[MFI_MAX_ARRAY_DEDICATED]; 907 } __packed; 908 909 struct mfi_conf { 910 uint32_t mfc_size; 911 uint16_t mfc_no_array; 912 uint16_t mfc_array_size; 913 uint16_t mfc_no_ld; 914 uint16_t mfc_ld_size; 915 uint16_t mfc_no_hs; 916 uint16_t mfc_hs_size; 917 uint8_t mfc_res[16]; 918 /* 919 * XXX this is a ridiculous hack and does not reflect reality 920 * Structures are actually indexed and therefore need pointer 921 * math to reach. We need the size of this structure first so 922 * call it with the size of this structure and then use the returned 923 * values to allocate memory and do the transfer of the whole structure 924 * then calculate pointers to each of these structures. 925 */ 926 struct mfi_array mfc_array[1]; 927 struct mfi_ld_cfg mfc_ld[1]; 928 struct mfi_hotspare mfc_hs[1]; 929 } __packed;
Cache object: c2777db560491156088705ed25399b02
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