The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/mfireg.h

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    1 /* $NetBSD: mfireg.h,v 1.3.14.1 2010/03/28 15:03:22 snj Exp $ */
    2 /* $OpenBSD: mfireg.h,v 1.24 2006/06/19 19:05:45 marco Exp $ */
    3 /*
    4  * Copyright (c) 2006 Marco Peereboom <marco@peereboom.us>
    5  *
    6  * Permission to use, copy, modify, and distribute this software for any
    7  * purpose with or without fee is hereby granted, provided that the above
    8  * copyright notice and this permission notice appear in all copies.
    9  *
   10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
   13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
   14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
   15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
   16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
   17  */
   18 
   19 /* management interface constants */
   20 #define MFI_MGMT_VD                             0x01
   21 #define MFI_MGMT_SD                             0x02
   22 
   23 /* generic constants */
   24 #define MFI_FRAME_SIZE                          64
   25 #define MFI_SENSE_SIZE                          128
   26 #define MFI_OSTS_INTR_VALID                     0x00000002 /* valid interrupt */
   27 #define MFI_OSTS_PPC_INTR_VALID                 0x80000000
   28 #define MFI_OSTS_GEN2_INTR_VALID                (0x00000001 | 0x00000004)
   29 #define MFI_INVALID_CTX                         0xffffffff
   30 #define MFI_ENABLE_INTR                         0x01
   31 #define MFI_MAXFER                              MAXPHYS /* XXX bogus */
   32 
   33 /* register offsets */
   34 #define MFI_IMSG0                               0x10 /* inbound msg 0 */
   35 #define MFI_IMSG1                               0x14 /* inbound msg 1 */
   36 #define MFI_OMSG0                               0x18 /* outbound msg 0 */
   37 #define MFI_OMSG1                               0x1c /* outbound msg 1 */
   38 #define MFI_IDB                                 0x20 /* inbound doorbell */
   39 #define MFI_ISTS                                0x24 /* inbound intr stat */
   40 #define MFI_IMSK                                0x28 /* inbound intr mask */
   41 #define MFI_ODB                                 0x2c /* outbound doorbell */
   42 #define MFI_OSTS                                0x30 /* outbound intr stat */
   43 #define MFI_OMSK                                0x34 /* outbound inter mask */
   44 #define MFI_IQP                                 0x40 /* inbound queue port */
   45 #define MFI_OQP                                 0x44 /* outbound queue port */
   46 #define MFI_ODC                                 0xa0 /* outbound doorbell clr */
   47 #define MFI_OSP                                 0xb0 /* outbound scratch pad */
   48 
   49 /* * firmware states */
   50 #define MFI_STATE_MASK                          0xf0000000
   51 #define MFI_STATE_UNDEFINED                     0x00000000
   52 #define MFI_STATE_BB_INIT                       0x10000000
   53 #define MFI_STATE_FW_INIT                       0x40000000
   54 #define MFI_STATE_WAIT_HANDSHAKE                0x60000000
   55 #define MFI_STATE_FW_INIT_2                     0x70000000
   56 #define MFI_STATE_DEVICE_SCAN                   0x80000000
   57 #define MFI_STATE_FLUSH_CACHE                   0xa0000000
   58 #define MFI_STATE_READY                         0xb0000000
   59 #define MFI_STATE_OPERATIONAL                   0xc0000000
   60 #define MFI_STATE_FAULT                         0xf0000000
   61 #define MFI_STATE_MAXSGL_MASK                   0x00ff0000
   62 #define MFI_STATE_MAXCMD_MASK                   0x0000ffff
   63 
   64 /* command reset register */
   65 #define MFI_INIT_ABORT                          0x00000000
   66 #define MFI_INIT_READY                          0x00000002
   67 #define MFI_INIT_MFIMODE                        0x00000004
   68 #define MFI_INIT_CLEAR_HANDSHAKE                0x00000008
   69 #define MFI_RESET_FLAGS                         MFI_INIT_READY|MFI_INIT_MFIMODE
   70 
   71 /* mfi Frame flags */
   72 #define MFI_FRAME_POST_IN_REPLY_QUEUE           0x0000
   73 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE      0x0001
   74 #define MFI_FRAME_SGL32                         0x0000
   75 #define MFI_FRAME_SGL64                         0x0002
   76 #define MFI_FRAME_SENSE32                       0x0000
   77 #define MFI_FRAME_SENSE64                       0x0004
   78 #define MFI_FRAME_DIR_NONE                      0x0000
   79 #define MFI_FRAME_DIR_WRITE                     0x0008
   80 #define MFI_FRAME_DIR_READ                      0x0010
   81 #define MFI_FRAME_DIR_BOTH                      0x0018
   82 
   83 /* mfi command opcodes */
   84 #define MFI_CMD_INIT                            0x00
   85 #define MFI_CMD_LD_READ                         0x01
   86 #define MFI_CMD_LD_WRITE                        0x02
   87 #define MFI_CMD_LD_SCSI_IO                      0x03
   88 #define MFI_CMD_PD_SCSI_IO                      0x04
   89 #define MFI_CMD_DCMD                            0x05
   90 #define MFI_CMD_ABORT                           0x06
   91 #define MFI_CMD_SMP                             0x07
   92 #define MFI_CMD_STP                             0x08
   93 
   94 /* direct commands */
   95 #define MR_DCMD_CTRL_GET_INFO                   0x01010000
   96 #define MR_DCMD_CTRL_CACHE_FLUSH                0x01101000
   97 #define   MR_FLUSH_CTRL_CACHE                   0x01
   98 #define   MR_FLUSH_DISK_CACHE                   0x02
   99 #define MR_DCMD_CTRL_SHUTDOWN                   0x01050000
  100 #define   MR_ENABLE_DRIVE_SPINDOWN              0x01
  101 #define MR_DCMD_CTRL_EVENT_GET_INFO             0x01040100
  102 #define MR_DCMD_CTRL_EVENT_GET                  0x01040300
  103 #define MR_DCMD_CTRL_EVENT_WAIT                 0x01040500
  104 #define MR_DCMD_PD_GET_LIST                     0x02010000
  105 #define MR_DCMD_PD_GET_INFO                     0x02020000
  106 #define MD_DCMD_PD_SET_STATE                    0x02030100
  107 #define MD_DCMD_PD_REBUILD                      0x02040100
  108 #define MR_DCMD_PD_BLINK                        0x02070100
  109 #define MR_DCMD_PD_UNBLINK                      0x02070200
  110 #define MR_DCMD_LD_GET_LIST                     0x03010000
  111 #define MR_DCMD_LD_GET_INFO                     0x03020000
  112 #define MR_DCMD_LD_GET_PROPERTIES               0x03030000
  113 #define MD_DCMD_CONF_GET                        0x04010000
  114 #define MR_DCMD_CLUSTER                         0x08000000
  115 #define MR_DCMD_CLUSTER_RESET_ALL               0x08010100
  116 #define MR_DCMD_CLUSTER_RESET_LD                0x08010200
  117 
  118 #define MR_DCMD_SPEAKER_GET                     0x01030100
  119 #define MR_DCMD_SPEAKER_ENABLE                  0x01030200
  120 #define MR_DCMD_SPEAKER_DISABLE                 0x01030300
  121 #define MR_DCMD_SPEAKER_SILENCE                 0x01030400
  122 #define MR_DCMD_SPEAKER_TEST                    0x01030500
  123 
  124 /* mailbox bytes in direct command */
  125 #define MFI_MBOX_SIZE                           12
  126 
  127 /* mfi completion codes */
  128 typedef enum {
  129         MFI_STAT_OK =                           0x00,
  130         MFI_STAT_INVALID_CMD =                  0x01,
  131         MFI_STAT_INVALID_DCMD =                 0x02,
  132         MFI_STAT_INVALID_PARAMETER =            0x03,
  133         MFI_STAT_INVALID_SEQUENCE_NUMBER =      0x04,
  134         MFI_STAT_ABORT_NOT_POSSIBLE =           0x05,
  135         MFI_STAT_APP_HOST_CODE_NOT_FOUND =      0x06,
  136         MFI_STAT_APP_IN_USE =                   0x07,
  137         MFI_STAT_APP_NOT_INITIALIZED =          0x08,
  138         MFI_STAT_ARRAY_INDEX_INVALID =          0x09,
  139         MFI_STAT_ARRAY_ROW_NOT_EMPTY =          0x0a,
  140         MFI_STAT_CONFIG_RESOURCE_CONFLICT =     0x0b,
  141         MFI_STAT_DEVICE_NOT_FOUND =             0x0c,
  142         MFI_STAT_DRIVE_TOO_SMALL =              0x0d,
  143         MFI_STAT_FLASH_ALLOC_FAIL =             0x0e,
  144         MFI_STAT_FLASH_BUSY =                   0x0f,
  145         MFI_STAT_FLASH_ERROR =                  0x10,
  146         MFI_STAT_FLASH_IMAGE_BAD =              0x11,
  147         MFI_STAT_FLASH_IMAGE_INCOMPLETE =       0x12,
  148         MFI_STAT_FLASH_NOT_OPEN =               0x13,
  149         MFI_STAT_FLASH_NOT_STARTED =            0x14,
  150         MFI_STAT_FLUSH_FAILED =                 0x15,
  151         MFI_STAT_HOST_CODE_NOT_FOUNT =          0x16,
  152         MFI_STAT_LD_CC_IN_PROGRESS =            0x17,
  153         MFI_STAT_LD_INIT_IN_PROGRESS =          0x18,
  154         MFI_STAT_LD_LBA_OUT_OF_RANGE =          0x19,
  155         MFI_STAT_LD_MAX_CONFIGURED =            0x1a,
  156         MFI_STAT_LD_NOT_OPTIMAL =               0x1b,
  157         MFI_STAT_LD_RBLD_IN_PROGRESS =          0x1c,
  158         MFI_STAT_LD_RECON_IN_PROGRESS =         0x1d,
  159         MFI_STAT_LD_WRONG_RAID_LEVEL =          0x1e,
  160         MFI_STAT_MAX_SPARES_EXCEEDED =          0x1f,
  161         MFI_STAT_MEMORY_NOT_AVAILABLE =         0x20,
  162         MFI_STAT_MFC_HW_ERROR =                 0x21,
  163         MFI_STAT_NO_HW_PRESENT =                0x22,
  164         MFI_STAT_NOT_FOUND =                    0x23,
  165         MFI_STAT_NOT_IN_ENCL =                  0x24,
  166         MFI_STAT_PD_CLEAR_IN_PROGRESS =         0x25,
  167         MFI_STAT_PD_TYPE_WRONG =                0x26,
  168         MFI_STAT_PR_DISABLED =                  0x27,
  169         MFI_STAT_ROW_INDEX_INVALID =            0x28,
  170         MFI_STAT_SAS_CONFIG_INVALID_ACTION =    0x29,
  171         MFI_STAT_SAS_CONFIG_INVALID_DATA =      0x2a,
  172         MFI_STAT_SAS_CONFIG_INVALID_PAGE =      0x2b,
  173         MFI_STAT_SAS_CONFIG_INVALID_TYPE =      0x2c,
  174         MFI_STAT_SCSI_DONE_WITH_ERROR =         0x2d,
  175         MFI_STAT_SCSI_IO_FAILED =               0x2e,
  176         MFI_STAT_SCSI_RESERVATION_CONFLICT =    0x2f,
  177         MFI_STAT_SHUTDOWN_FAILED =              0x30,
  178         MFI_STAT_TIME_NOT_SET =                 0x31,
  179         MFI_STAT_WRONG_STATE =                  0x32,
  180         MFI_STAT_LD_OFFLINE =                   0x33,
  181         MFI_STAT_PEER_NOTIFICATION_REJECTED =   0x34,
  182         MFI_STAT_PEER_NOTIFICATION_FAILED =     0x35,
  183         MFI_STAT_RESERVATION_IN_PROGRESS =      0x36,
  184         MFI_STAT_I2C_ERRORS_DETECTED =          0x37,
  185         MFI_STAT_PCI_ERRORS_DETECTED =          0x38,
  186         MFI_STAT_INVALID_STATUS =               0xff
  187 } mfi_status_t;
  188 
  189 typedef enum {
  190         MFI_EVT_CLASS_DEBUG =                   -2,
  191         MFI_EVT_CLASS_PROGRESS =                -1,
  192         MFI_EVT_CLASS_INFO =                    0,
  193         MFI_EVT_CLASS_WARNING =                 1,
  194         MFI_EVT_CLASS_CRITICAL =                2,
  195         MFI_EVT_CLASS_FATAL =                   3,
  196         MFI_EVT_CLASS_DEAD =                    4
  197 } mfi_evt_class_t;
  198 
  199 typedef enum {
  200         MFI_EVT_LOCALE_LD =                     0x0001,
  201         MFI_EVT_LOCALE_PD =                     0x0002,
  202         MFI_EVT_LOCALE_ENCL =                   0x0004,
  203         MFI_EVT_LOCALE_BBU =                    0x0008,
  204         MFI_EVT_LOCALE_SAS =                    0x0010,
  205         MFI_EVT_LOCALE_CTRL =                   0x0020,
  206         MFI_EVT_LOCALE_CONFIG =                 0x0040,
  207         MFI_EVT_LOCALE_CLUSTER =                0x0080,
  208         MFI_EVT_LOCALE_ALL =                    0xffff
  209 } mfi_evt_locale_t;
  210 
  211 typedef enum {
  212         MR_EVT_ARGS_NONE =                      0x00,
  213         MR_EVT_ARGS_CDB_SENSE,
  214         MR_EVT_ARGS_LD,
  215         MR_EVT_ARGS_LD_COUNT,
  216         MR_EVT_ARGS_LD_LBA,
  217         MR_EVT_ARGS_LD_OWNER,
  218         MR_EVT_ARGS_LD_LBA_PD_LBA,
  219         MR_EVT_ARGS_LD_PROG,
  220         MR_EVT_ARGS_LD_STATE,
  221         MR_EVT_ARGS_LD_STRIP,
  222         MR_EVT_ARGS_PD,
  223         MR_EVT_ARGS_PD_ERR,
  224         MR_EVT_ARGS_PD_LBA,
  225         MR_EVT_ARGS_PD_LBA_LD,
  226         MR_EVT_ARGS_PD_PROG,
  227         MR_EVT_ARGS_PD_STATE,
  228         MR_EVT_ARGS_PCI,
  229         MR_EVT_ARGS_RATE,
  230         MR_EVT_ARGS_STR,
  231         MR_EVT_ARGS_TIME,
  232         MR_EVT_ARGS_ECC
  233 } mfi_evt_args;
  234 
  235 /* driver definitions */
  236 #define MFI_MAX_PD_CHANNELS                     2
  237 #define MFI_MAX_PD_ARRAY                        32
  238 #define MFI_MAX_LD_CHANNELS                     2
  239 #define MFI_MAX_CHANNELS        (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS)
  240 #define MFI_MAX_CHANNEL_DEVS                    128
  241 #define MFI_DEFAULT_ID                          -1
  242 #define MFI_MAX_LUN                             8
  243 #define MFI_MAX_LD                              64
  244 #define MFI_MAX_SPAN                            8
  245 #define MFI_MAX_ARRAY_DEDICATED                 16
  246 
  247 /* sense buffer */
  248 struct mfi_sense {
  249         uint8_t                 mse_data[MFI_SENSE_SIZE];
  250 } __packed;
  251 
  252 /* scatter gather elements */
  253 struct mfi_sg32 {
  254         uint32_t                addr;
  255         uint32_t                len;
  256 } __packed;
  257 
  258 struct mfi_sg64 {
  259         uint64_t                addr;
  260         uint32_t                len;
  261 } __packed;
  262 
  263 union mfi_sgl {
  264         struct mfi_sg32         sg32[1];
  265         struct mfi_sg64         sg64[1];
  266 } __packed;
  267 
  268 /* message frame */
  269 struct mfi_frame_header {
  270         uint8_t                 mfh_cmd;
  271         uint8_t                 mfh_sense_len;
  272         uint8_t                 mfh_cmd_status;
  273         uint8_t                 mfh_scsi_status;
  274         uint8_t                 mfh_target_id;
  275         uint8_t                 mfh_lun_id;
  276         uint8_t                 mfh_cdb_len;
  277         uint8_t                 mfh_sg_count;
  278         uint32_t                mfh_context;
  279         uint32_t                mfh_pad0;
  280         uint16_t                mfh_flags;
  281         uint16_t                mfh_timeout;
  282         uint32_t                mfh_data_len;
  283 } __packed;
  284 
  285 union mfi_sgl_frame {
  286         struct mfi_sg32         sge32[8];
  287         struct mfi_sg64         sge64[5];
  288 
  289 } __packed;
  290 
  291 struct mfi_init_frame {
  292         struct mfi_frame_header mif_header;
  293         uint32_t                mif_qinfo_new_addr_lo;
  294         uint32_t                mif_qinfo_new_addr_hi;
  295         uint32_t                mif_qinfo_old_addr_lo;
  296         uint32_t                mif_qinfo_old_addr_hi;
  297         uint32_t                mif_reserved[6];
  298 } __packed;
  299 
  300 /* queue init structure */
  301 struct mfi_init_qinfo {
  302         uint32_t                miq_flags;
  303         uint32_t                miq_rq_entries;
  304         uint32_t                miq_rq_addr_lo;
  305         uint32_t                miq_rq_addr_hi;
  306         uint32_t                miq_pi_addr_lo;
  307         uint32_t                miq_pi_addr_hi;
  308         uint32_t                miq_ci_addr_lo;
  309         uint32_t                miq_ci_addr_hi;
  310 } __packed;
  311 
  312 #define MFI_IO_FRAME_SIZE       40
  313 struct mfi_io_frame {
  314         struct mfi_frame_header mif_header;
  315         uint32_t                mif_sense_addr_lo;
  316         uint32_t                mif_sense_addr_hi;
  317         uint32_t                mif_lba_lo;
  318         uint32_t                mif_lba_hi;
  319         union mfi_sgl           mif_sgl;
  320 } __packed;
  321 
  322 #define MFI_PASS_FRAME_SIZE     48
  323 struct mfi_pass_frame {
  324         struct mfi_frame_header mpf_header;
  325         uint32_t                mpf_sense_addr_lo;
  326         uint32_t                mpf_sense_addr_hi;
  327         uint8_t                 mpf_cdb[16];
  328         union mfi_sgl           mpf_sgl;
  329 } __packed;
  330 
  331 #define MFI_DCMD_FRAME_SIZE     40
  332 struct mfi_dcmd_frame {
  333         struct mfi_frame_header mdf_header;
  334         uint32_t                mdf_opcode;
  335         uint8_t                 mdf_mbox[MFI_MBOX_SIZE];
  336         union mfi_sgl           mdf_sgl;
  337 } __packed;
  338 
  339 struct mfi_abort_frame {
  340         struct mfi_frame_header maf_header;
  341         uint32_t                maf_abort_context;
  342         uint32_t                maf_pad;
  343         uint32_t                maf_abort_mfi_addr_lo;
  344         uint32_t                maf_abort_mfi_addr_hi;
  345         uint32_t                maf_reserved[6];
  346 } __packed;
  347 
  348 struct mfi_smp_frame {
  349         struct mfi_frame_header msf_header;
  350         uint64_t                msf_sas_addr;
  351         union {
  352                 struct mfi_sg32 sg32[2];
  353                 struct mfi_sg64 sg64[2];
  354         }                       msf_sgl;
  355 } __packed;
  356 
  357 struct mfi_stp_frame {
  358         struct mfi_frame_header msf_header;
  359         uint16_t                msf_fis[10];
  360         uint32_t                msf_stp_flags;
  361         union {
  362                 struct mfi_sg32 sg32[2];
  363                 struct mfi_sg64 sg64[2];
  364         }                       msf_sgl;
  365 } __packed;
  366 
  367 union mfi_frame {
  368         struct mfi_frame_header mfr_header;
  369         struct mfi_init_frame   mfr_init;
  370         struct mfi_io_frame     mfr_io;
  371         struct mfi_pass_frame   mfr_pass;
  372         struct mfi_dcmd_frame   mfr_dcmd;
  373         struct mfi_abort_frame  mfr_abort;
  374         struct mfi_smp_frame    mfr_smp;
  375         struct mfi_stp_frame    mfr_stp;
  376         uint8_t                 mfr_bytes[MFI_FRAME_SIZE];
  377 };
  378 
  379 union mfi_evt_class_locale {
  380         struct {
  381                 uint16_t        locale;
  382                 uint8_t         reserved;
  383                 int8_t          class;
  384         } __packed              mec_members;
  385 
  386         uint32_t                mec_word;
  387 } __packed;
  388 
  389 struct mfi_evt_log_info {
  390         uint32_t                mel_newest_seq_num;
  391         uint32_t                mel_oldest_seq_num;
  392         uint32_t                mel_clear_seq_num;
  393         uint32_t                mel_shutdown_seq_num;
  394         uint32_t                mel_boot_seq_num;
  395 } __packed;
  396 
  397 struct mfi_progress {
  398         uint16_t                mp_progress;
  399         uint16_t                mp_elapsed_seconds;
  400 } __packed;
  401 
  402 struct mfi_evtarg_ld {
  403         uint16_t                mel_target_id;
  404         uint8_t                 mel_ld_index;
  405         uint8_t                 mel_reserved;
  406 } __packed;
  407 
  408 struct mfi_evtarg_pd {
  409         uint16_t                mep_device_id;
  410         uint8_t                 mep_encl_index;
  411         uint8_t                 mep_slot_number;
  412 } __packed;
  413 
  414 struct mfi_evt_detail {
  415         uint32_t                                med_seq_num;
  416         uint32_t                                med_time_stamp;
  417         uint32_t                                med_code;
  418         union mfi_evt_class_locale              med_cl;
  419         uint8_t                                 med_arg_type;
  420         uint8_t                                 med_reserved1[15];
  421 
  422         union {
  423                 struct {
  424                         struct mfi_evtarg_pd    pd;
  425                         uint8_t                 cdb_length;
  426                         uint8_t                 sense_length;
  427                         uint8_t                 reserved[2];
  428                         uint8_t                 cdb[16];
  429                         uint8_t                 sense[64];
  430                 } __packed                      cdb_sense;
  431 
  432                 struct mfi_evtarg_ld            ld;
  433 
  434                 struct {
  435                         struct mfi_evtarg_ld    ld;
  436                         uint64_t                count;
  437                 } __packed                      ld_count;
  438 
  439                 struct {
  440                         uint64_t                lba;
  441                         struct mfi_evtarg_ld    ld;
  442                 } __packed                      ld_lba;
  443 
  444                 struct {
  445                         struct mfi_evtarg_ld    ld;
  446                         uint32_t                prev_owner;
  447                         uint32_t                new_owner;
  448                 } __packed                      ld_owner;
  449 
  450                 struct {
  451                         uint64_t                ld_lba;
  452                         uint64_t                pd_lba;
  453                         struct mfi_evtarg_ld    ld;
  454                         struct mfi_evtarg_pd    pd;
  455                 } __packed                      ld_lba_pd_lba;
  456 
  457                 struct {
  458                         struct mfi_evtarg_ld    ld;
  459                         struct mfi_progress     prog;
  460                 } __packed                      ld_prog;
  461 
  462                 struct {
  463                         struct mfi_evtarg_ld    ld;
  464                         uint32_t                prev_state;
  465                         uint32_t                new_state;
  466                 } __packed                      ld_state;
  467 
  468                 struct {
  469                         uint64_t                strip;
  470                         struct mfi_evtarg_ld    ld;
  471                 } __packed                      ld_strip;
  472 
  473                 struct mfi_evtarg_pd            pd;
  474 
  475                 struct {
  476                         struct mfi_evtarg_pd    pd;
  477                         uint32_t                err;
  478                 } __packed                      pd_err;
  479 
  480                 struct {
  481                         uint64_t                lba;
  482                         struct mfi_evtarg_pd    pd;
  483                 } __packed                      pd_lba;
  484 
  485                 struct {
  486                         uint64_t                lba;
  487                         struct mfi_evtarg_pd    pd;
  488                         struct mfi_evtarg_ld    ld;
  489                 } __packed                      pd_lba_ld;
  490 
  491                 struct {
  492                         struct mfi_evtarg_pd    pd;
  493                         struct mfi_progress     prog;
  494                 } __packed                      pd_prog;
  495 
  496                 struct {
  497                         struct mfi_evtarg_pd    pd;
  498                         uint32_t                prev_state;
  499                         uint32_t                new_state;
  500                 } __packed                      pd_state;
  501 
  502                 struct {
  503                         uint16_t                vendor_id;
  504                         uint16_t                device_id;
  505                         uint16_t                subvendor_id;
  506                         uint16_t                subdevice_id;
  507                 } __packed                      pci;
  508 
  509                 uint32_t                        rate;
  510                 char                            str[96];
  511 
  512                 struct {
  513                         uint32_t                rtc;
  514                         uint32_t                elapsed_seconds;
  515                 } __packed                      time;
  516 
  517                 struct {
  518                         uint32_t                ecar;
  519                         uint32_t                elog;
  520                         char                    str[64];
  521                 } __packed                      ecc;
  522 
  523                 uint8_t                         b[96];
  524                 uint16_t                        s[48];
  525                 uint32_t                        w[24];
  526                 uint64_t                        d[12];
  527         }                                       args;
  528 
  529         char                                    med_description[128];
  530 } __packed;
  531 
  532 /* controller properties from mfi_ctrl_info */
  533 struct mfi_ctrl_props {
  534         uint16_t                mcp_seq_num;
  535         uint16_t                mcp_pred_fail_poll_interval;
  536         uint16_t                mcp_intr_throttle_cnt;
  537         uint16_t                mcp_intr_throttle_timeout;
  538         uint8_t                 mcp_rebuild_rate;
  539         uint8_t                 mcp_patrol_read_rate;
  540         uint8_t                 mcp_bgi_rate;
  541         uint8_t                 mcp_cc_rate;
  542         uint8_t                 mcp_recon_rate;
  543         uint8_t                 mcp_cache_flush_interval;
  544         uint8_t                 mcp_spinup_drv_cnt;
  545         uint8_t                 mcp_spinup_delay;
  546         uint8_t                 mcp_cluster_enable;
  547         uint8_t                 mcp_coercion_mode;
  548         uint8_t                 mcp_alarm_enable;
  549         uint8_t                 mcp_disable_auto_rebuild;
  550         uint8_t                 mcp_disable_battery_warn;
  551         uint8_t                 mcp_ecc_bucket_size;
  552         uint16_t                mcp_ecc_bucket_leak_rate;
  553         uint8_t                 mcp_restore_hotspare_on_insertion;
  554         uint8_t                 mcp_expose_encl_devices;
  555         uint8_t                 mcp_reserved[38];
  556 } __packed;
  557 
  558 /* pci info */
  559 struct mfi_info_pci {
  560         uint16_t                mip_vendor;
  561         uint16_t                mip_device;
  562         uint16_t                mip_subvendor;
  563         uint16_t                mip_subdevice;
  564         uint8_t                 mip_reserved[24];
  565 } __packed;
  566 
  567 /* host interface infor */
  568 struct mfi_info_host {
  569         uint8_t                 mih_type;
  570 #define MFI_INFO_HOST_PCIX      0x01
  571 #define MFI_INFO_HOST_PCIE      0x02
  572 #define MFI_INFO_HOST_ISCSI     0x04
  573 #define MFI_INFO_HOST_SAS3G     0x08
  574         uint8_t                 mih_reserved[6];
  575         uint8_t                 mih_port_count;
  576         uint64_t                mih_port_addr[8];
  577 } __packed;
  578 
  579 /* device  interface info */
  580 struct mfi_info_device {
  581         uint8_t                 mid_type;
  582 #define MFI_INFO_DEV_SPI        0x01
  583 #define MFI_INFO_DEV_SAS3G      0x02
  584 #define MFI_INFO_DEV_SATA1      0x04
  585 #define MFI_INFO_DEV_SATA3G     0x08
  586         uint8_t                 mid_reserved[6];
  587         uint8_t                 mid_port_count;
  588         uint64_t                mid_port_addr[8];
  589 } __packed;
  590 
  591 /* firmware component info */
  592 struct mfi_info_component {
  593         char                    mic_name[8];
  594         char                    mic_version[32];
  595         char                    mic_build_date[16];
  596         char                    mic_build_time[16];
  597 } __packed;
  598 
  599 /* controller info from MFI_DCMD_CTRL_GETINFO. */
  600 struct mfi_ctrl_info {
  601         struct mfi_info_pci     mci_pci;
  602         struct mfi_info_host    mci_host;
  603         struct mfi_info_device  mci_device;
  604 
  605         /* Firmware components that are present and active. */
  606         uint32_t                mci_image_check_word;
  607         uint32_t                mci_image_component_count;
  608         struct mfi_info_component mci_image_component[8];
  609 
  610         /* Firmware components that have been flashed but are inactive */
  611         uint32_t                mci_pending_image_component_count;
  612         struct mfi_info_component mci_pending_image_component[8];
  613 
  614         uint8_t                 mci_max_arms;
  615         uint8_t                 mci_max_spans;
  616         uint8_t                 mci_max_arrays;
  617         uint8_t                 mci_max_lds;
  618         char                    mci_product_name[80];
  619         char                    mci_serial_number[32];
  620         uint32_t                mci_hw_present;
  621 #define MFI_INFO_HW_BBU         0x01
  622 #define MFI_INFO_HW_ALARM       0x02
  623 #define MFI_INFO_HW_NVRAM       0x04
  624 #define MFI_INFO_HW_UART        0x08
  625         uint32_t                mci_current_fw_time;
  626         uint16_t                mci_max_cmds;
  627         uint16_t                mci_max_sg_elements;
  628         uint32_t                mci_max_request_size;
  629         uint16_t                mci_lds_present;
  630         uint16_t                mci_lds_degraded;
  631         uint16_t                mci_lds_offline;
  632         uint16_t                mci_pd_present;
  633         uint16_t                mci_pd_disks_present;
  634         uint16_t                mci_pd_disks_pred_failure;
  635         uint16_t                mci_pd_disks_failed;
  636         uint16_t                mci_nvram_size;
  637         uint16_t                mci_memory_size;
  638         uint16_t                mci_flash_size;
  639         uint16_t                mci_ram_correctable_errors;
  640         uint16_t                mci_ram_uncorrectable_errors;
  641         uint8_t                 mci_cluster_allowed;
  642         uint8_t                 mci_cluster_active;
  643         uint16_t                mci_max_strips_per_io;
  644 
  645         uint32_t                mci_raid_levels;
  646 #define MFI_INFO_RAID_0         0x01
  647 #define MFI_INFO_RAID_1         0x02
  648 #define MFI_INFO_RAID_5         0x04
  649 #define MFI_INFO_RAID_1E        0x08
  650 #define MFI_INFO_RAID_6         0x10
  651 
  652         uint32_t                mci_adapter_ops;
  653 #define MFI_INFO_AOPS_RBLD_RATE         0x0001          
  654 #define MFI_INFO_AOPS_CC_RATE           0x0002
  655 #define MFI_INFO_AOPS_BGI_RATE          0x0004
  656 #define MFI_INFO_AOPS_RECON_RATE        0x0008
  657 #define MFI_INFO_AOPS_PATROL_RATE       0x0010
  658 #define MFI_INFO_AOPS_ALARM_CONTROL     0x0020
  659 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040
  660 #define MFI_INFO_AOPS_BBU               0x0080
  661 #define MFI_INFO_AOPS_SPANNING_ALLOWED  0x0100
  662 #define MFI_INFO_AOPS_DEDICATED_SPARES  0x0200
  663 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400
  664 #define MFI_INFO_AOPS_FOREIGN_IMPORT    0x0800
  665 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC   0x1000
  666 #define MFI_INFO_AOPS_MIXED_ARRAY       0x2000
  667 #define MFI_INFO_AOPS_GLOBAL_SPARES     0x4000
  668 
  669         uint32_t                mci_ld_ops;
  670 #define MFI_INFO_LDOPS_READ_POLICY      0x01
  671 #define MFI_INFO_LDOPS_WRITE_POLICY     0x02
  672 #define MFI_INFO_LDOPS_IO_POLICY        0x04
  673 #define MFI_INFO_LDOPS_ACCESS_POLICY    0x08
  674 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10
  675 
  676         struct {
  677                 uint8_t         min;
  678                 uint8_t         max;
  679                 uint8_t         reserved[2];
  680         } __packed              mci_stripe_sz_ops;
  681 
  682         uint32_t                mci_pd_ops;
  683 #define MFI_INFO_PDOPS_FORCE_ONLINE     0x01
  684 #define MFI_INFO_PDOPS_FORCE_OFFLINE    0x02
  685 #define MFI_INFO_PDOPS_FORCE_REBUILD    0x04
  686 
  687         uint32_t                mci_pd_mix_support;
  688 #define MFI_INFO_PDMIX_SAS              0x01
  689 #define MFI_INFO_PDMIX_SATA             0x02
  690 #define MFI_INFO_PDMIX_ENCL             0x04
  691 #define MFI_INFO_PDMIX_LD               0x08
  692 #define MFI_INFO_PDMIX_SATA_CLUSTER     0x10
  693 
  694         uint8_t                 mci_ecc_bucket_count;
  695         uint8_t                 mci_reserved2[11];
  696         struct mfi_ctrl_props   mci_properties;
  697         char                    mci_package_version[0x60];
  698         uint8_t                 mci_pad[0x800 - 0x6a0];
  699 } __packed;
  700 
  701 /* logical disk info from MR_DCMD_LD_GET_LIST */
  702 struct mfi_ld {
  703         uint8_t                 mld_target;
  704         uint8_t                 mld_res;
  705         uint16_t                mld_seq;
  706 } __packed;
  707 
  708 struct mfi_ld_list {
  709         uint32_t                mll_no_ld;
  710         uint32_t                mll_res;
  711         struct {
  712                 struct mfi_ld   mll_ld;
  713                 uint8_t         mll_state;
  714 #define MFI_LD_OFFLINE                  0x00
  715 #define MFI_LD_PART_DEGRADED            0x01
  716 #define MFI_LD_DEGRADED                 0x02
  717 #define MFI_LD_ONLINE                   0x03
  718                 uint8_t         mll_res2;
  719                 uint8_t         mll_res3;
  720                 uint8_t         mll_res4;
  721                 u_quad_t        mll_size;
  722         } mll_list[MFI_MAX_LD];
  723 } __packed;
  724 
  725 /* logicl disk details from MR_DCMD_LD_GET_INFO */
  726 struct mfi_ld_prop {
  727         struct mfi_ld           mlp_ld;
  728         char                    mlp_name[16];
  729         uint8_t                 mlp_cache_policy;
  730         uint8_t                 mlp_acces_policy;
  731         uint8_t                 mlp_diskcache_policy;
  732         uint8_t                 mlp_cur_cache_policy;
  733         uint8_t                 mlp_disable_bgi;
  734         uint8_t                 mlp_res[7];
  735 } __packed;
  736 
  737 struct mfi_ld_parm {
  738         uint8_t                 mpa_pri_raid;   /* SNIA DDF PRL */
  739 #define MFI_DDF_PRL_RAID0       0x00
  740 #define MFI_DDF_PRL_RAID1       0x01
  741 #define MFI_DDF_PRL_RAID3       0x03
  742 #define MFI_DDF_PRL_RAID4       0x04
  743 #define MFI_DDF_PRL_RAID5       0x05
  744 #define MFI_DDF_PRL_RAID1E      0x11
  745 #define MFI_DDF_PRL_JBOD        0x0f
  746 #define MFI_DDF_PRL_CONCAT      0x1f
  747 #define MFI_DDF_PRL_RAID5E      0x15
  748 #define MFI_DDF_PRL_RAID5EE     0x25
  749 #define MFI_DDF_PRL_RAID6       0x16
  750         uint8_t                 mpa_raid_qual;  /* SNIA DDF RLQ */
  751         uint8_t                 mpa_sec_raid;   /* SNIA DDF SRL */
  752 #define MFI_DDF_SRL_STRIPED     0x00
  753 #define MFI_DDF_SRL_MIRRORED    0x01
  754 #define MFI_DDF_SRL_CONCAT      0x02
  755 #define MFI_DDF_SRL_SPANNED     0x03
  756         uint8_t                 mpa_stripe_size;
  757         uint8_t                 mpa_no_drv_per_span;
  758         uint8_t                 mpa_span_depth;
  759         uint8_t                 mpa_state;
  760         uint8_t                 mpa_init_state;
  761         uint8_t                 mpa_res[24];
  762 } __packed;
  763 
  764 struct mfi_ld_span {
  765         u_quad_t                mls_start_block;
  766         u_quad_t                mls_no_blocks;
  767         uint16_t                mls_index;
  768         uint8_t                 mls_res[6];
  769 } __packed;
  770 
  771 struct mfi_ld_cfg {
  772         struct mfi_ld_prop      mlc_prop;
  773         struct mfi_ld_parm      mlc_parm;
  774         struct mfi_ld_span      mlc_span[MFI_MAX_SPAN];
  775 } __packed;
  776 
  777 struct mfi_ld_progress {
  778         uint32_t                mlp_in_prog;
  779 #define MFI_LD_PROG_CC          0x01
  780 #define MFI_LD_PROG_BGI         0x02
  781 #define MFI_LD_PROG_FGI         0x04
  782 #define MFI_LD_PROG_RECONSTRUCT 0x08
  783         struct mfi_progress     mlp_cc;
  784         struct mfi_progress     mlp_bgi;
  785         struct mfi_progress     mlp_fgi;
  786         struct mfi_progress     mlp_reconstruct;
  787         struct mfi_progress     mlp_res[4];
  788 } __packed;
  789 
  790 struct mfi_ld_details {
  791         struct mfi_ld_cfg       mld_cfg;
  792         u_quad_t                mld_size;
  793         struct mfi_ld_progress  mld_progress;
  794         uint16_t                mld_clust_own_id;
  795         uint8_t                 mld_res1;
  796         uint8_t                 mld_res2;
  797         uint8_t                 mld_inq_page83[64];
  798         uint8_t                 mld_res[16];
  799 } __packed;
  800 
  801 /* physical disk info from MR_DCMD_PD_GET_LIST */
  802 struct mfi_pd_address {
  803         uint16_t                mpa_pd_id;
  804         uint16_t                mpa_enc_id;
  805         uint8_t                 mpa_enc_index;
  806         uint8_t                 mpa_enc_slot;
  807         uint8_t                 mpa_scsi_type;
  808         uint8_t                 mpa_port;
  809         u_quad_t                mpa_sas_address[2];
  810 } __packed;
  811 
  812 struct mfi_pd_list {
  813         uint32_t                mpl_size;
  814         uint32_t                mpl_no_pd;
  815         struct mfi_pd_address   mpl_address[1];
  816 } __packed;
  817 #define MFI_PD_LIST_SIZE        (256 * sizeof(struct mfi_pd_address) + 8)
  818 
  819 struct mfi_pd {
  820         uint16_t                mfp_id;
  821         uint16_t                mfp_seq;
  822 } __packed;
  823 
  824 struct mfi_pd_progress {
  825         uint32_t                mfp_in_prog;
  826 #define MFI_PD_PROG_RBLD        0x01
  827 #define MFI_PD_PROG_PR          0x02
  828 #define MFI_PD_PROG_CLEAR       0x04
  829         struct mfi_progress     mfp_rebuild;
  830         struct mfi_progress     mfp_patrol_read;
  831         struct mfi_progress     mfp_clear;
  832         struct mfi_progress     mfp_res[4];
  833 } __packed;
  834 
  835 struct mfi_pd_details {
  836         struct mfi_pd           mpd_pd;
  837         uint8_t                 mpd_inq_data[96];
  838         uint8_t                 mpd_inq_page83[64];
  839         uint8_t                 mpd_no_support;
  840         uint8_t                 mpd_scsy_type;
  841         uint8_t                 mpd_port;
  842         uint8_t                 mpd_speed;
  843         uint32_t                mpd_mediaerr_cnt;
  844         uint32_t                mpd_othererr_cnt;
  845         uint32_t                mpd_predfail_cnt;
  846         uint32_t                mpd_last_pred_event;
  847         uint16_t                mpd_fw_state;
  848         uint8_t                 mpd_rdy_for_remove;
  849         uint8_t                 mpd_link_speed;
  850         uint32_t                mpd_ddf_state;
  851 #define MFI_DDF_GUID_FORCED     0x01
  852 #define MFI_DDF_PART_OF_VD      0x02
  853 #define MFI_DDF_GLOB_HOTSPARE   0x04
  854 #define MFI_DDF_HOTSPARE        0x08
  855 #define MFI_DDF_FOREIGN         0x10
  856 #define MFI_DDF_TYPE_MASK       0xf000
  857 #define MFI_DDF_TYPE_UNKNOWN    0x0000
  858 #define MFI_DDF_TYPE_PAR_SCSI   0x1000
  859 #define MFI_DDF_TYPE_SAS        0x2000
  860 #define MFI_DDF_TYPE_SATA       0x3000
  861 #define MFI_DDF_TYPE_FC         0x4000
  862         struct {
  863                 uint8_t         mpp_cnt;
  864                 uint8_t         mpp_severed;
  865                 uint8_t         mpp_res[6];
  866                 u_quad_t        mpp_sas_addr[4];
  867         } __packed mpd_path;
  868         u_quad_t                mpd_size;
  869         u_quad_t                mpd_no_coerce_size;
  870         u_quad_t                mpd_coerce_size;
  871         uint16_t                mpd_enc_id;
  872         uint8_t                 mpd_enc_idx;
  873         uint8_t                 mpd_enc_slot;
  874         struct mfi_pd_progress  mpd_progress;
  875         uint8_t                 mpd_bblock_full;
  876         uint8_t                 mpd_unusable;
  877         uint8_t                 mpd_res[218]; /* size is 512 */
  878 } __packed;
  879 
  880 /* array configuration from MD_DCMD_CONF_GET */
  881 struct mfi_array {
  882         u_quad_t                mar_smallest_pd;
  883         uint8_t                 mar_no_disk;
  884         uint8_t                 mar_res1;
  885         uint16_t                mar_array_ref;
  886         uint8_t                 mar_res2[20];
  887         struct {
  888                 struct mfi_pd   mar_pd;
  889                 uint16_t        mar_pd_state;
  890 #define MFI_PD_UNCONFIG_GOOD    0x00
  891 #define MFI_PD_UNCONFIG_BAD     0x01
  892 #define MFI_PD_HOTSPARE         0x02
  893 #define MFI_PD_OFFLINE          0x10
  894 #define MFI_PD_FAILED           0x11
  895 #define MFI_PD_REBUILD          0x14
  896 #define MFI_PD_ONLINE           0x18
  897                 uint8_t         mar_enc_pd;
  898                 uint8_t         mar_enc_slot;
  899         } pd[MFI_MAX_PD_ARRAY];
  900 } __packed;
  901 
  902 struct mfi_hotspare {
  903         struct mfi_pd   mhs_pd;
  904         uint8_t         mhs_type;
  905 #define MFI_PD_HS_DEDICATED     0x01
  906 #define MFI_PD_HS_REVERTIBLE    0x02
  907 #define MFI_PD_HS_ENC_AFFINITY  0x04
  908         uint8_t         mhs_res[2];
  909         uint8_t         mhs_array_max;
  910         uint16_t        mhs_array_ref[MFI_MAX_ARRAY_DEDICATED];
  911 } __packed;
  912 
  913 struct mfi_conf {
  914         uint32_t                mfc_size;
  915         uint16_t                mfc_no_array;
  916         uint16_t                mfc_array_size;
  917         uint16_t                mfc_no_ld;
  918         uint16_t                mfc_ld_size;
  919         uint16_t                mfc_no_hs;
  920         uint16_t                mfc_hs_size;
  921         uint8_t                 mfc_res[16];
  922         /*
  923          * XXX this is a ridiculous hack and does not reflect reality
  924          * Structures are actually indexed and therefore need pointer
  925          * math to reach.  We need the size of this structure first so
  926          * call it with the size of this structure and then use the returned
  927          * values to allocate memory and do the transfer of the whole structure
  928          * then calculate pointers to each of these structures.
  929          */
  930         struct mfi_array        mfc_array[1];
  931         struct mfi_ld_cfg       mfc_ld[1];
  932         struct mfi_hotspare     mfc_hs[1];
  933 } __packed;

Cache object: 0b9ecf10ce8bb9844998d81f4c090b8a


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