Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/mfireg.h
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1 /* $OpenBSD: mfireg.h,v 1.52 2022/09/16 12:08:27 stsp Exp $ */ 2 /* 3 * Copyright (c) 2006 Marco Peereboom <marco@peereboom.us> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 /* management interface constants */ 19 #define MFI_MGMT_VD 0x01 20 #define MFI_MGMT_SD 0x02 21 22 /* generic constants */ 23 #define MFI_FRAME_SIZE 64 24 #define MFI_SENSE_SIZE 128 25 #define MFI_OSTS_INTR_VALID 0x00000002 /* valid interrupt */ 26 #define MFI_OSTS_PPC_INTR_VALID 0x80000000 27 #define MFI_OSTS_GEN2_INTR_VALID (0x00000001 | 0x00000004) 28 #define MFI_INVALID_CTX 0xffffffff 29 #define MFI_ENABLE_INTR 0x01 30 31 /* register offsets */ 32 #define MFI_IMSG0 0x10 /* inbound msg 0 */ 33 #define MFI_IMSG1 0x14 /* inbound msg 1 */ 34 #define MFI_OMSG0 0x18 /* outbound msg 0 */ 35 #define MFI_OMSG1 0x1c /* outbound msg 1 */ 36 #define MFI_IDB 0x20 /* inbound doorbell */ 37 #define MFI_ISTS 0x24 /* inbound intr stat */ 38 #define MFI_IMSK 0x28 /* inbound intr mask */ 39 #define MFI_ODB 0x2c /* outbound doorbell */ 40 #define MFI_OSTS 0x30 /* outbound intr stat */ 41 #define MFI_OMSK 0x34 /* outbound inter mask */ 42 #define MFI_IQP 0x40 /* inbound queue port */ 43 #define MFI_OQP 0x44 /* outbound queue port */ 44 #define MFI_ODC 0xa0 /* outbound doorbell clr */ 45 #define MFI_OSP 0xb0 /* outbound scratch pad */ 46 47 /* 48 * skinny specific changes 49 */ 50 #define MFI_SKINNY_IDB 0x00 /* Inbound doorbell is at 0x00 for skinny */ 51 #define MFI_IQPL 0x000000c0 52 #define MFI_IQPH 0x000000c4 53 #define MFI_OSTS_SKINNY_INTR_VALID 0x00000001 54 55 /* * firmware states */ 56 #define MFI_STATE_MASK 0xf0000000 57 #define MFI_STATE_UNDEFINED 0x00000000 58 #define MFI_STATE_BB_INIT 0x10000000 59 #define MFI_STATE_FW_INIT 0x40000000 60 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 61 #define MFI_STATE_FW_INIT_2 0x70000000 62 #define MFI_STATE_DEVICE_SCAN 0x80000000 63 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 64 #define MFI_STATE_FLUSH_CACHE 0xa0000000 65 #define MFI_STATE_READY 0xb0000000 66 #define MFI_STATE_OPERATIONAL 0xc0000000 67 #define MFI_STATE_FAULT 0xf0000000 68 #define MFI_STATE_MAXSGL_MASK 0x00ff0000 69 #define MFI_STATE_MAXCMD_MASK 0x0000ffff 70 71 /* command reset register */ 72 #define MFI_INIT_ABORT 0x00000000 73 #define MFI_INIT_READY 0x00000002 74 #define MFI_INIT_MFIMODE 0x00000004 75 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 76 #define MFI_INIT_HOTPLUG 0x00000010 77 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE 78 79 /* mfi Frame flags */ 80 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 81 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 82 #define MFI_FRAME_SGL32 0x0000 83 #define MFI_FRAME_SGL64 0x0002 84 #define MFI_FRAME_SENSE32 0x0000 85 #define MFI_FRAME_SENSE64 0x0004 86 #define MFI_FRAME_DIR_NONE 0x0000 87 #define MFI_FRAME_DIR_WRITE 0x0008 88 #define MFI_FRAME_DIR_READ 0x0010 89 #define MFI_FRAME_DIR_BOTH 0x0018 90 #define MFI_FRAME_IEEE 0x0020 91 92 /* mfi command opcodes */ 93 #define MFI_CMD_INIT 0x00 94 #define MFI_CMD_LD_READ 0x01 95 #define MFI_CMD_LD_WRITE 0x02 96 #define MFI_CMD_LD_SCSI_IO 0x03 97 #define MFI_CMD_PD_SCSI_IO 0x04 98 #define MFI_CMD_DCMD 0x05 99 #define MFI_CMD_ABORT 0x06 100 #define MFI_CMD_SMP 0x07 101 #define MFI_CMD_STP 0x08 102 103 #define MFI_PR_STATE_STOPPED 0 104 #define MFI_PR_STATE_READY 1 105 #define MFI_PR_STATE_ACTIVE 2 106 #define MFI_PR_STATE_ABORTED 0xff 107 108 #define MFI_PR_OPMODE_AUTO 0x00 109 #define MFI_PR_OPMODE_MANUAL 0x01 110 #define MFI_PR_OPMODE_DISABLED 0x02 111 112 /* direct commands */ 113 #define MR_DCMD_CTRL_GET_INFO 0x01010000 114 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 115 #define MR_FLUSH_CTRL_CACHE 0x01 116 #define MR_FLUSH_DISK_CACHE 0x02 117 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 118 #define MR_ENABLE_DRIVE_SPINDOWN 0x01 119 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 120 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 121 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 122 #define MR_DCMD_PR_GET_STATUS 0x01070100 123 #define MR_DCMD_PR_GET_PROPERTIES 0x01070200 124 #define MR_DCMD_PR_SET_PROPERTIES 0x01070300 125 #define MR_DCMD_PR_START 0x01070400 126 #define MR_DCMD_PR_STOP 0x01070500 127 #define MR_DCMD_TIME_SECS_GET 0x01080201 128 #define MR_DCMD_PD_GET_LIST 0x02010000 129 #define MR_DCMD_PD_GET_INFO 0x02020000 130 #define MR_DCMD_PD_SET_STATE 0x02030100 131 #define MR_DCMD_PD_REBUILD 0x02040100 132 #define MR_DCMD_PD_BLINK 0x02070100 133 #define MR_DCMD_PD_UNBLINK 0x02070200 134 #define MR_DCMD_PD_GET_ALLOWED_OPS_LIST 0x020a0100 135 #define MR_DCMD_LD_GET_LIST 0x03010000 136 #define MR_DCMD_LD_GET_INFO 0x03020000 137 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 138 #define MR_DCMD_LD_SET_PROPERTIES 0x03040000 139 #define MR_DCMD_LD_DELETE 0x03090000 140 #define MR_DCMD_CONF_GET 0x04010000 141 #define MR_DCMD_CFG_ADD 0x04020000 142 #define MR_DCMD_CFG_CLEAR 0x04030000 143 #define MR_DCMD_CFG_MAKE_SPARE 0x04040000 144 #define MR_DCMD_CFG_FOREIGN_SCAN 0x04060100 145 #define MR_DCMD_CFG_FOREIGN_CLEAR 0x04060500 146 #define MR_DCMD_BBU_GET_STATUS 0x05010000 147 #define MR_DCMD_BBU_GET_CAPACITY_INFO 0x05020000 148 #define MR_DCMD_BBU_GET_DESIGN_INFO 0x05030000 149 #define MR_DCMD_BBU_START_LEARN 0x05040000 150 #define MR_DCMD_BBU_GET_PROP 0x05050100 151 #define MR_DCMD_BBU_SET_PROP 0x05050200 152 #define MR_DCMD_CLUSTER 0x08000000 153 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 154 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 155 156 #define MR_DCMD_SPEAKER_GET 0x01030100 157 #define MR_DCMD_SPEAKER_ENABLE 0x01030200 158 #define MR_DCMD_SPEAKER_DISABLE 0x01030300 159 #define MR_DCMD_SPEAKER_SILENCE 0x01030400 160 #define MR_DCMD_SPEAKER_TEST 0x01030500 161 162 #define MR_LD_CACHE_WRITE_BACK 0x01 163 #define MR_LD_CACHE_WRITE_ADAPTIVE 0x02 164 #define MR_LD_CACHE_READ_AHEAD 0x04 165 #define MR_LD_CACHE_READ_ADAPTIVE 0x08 166 #define MR_LD_CACHE_WRITE_CACHE_BAD_BBU 0x10 167 #define MR_LD_CACHE_ALLOW_WRITE_CACHE 0x20 168 #define MR_LD_CACHE_ALLOW_READ_CACHE 0x40 169 170 #define MR_LD_DISK_CACHE_ENABLE 0x01 171 #define MR_LD_DISK_CACHE_DISABLE 0x02 172 173 /* mailbox bytes in direct command */ 174 #define MFI_MBOX_SIZE 12 175 176 union mfi_mbox { 177 uint8_t b[MFI_MBOX_SIZE]; 178 uint16_t s[6]; 179 uint32_t w[3]; 180 } __packed __aligned(4); 181 182 /* mfi completion codes */ 183 typedef enum { 184 MFI_STAT_OK = 0x00, 185 MFI_STAT_INVALID_CMD = 0x01, 186 MFI_STAT_INVALID_DCMD = 0x02, 187 MFI_STAT_INVALID_PARAMETER = 0x03, 188 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 189 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 190 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 191 MFI_STAT_APP_IN_USE = 0x07, 192 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 193 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 194 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 195 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 196 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 197 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 198 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 199 MFI_STAT_FLASH_BUSY = 0x0f, 200 MFI_STAT_FLASH_ERROR = 0x10, 201 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 202 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 203 MFI_STAT_FLASH_NOT_OPEN = 0x13, 204 MFI_STAT_FLASH_NOT_STARTED = 0x14, 205 MFI_STAT_FLUSH_FAILED = 0x15, 206 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 207 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 208 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 209 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 210 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 211 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 212 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 213 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 214 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 215 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 216 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 217 MFI_STAT_MFC_HW_ERROR = 0x21, 218 MFI_STAT_NO_HW_PRESENT = 0x22, 219 MFI_STAT_NOT_FOUND = 0x23, 220 MFI_STAT_NOT_IN_ENCL = 0x24, 221 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 222 MFI_STAT_PD_TYPE_WRONG = 0x26, 223 MFI_STAT_PR_DISABLED = 0x27, 224 MFI_STAT_ROW_INDEX_INVALID = 0x28, 225 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 226 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 227 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 228 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 229 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 230 MFI_STAT_SCSI_IO_FAILED = 0x2e, 231 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 232 MFI_STAT_SHUTDOWN_FAILED = 0x30, 233 MFI_STAT_TIME_NOT_SET = 0x31, 234 MFI_STAT_WRONG_STATE = 0x32, 235 MFI_STAT_LD_OFFLINE = 0x33, 236 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 237 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 238 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 239 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 240 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 241 MFI_STAT_INVALID_STATUS = 0xff 242 } mfi_status_t; 243 244 typedef enum { 245 MFI_EVT_CLASS_DEBUG = -2, 246 MFI_EVT_CLASS_PROGRESS = -1, 247 MFI_EVT_CLASS_INFO = 0, 248 MFI_EVT_CLASS_WARNING = 1, 249 MFI_EVT_CLASS_CRITICAL = 2, 250 MFI_EVT_CLASS_FATAL = 3, 251 MFI_EVT_CLASS_DEAD = 4 252 } mfi_evt_class_t; 253 254 typedef enum { 255 MFI_EVT_LOCALE_LD = 0x0001, 256 MFI_EVT_LOCALE_PD = 0x0002, 257 MFI_EVT_LOCALE_ENCL = 0x0004, 258 MFI_EVT_LOCALE_BBU = 0x0008, 259 MFI_EVT_LOCALE_SAS = 0x0010, 260 MFI_EVT_LOCALE_CTRL = 0x0020, 261 MFI_EVT_LOCALE_CONFIG = 0x0040, 262 MFI_EVT_LOCALE_CLUSTER = 0x0080, 263 MFI_EVT_LOCALE_ALL = 0xffff 264 } mfi_evt_locale_t; 265 266 #define MFI_EVT_ARGS_NONE 0x00 267 #define MFI_EVT_ARGS_CDB_SENSE 0x01 268 #define MFI_EVT_ARGS_LD 0x02 269 #define MFI_EVT_ARGS_LD_COUNT 0x03 270 #define MFI_EVT_ARGS_LD_LBA 0x04 271 #define MFI_EVT_ARGS_LD_OWNER 0x05 272 #define MFI_EVT_ARGS_LD_LBA_PD_LBA 0x06 273 #define MFI_EVT_ARGS_LD_PROG 0x07 274 #define MFI_EVT_ARGS_LD_STATE 0x08 275 #define MFI_EVT_ARGS_LD_STRIP 0x09 276 #define MFI_EVT_ARGS_PD 0x0a 277 #define MFI_EVT_ARGS_PD_ERR 0x0b 278 #define MFI_EVT_ARGS_PD_LBA 0x0c 279 #define MFI_EVT_ARGS_PD_LBA_LD 0x0d 280 #define MFI_EVT_ARGS_PD_PROG 0x0e 281 #define MFI_EVT_ARGS_PD_STATE 0x0f 282 #define MFI_EVT_ARGS_PCI 0x10 283 #define MFI_EVT_ARGS_RATE 0x11 284 #define MFI_EVT_ARGS_STR 0x12 285 #define MFI_EVT_ARGS_TIME 0x13 286 #define MFI_EVT_ARGS_ECC 0x14 287 #define MFI_EVT_ARGS_LD_PROP 0x15 288 #define MFI_EVT_ARGS_PD_SPARE 0x16 289 #define MFI_EVT_ARGS_PD_INDEX 0x17 290 #define MFI_EVT_ARGS_DIAG_PASS 0x18 291 #define MFI_EVT_ARGS_DIAG_FAIL 0x19 292 #define MFI_EVT_ARGS_PD_LBA_LBA 0x1a 293 #define MFI_EVT_ARGS_PORT_PHY 0x1b 294 #define MFI_EVT_ARGS_PD_MISSING 0x1c 295 #define MFI_EVT_ARGS_PD_ADDRESS 0x1d 296 #define MFI_EVT_ARGS_BITMAP 0x1e 297 #define MFI_EVT_ARGS_CONNECTOR 0x1f 298 #define MFI_EVT_ARGS_PD_PD 0x20 299 #define MFI_EVT_ARGS_PD_FRU 0x21 300 #define MFI_EVT_ARGS_PD_PATHINFO 0x22 301 #define MFI_EVT_ARGS_PD_POWER_STATE 0x23 302 #define MFI_EVT_ARGS_GENERIC 0x24 303 304 #define MFI_EVT_CFG_CLEARED 0x0004 305 #define MFI_EVT_LD_STATE_CHANGE 0x0051 306 #define MFI_EVT_PD_INSERTED 0x005b 307 #define MFI_EVT_PD_REMOVED 0x0070 308 #define MFI_EVT_PD_STATE_CHANGE 0x0072 309 #define MFI_EVT_LD_CREATED 0x008a 310 #define MFI_EVT_LD_DELETED 0x008b 311 #define MFI_EVT_FOREIGN_CFG_IMPORTED 0x00db 312 #define MFI_EVT_PD_REMOVED_EXT 0x00f8 313 #define MFI_EVT_PD_INSERTED_EXT 0x00f7 314 #define MFI_EVT_LD_OFFLINE 0x00fc 315 #define MFI_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 316 #define MFI_EVT_CTRL_PROP_CHANGED 0x012f 317 318 /* driver definitions */ 319 #define MFI_MAX_PD_CHANNELS 2 320 #define MFI_MAX_PD_ARRAY 32 321 #define MFI_MAX_LD_CHANNELS 2 322 #define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 323 #define MFI_MAX_CHANNEL_DEVS 128 324 #define MFI_DEFAULT_ID -1 325 #define MFI_MAX_LUN 8 326 #define MFI_MAX_LD 64 327 #define MFI_MAX_SPAN 8 328 #define MFI_MAX_ARRAY_DEDICATED 16 329 #define MFI_MAX_PD 256 330 331 /* sense buffer */ 332 struct mfi_sense { 333 uint8_t mse_data[MFI_SENSE_SIZE]; 334 } __packed; 335 336 /* scatter gather elements */ 337 struct mfi_sg32 { 338 uint32_t addr; 339 uint32_t len; 340 } __packed; 341 342 struct mfi_sg64 { 343 uint64_t addr; 344 uint32_t len; 345 } __packed; 346 347 struct mfi_sg_skinny { 348 uint64_t addr; 349 uint32_t len; 350 uint32_t flag; 351 } __packed; 352 353 union mfi_sgl { 354 struct mfi_sg32 sg32[1]; 355 struct mfi_sg64 sg64[1]; 356 struct mfi_sg_skinny sg_skinny[1]; 357 } __packed; 358 359 /* message frame */ 360 struct mfi_frame_header { 361 uint8_t mfh_cmd; 362 uint8_t mfh_sense_len; 363 uint8_t mfh_cmd_status; 364 uint8_t mfh_scsi_status; 365 uint8_t mfh_target_id; 366 uint8_t mfh_lun_id; 367 uint8_t mfh_cdb_len; 368 uint8_t mfh_sg_count; 369 uint32_t mfh_context; 370 uint32_t mfh_pad0; 371 uint16_t mfh_flags; 372 uint16_t mfh_timeout; 373 uint32_t mfh_data_len; 374 } __packed; 375 376 union mfi_sgl_frame { 377 struct mfi_sg32 sge32[8]; 378 struct mfi_sg64 sge64[5]; 379 380 } __packed; 381 382 struct mfi_init_frame { 383 struct mfi_frame_header mif_header; 384 uint64_t mif_qinfo_new_addr; 385 uint64_t mif_qinfo_old_addr; 386 uint32_t mif_reserved[6]; 387 } __packed; 388 389 /* queue init structure */ 390 struct mfi_init_qinfo { 391 uint32_t miq_flags; 392 uint32_t miq_rq_entries; 393 uint64_t miq_rq_addr; 394 uint64_t miq_pi_addr; 395 uint64_t miq_ci_addr; 396 } __packed; 397 398 #define MFI_IO_FRAME_SIZE 40 399 struct mfi_io_frame { 400 struct mfi_frame_header mif_header; 401 uint64_t mif_sense_addr; 402 uint64_t mif_lba; 403 union mfi_sgl mif_sgl; 404 } __packed; 405 406 #define MFI_PASS_FRAME_SIZE 48 407 struct mfi_pass_frame { 408 struct mfi_frame_header mpf_header; 409 uint64_t mpf_sense_addr; 410 uint8_t mpf_cdb[16]; 411 union mfi_sgl mpf_sgl; 412 } __packed; 413 414 #define MFI_DCMD_FRAME_SIZE 40 415 struct mfi_dcmd_frame { 416 struct mfi_frame_header mdf_header; 417 uint32_t mdf_opcode; 418 union mfi_mbox mdf_mbox; 419 union mfi_sgl mdf_sgl; 420 } __packed; 421 422 struct mfi_abort_frame { 423 struct mfi_frame_header maf_header; 424 uint32_t maf_abort_context; 425 uint32_t maf_pad; 426 uint64_t maf_abort_mfi_addr; 427 uint32_t maf_reserved[6]; 428 } __packed; 429 430 struct mfi_smp_frame { 431 struct mfi_frame_header msf_header; 432 uint64_t msf_sas_addr; 433 union { 434 struct mfi_sg32 sg32[2]; 435 struct mfi_sg64 sg64[2]; 436 } msf_sgl; 437 } __packed; 438 439 struct mfi_stp_frame { 440 struct mfi_frame_header msf_header; 441 uint16_t msf_fis[10]; 442 uint32_t msf_stp_flags; 443 union { 444 struct mfi_sg32 sg32[2]; 445 struct mfi_sg64 sg64[2]; 446 } msf_sgl; 447 } __packed; 448 449 union mfi_frame { 450 struct mfi_frame_header mfr_header; 451 struct mfi_init_frame mfr_init; 452 struct mfi_io_frame mfr_io; 453 struct mfi_pass_frame mfr_pass; 454 struct mfi_dcmd_frame mfr_dcmd; 455 struct mfi_abort_frame mfr_abort; 456 struct mfi_smp_frame mfr_smp; 457 struct mfi_stp_frame mfr_stp; 458 uint8_t mfr_bytes[MFI_FRAME_SIZE]; 459 }; 460 461 union mfi_evt_class_locale { 462 struct { 463 uint16_t locale; 464 uint8_t reserved; 465 int8_t class; 466 } __packed mec_members; 467 468 uint32_t mec_word; 469 } __packed; 470 471 struct mfi_evt_log_info { 472 uint32_t mel_newest_seq_num; 473 uint32_t mel_oldest_seq_num; 474 uint32_t mel_clear_seq_num; 475 uint32_t mel_shutdown_seq_num; 476 uint32_t mel_boot_seq_num; 477 } __packed; 478 479 struct mfi_progress { 480 uint16_t mp_progress; 481 uint16_t mp_elapsed_seconds; 482 } __packed; 483 484 struct mfi_evtarg_ld { 485 uint16_t mel_target_id; 486 uint8_t mel_ld_index; 487 uint8_t mel_reserved; 488 } __packed; 489 490 struct mfi_evtarg_pd { 491 uint16_t mep_device_id; 492 uint8_t mep_encl_index; 493 uint8_t mep_slot_number; 494 } __packed; 495 496 struct mfi_evtarg_pd_state { 497 struct mfi_evtarg_pd pd; 498 uint32_t prev_state; 499 uint32_t new_state; 500 } __packed; 501 502 struct mfi_evtarg_pd_address { 503 uint16_t device_id; 504 uint16_t encl_id; 505 506 union { 507 struct { 508 uint8_t encl_index; 509 uint8_t slot_number; 510 } __packed pd_address; 511 struct { 512 uint8_t encl_position; 513 uint8_t encl_connector_index; 514 } __packed encl_address; 515 } __packed address; 516 517 uint8_t scsi_dev_type; 518 519 union { 520 uint8_t port_bitmap; 521 uint8_t port_numbers; 522 } __packed connected; 523 524 uint64_t sas_addr[2]; 525 } __packed __aligned(8); 526 527 struct mfi_evt_detail { 528 uint32_t med_seq_num; 529 uint32_t med_time_stamp; 530 uint32_t med_code; 531 union mfi_evt_class_locale med_cl; 532 uint8_t med_arg_type; 533 uint8_t med_reserved1[15]; 534 535 union { 536 struct { 537 struct mfi_evtarg_pd pd; 538 uint8_t cdb_length; 539 uint8_t sense_length; 540 uint8_t reserved[2]; 541 uint8_t cdb[16]; 542 uint8_t sense[64]; 543 } __packed cdb_sense; 544 545 struct mfi_evtarg_ld ld; 546 547 struct { 548 struct mfi_evtarg_ld ld; 549 uint64_t count; 550 } __packed ld_count; 551 552 struct { 553 uint64_t lba; 554 struct mfi_evtarg_ld ld; 555 } __packed ld_lba; 556 557 struct { 558 struct mfi_evtarg_ld ld; 559 uint32_t prev_owner; 560 uint32_t new_owner; 561 } __packed ld_owner; 562 563 struct { 564 uint64_t ld_lba; 565 uint64_t pd_lba; 566 struct mfi_evtarg_ld ld; 567 struct mfi_evtarg_pd pd; 568 } __packed ld_lba_pd_lba; 569 570 struct { 571 struct mfi_evtarg_ld ld; 572 struct mfi_progress prog; 573 } __packed ld_prog; 574 575 struct { 576 struct mfi_evtarg_ld ld; 577 uint32_t prev_state; 578 uint32_t new_state; 579 } __packed ld_state; 580 581 struct { 582 uint64_t strip; 583 struct mfi_evtarg_ld ld; 584 } __packed ld_strip; 585 586 struct mfi_evtarg_pd pd; 587 588 struct { 589 struct mfi_evtarg_pd pd; 590 uint32_t err; 591 } __packed pd_err; 592 593 struct { 594 uint64_t lba; 595 struct mfi_evtarg_pd pd; 596 } __packed pd_lba; 597 598 struct { 599 uint64_t lba; 600 struct mfi_evtarg_pd pd; 601 struct mfi_evtarg_ld ld; 602 } __packed pd_lba_ld; 603 604 struct { 605 struct mfi_evtarg_pd pd; 606 struct mfi_progress prog; 607 } __packed pd_prog; 608 609 struct mfi_evtarg_pd_state pd_state; 610 611 struct { 612 uint16_t vendor_id; 613 uint16_t device_id; 614 uint16_t subvendor_id; 615 uint16_t subdevice_id; 616 } __packed pci; 617 618 uint32_t rate; 619 char str[96]; 620 621 struct { 622 uint32_t rtc; 623 uint32_t elapsed_seconds; 624 } __packed time; 625 626 struct { 627 uint32_t ecar; 628 uint32_t elog; 629 char str[64]; 630 } __packed ecc; 631 632 struct mfi_evtarg_pd_address pd_address; 633 634 uint8_t b[96]; 635 uint16_t s[48]; 636 uint32_t w[24]; 637 uint64_t d[12]; 638 } args; 639 640 char med_description[128]; 641 } __packed; 642 643 /* controller properties from mfi_ctrl_info */ 644 struct mfi_ctrl_props { 645 uint16_t mcp_seq_num; 646 uint16_t mcp_pred_fail_poll_interval; 647 uint16_t mcp_intr_throttle_cnt; 648 uint16_t mcp_intr_throttle_timeout; 649 uint8_t mcp_rebuild_rate; 650 uint8_t mcp_patrol_read_rate; 651 uint8_t mcp_bgi_rate; 652 uint8_t mcp_cc_rate; 653 uint8_t mcp_recon_rate; 654 uint8_t mcp_cache_flush_interval; 655 uint8_t mcp_spinup_drv_cnt; 656 uint8_t mcp_spinup_delay; 657 uint8_t mcp_cluster_enable; 658 uint8_t mcp_coercion_mode; 659 uint8_t mcp_alarm_enable; 660 uint8_t mcp_disable_auto_rebuild; 661 uint8_t mcp_disable_battery_warn; 662 uint8_t mcp_ecc_bucket_size; 663 uint16_t mcp_ecc_bucket_leak_rate; 664 uint8_t mcp_restore_hotspare_on_insertion; 665 uint8_t mcp_expose_encl_devices; 666 uint8_t mcp_reserved[38]; 667 } __packed; 668 669 /* pci info */ 670 struct mfi_info_pci { 671 uint16_t mip_vendor; 672 uint16_t mip_device; 673 uint16_t mip_subvendor; 674 uint16_t mip_subdevice; 675 uint8_t mip_reserved[24]; 676 } __packed; 677 678 /* host interface info */ 679 struct mfi_info_host { 680 uint8_t mih_type; 681 #define MFI_INFO_HOST_PCIX 0x01 682 #define MFI_INFO_HOST_PCIE 0x02 683 #define MFI_INFO_HOST_ISCSI 0x04 684 #define MFI_INFO_HOST_SAS3G 0x08 685 uint8_t mih_reserved[6]; 686 uint8_t mih_port_count; 687 uint64_t mih_port_addr[8]; 688 } __packed; 689 690 /* device interface info */ 691 struct mfi_info_device { 692 uint8_t mid_type; 693 #define MFI_INFO_DEV_SPI 0x01 694 #define MFI_INFO_DEV_SAS3G 0x02 695 #define MFI_INFO_DEV_SATA1 0x04 696 #define MFI_INFO_DEV_SATA3G 0x08 697 uint8_t mid_reserved[6]; 698 uint8_t mid_port_count; 699 uint64_t mid_port_addr[8]; 700 } __packed; 701 702 /* firmware component info */ 703 struct mfi_info_component { 704 char mic_name[8]; 705 char mic_version[32]; 706 char mic_build_date[16]; 707 char mic_build_time[16]; 708 } __packed; 709 710 /* controller info from MFI_DCMD_CTRL_GETINFO. */ 711 struct mfi_ctrl_info { 712 struct mfi_info_pci mci_pci; 713 struct mfi_info_host mci_host; 714 struct mfi_info_device mci_device; 715 716 /* Firmware components that are present and active. */ 717 uint32_t mci_image_check_word; 718 uint32_t mci_image_component_count; 719 struct mfi_info_component mci_image_component[8]; 720 721 /* Firmware components that have been flashed but are inactive */ 722 uint32_t mci_pending_image_component_count; 723 struct mfi_info_component mci_pending_image_component[8]; 724 725 uint8_t mci_max_arms; 726 uint8_t mci_max_spans; 727 uint8_t mci_max_arrays; 728 uint8_t mci_max_lds; 729 char mci_product_name[80]; 730 char mci_serial_number[32]; 731 uint32_t mci_hw_present; 732 #define MFI_INFO_HW_BBU 0x01 733 #define MFI_INFO_HW_ALARM 0x02 734 #define MFI_INFO_HW_NVRAM 0x04 735 #define MFI_INFO_HW_UART 0x08 736 #define MFI_INFO_HW_FMT "\020" "\001BBU" "\002ALARM" "\003NVRAM" \ 737 "\004UART" 738 739 uint32_t mci_current_fw_time; 740 uint16_t mci_max_cmds; 741 uint16_t mci_max_sg_elements; 742 uint32_t mci_max_request_size; 743 uint16_t mci_lds_present; 744 uint16_t mci_lds_degraded; 745 uint16_t mci_lds_offline; 746 uint16_t mci_pd_present; 747 uint16_t mci_pd_disks_present; 748 uint16_t mci_pd_disks_pred_failure; 749 uint16_t mci_pd_disks_failed; 750 uint16_t mci_nvram_size; 751 uint16_t mci_memory_size; 752 uint16_t mci_flash_size; 753 uint16_t mci_ram_correctable_errors; 754 uint16_t mci_ram_uncorrectable_errors; 755 uint8_t mci_cluster_allowed; 756 uint8_t mci_cluster_active; 757 uint16_t mci_max_strips_per_io; 758 759 uint32_t mci_raid_levels; 760 #define MFI_INFO_RAID_0 0x01 761 #define MFI_INFO_RAID_1 0x02 762 #define MFI_INFO_RAID_5 0x04 763 #define MFI_INFO_RAID_1E 0x08 764 #define MFI_INFO_RAID_6 0x10 765 766 uint32_t mci_adapter_ops; 767 #define MFI_INFO_AOPS_RBLD_RATE 0x0001 768 #define MFI_INFO_AOPS_CC_RATE 0x0002 769 #define MFI_INFO_AOPS_BGI_RATE 0x0004 770 #define MFI_INFO_AOPS_RECON_RATE 0x0008 771 #define MFI_INFO_AOPS_PATROL_RATE 0x0010 772 #define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 773 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 774 #define MFI_INFO_AOPS_BBU 0x0080 775 #define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 776 #define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 777 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 778 #define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 779 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 780 #define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 781 #define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 782 #define MFI_INFO_AOPS_FMT "\020" "\001RBLD_RATE" "\002CC_RATE" \ 783 "\003BGI_RATE" "\004RECON_RATE" \ 784 "\005PATROL_RATE" "\006ALARM_CONTROL" \ 785 "\007CLUSTER_SUPPORT" "\010BBU" \ 786 "\011SPANNING_ALLOWED" \ 787 "\012DEDICATED_SPARES" \ 788 "\013REVERTIBLE_SPARES" \ 789 "\014FOREIGN_IMPORT" "\015SELF_DIAGNOSTIC" \ 790 "\016MIXED_ARRAY" "\017GLOBAL_SPARES" 791 792 uint32_t mci_ld_ops; 793 #define MFI_INFO_LDOPS_READ_POLICY 0x01 794 #define MFI_INFO_LDOPS_WRITE_POLICY 0x02 795 #define MFI_INFO_LDOPS_IO_POLICY 0x04 796 #define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 797 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 798 799 struct { 800 uint8_t min; 801 uint8_t max; 802 uint8_t reserved[2]; 803 } __packed mci_stripe_sz_ops; 804 805 uint32_t mci_pd_ops; 806 #define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 807 #define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 808 #define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 809 810 uint32_t mci_pd_mix_support; 811 #define MFI_INFO_PDMIX_SAS 0x01 812 #define MFI_INFO_PDMIX_SATA 0x02 813 #define MFI_INFO_PDMIX_ENCL 0x04 814 #define MFI_INFO_PDMIX_LD 0x08 815 #define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 816 817 uint8_t mci_ecc_bucket_count; 818 uint8_t mci_reserved2[11]; 819 struct mfi_ctrl_props mci_properties; 820 char mci_package_version[0x60]; 821 uint8_t mci_pad[0x800 - 0x6a0]; 822 } __packed; 823 824 /* logical disk info from MR_DCMD_LD_GET_LIST */ 825 struct mfi_ld { 826 uint8_t mld_target; 827 uint8_t mld_res; 828 uint16_t mld_seq; 829 } __packed; 830 831 struct mfi_ld_list { 832 uint32_t mll_no_ld; 833 uint32_t mll_res; 834 struct { 835 struct mfi_ld mll_ld; 836 uint8_t mll_state; 837 #define MFI_LD_OFFLINE 0x00 838 #define MFI_LD_PART_DEGRADED 0x01 839 #define MFI_LD_DEGRADED 0x02 840 #define MFI_LD_ONLINE 0x03 841 uint8_t mll_res2; 842 uint8_t mll_res3; 843 uint8_t mll_res4; 844 uint64_t mll_size; 845 } mll_list[MFI_MAX_LD]; 846 } __packed; 847 848 /* logicl disk details from MR_DCMD_LD_GET_INFO */ 849 struct mfi_ld_prop { 850 struct mfi_ld mlp_ld; 851 char mlp_name[16]; 852 uint8_t mlp_cache_policy; 853 uint8_t mlp_acces_policy; 854 uint8_t mlp_diskcache_policy; 855 uint8_t mlp_cur_cache_policy; 856 uint8_t mlp_disable_bgi; 857 uint8_t mlp_res[7]; 858 } __packed; 859 860 struct mfi_ld_parm { 861 uint8_t mpa_pri_raid; /* SNIA DDF PRL */ 862 #define MFI_DDF_PRL_RAID0 0x00 863 #define MFI_DDF_PRL_RAID1 0x01 864 #define MFI_DDF_PRL_RAID3 0x03 865 #define MFI_DDF_PRL_RAID4 0x04 866 #define MFI_DDF_PRL_RAID5 0x05 867 #define MFI_DDF_PRL_RAID1E 0x11 868 #define MFI_DDF_PRL_JBOD 0x0f 869 #define MFI_DDF_PRL_CONCAT 0x1f 870 #define MFI_DDF_PRL_RAID5E 0x15 871 #define MFI_DDF_PRL_RAID5EE 0x25 872 #define MFI_DDF_PRL_RAID6 0x16 873 uint8_t mpa_raid_qual; /* SNIA DDF RLQ */ 874 uint8_t mpa_sec_raid; /* SNIA DDF SRL */ 875 #define MFI_DDF_SRL_STRIPED 0x00 876 #define MFI_DDF_SRL_MIRRORED 0x01 877 #define MFI_DDF_SRL_CONCAT 0x02 878 #define MFI_DDF_SRL_SPANNED 0x03 879 uint8_t mpa_stripe_size; 880 uint8_t mpa_no_drv_per_span; 881 uint8_t mpa_span_depth; 882 uint8_t mpa_state; 883 uint8_t mpa_init_state; 884 uint8_t mpa_res[24]; 885 } __packed; 886 887 struct mfi_ld_span { 888 uint64_t mls_start_block; 889 uint64_t mls_no_blocks; 890 uint16_t mls_index; 891 uint8_t mls_res[6]; 892 } __packed; 893 894 struct mfi_ld_cfg { 895 struct mfi_ld_prop mlc_prop; 896 struct mfi_ld_parm mlc_parm; 897 struct mfi_ld_span mlc_span[MFI_MAX_SPAN]; 898 } __packed; 899 900 struct mfi_ld_progress { 901 uint32_t mlp_in_prog; 902 #define MFI_LD_PROG_CC 0x01 903 #define MFI_LD_PROG_BGI 0x02 904 #define MFI_LD_PROG_FGI 0x04 905 #define MFI_LD_PROG_RECONSTRUCT 0x08 906 struct mfi_progress mlp_cc; 907 struct mfi_progress mlp_bgi; 908 struct mfi_progress mlp_fgi; 909 struct mfi_progress mlp_reconstruct; 910 struct mfi_progress mlp_res[4]; 911 } __packed; 912 913 struct mfi_ld_details { 914 struct mfi_ld_cfg mld_cfg; 915 uint64_t mld_size; 916 struct mfi_ld_progress mld_progress; 917 uint16_t mld_clust_own_id; 918 uint8_t mld_res1; 919 uint8_t mld_res2; 920 uint8_t mld_inq_page83[64]; 921 uint8_t mld_res[16]; 922 } __packed; 923 924 /* physical disk info from MR_DCMD_PD_GET_LIST */ 925 struct mfi_pd_address { 926 uint16_t mpa_pd_id; 927 uint16_t mpa_enc_id; 928 uint8_t mpa_enc_index; 929 uint8_t mpa_enc_slot; 930 uint8_t mpa_scsi_type; 931 uint8_t mpa_port; 932 uint64_t mpa_sas_address[2]; 933 } __packed; 934 935 struct mfi_pd_list { 936 uint32_t mpl_size; 937 uint32_t mpl_no_pd; 938 struct mfi_pd_address mpl_address[MFI_MAX_PD]; 939 } __packed; 940 941 struct mfi_pd { 942 uint16_t mfp_id; 943 uint16_t mfp_seq; 944 } __packed; 945 946 struct mfi_pd_progress { 947 uint32_t mfp_in_prog; 948 #define MFI_PD_PROG_RBLD 0x01 949 #define MFI_PD_PROG_PR 0x02 950 #define MFI_PD_PROG_CLEAR 0x04 951 struct mfi_progress mfp_rebuild; 952 struct mfi_progress mfp_patrol_read; 953 struct mfi_progress mfp_clear; 954 struct mfi_progress mfp_res[4]; 955 } __packed; 956 957 struct mfi_pd_details { 958 struct mfi_pd mpd_pd; 959 uint8_t mpd_inq_data[96]; 960 uint8_t mpd_inq_page83[64]; 961 uint8_t mpd_no_support; 962 uint8_t mpd_scsi_type; 963 uint8_t mpd_port; 964 uint8_t mpd_speed; 965 uint32_t mpd_mediaerr_cnt; 966 uint32_t mpd_othererr_cnt; 967 uint32_t mpd_predfail_cnt; 968 uint32_t mpd_last_pred_event; 969 uint16_t mpd_fw_state; 970 uint8_t mpd_rdy_for_remove; 971 uint8_t mpd_link_speed; 972 uint32_t mpd_ddf_state; 973 #define MFI_DDF_GUID_FORCED 0x01 974 #define MFI_DDF_PART_OF_VD 0x02 975 #define MFI_DDF_GLOB_HOTSPARE 0x04 976 #define MFI_DDF_HOTSPARE 0x08 977 #define MFI_DDF_FOREIGN 0x10 978 #define MFI_DDF_TYPE_MASK 0xf000 979 #define MFI_DDF_TYPE_UNKNOWN 0x0000 980 #define MFI_DDF_TYPE_PAR_SCSI 0x1000 981 #define MFI_DDF_TYPE_SAS 0x2000 982 #define MFI_DDF_TYPE_SATA 0x3000 983 #define MFI_DDF_TYPE_FC 0x4000 984 struct { 985 uint8_t mpp_cnt; 986 uint8_t mpp_severed; 987 uint8_t mpp_connector_idx[2]; 988 uint8_t mpp_res[4]; 989 uint64_t mpp_sas_addr[2]; 990 uint8_t mpp_res2[16]; 991 } __packed mpd_path; 992 uint64_t mpd_size; 993 uint64_t mpd_no_coerce_size; 994 uint64_t mpd_coerce_size; 995 uint16_t mpd_enc_id; 996 uint8_t mpd_enc_idx; 997 uint8_t mpd_enc_slot; 998 struct mfi_pd_progress mpd_progress; 999 uint8_t mpd_bblock_full; 1000 uint8_t mpd_unusable; 1001 uint8_t mpd_inq_page83_ext[64]; 1002 uint8_t mpd_power_state; /* XXX */ 1003 uint8_t mpd_enc_pos; 1004 uint32_t mpd_allowed_ops; 1005 #define MFI_PD_A_ONLINE (1<<0) 1006 #define MFI_PD_A_OFFLINE (1<<1) 1007 #define MFI_PD_A_FAILED (1<<2) 1008 #define MFI_PD_A_BAD (1<<3) 1009 #define MFI_PD_A_UNCONFIG (1<<4) 1010 #define MFI_PD_A_HOTSPARE (1<<5) 1011 #define MFI_PD_A_REMOVEHOTSPARE (1<<6) 1012 #define MFI_PD_A_REPLACEMISSING (1<<7) 1013 #define MFI_PD_A_MARKMISSING (1<<8) 1014 #define MFI_PD_A_STARTREBUILD (1<<9) 1015 #define MFI_PD_A_STOPREBUILD (1<<10) 1016 #define MFI_PD_A_BLINK (1<<11) 1017 #define MFI_PD_A_CLEAR (1<<12) 1018 #define MFI_PD_A_FOREIGNIMPORNOTALLOWED (1<<13) 1019 #define MFI_PD_A_STARTCOPYBACK (1<<14) 1020 #define MFI_PD_A_STOPCOPYBACK (1<<15) 1021 #define MFI_PD_A_FWDOWNLOADDNOTALLOWED (1<<16) 1022 #define MFI_PD_A_REPROVISION (1<<17) 1023 uint16_t mpd_copyback_partner_id; 1024 uint16_t mpd_enc_partner_devid; 1025 uint16_t mpd_security; 1026 #define MFI_PD_FDE_CAPABLE (1<<0) 1027 #define MFI_PD_FDE_ENABLED (1<<1) 1028 #define MFI_PD_FDE_SECURED (1<<2) 1029 #define MFI_PD_FDE_LOCKED (1<<3) 1030 #define MFI_PD_FDE_FOREIGNLOCK (1<<4) 1031 uint8_t mpd_media; 1032 uint8_t mpd_res[141]; /* size is 512 */ 1033 } __packed; 1034 1035 struct mfi_pd_allowedops_list { 1036 uint32_t mpo_no_entries; 1037 uint32_t mpo_res; 1038 uint32_t mpo_allowedops_list[MFI_MAX_PD]; 1039 } __packed; 1040 1041 /* array configuration from MR_DCMD_CONF_GET */ 1042 struct mfi_array { 1043 uint64_t mar_smallest_pd; 1044 uint8_t mar_no_disk; 1045 uint8_t mar_res1; 1046 uint16_t mar_array_ref; 1047 uint8_t mar_res2[20]; 1048 struct { 1049 struct mfi_pd mar_pd; 1050 uint16_t mar_pd_state; 1051 #define MFI_PD_UNCONFIG_GOOD 0x00 1052 #define MFI_PD_UNCONFIG_BAD 0x01 1053 #define MFI_PD_HOTSPARE 0x02 1054 #define MFI_PD_OFFLINE 0x10 1055 #define MFI_PD_FAILED 0x11 1056 #define MFI_PD_REBUILD 0x14 1057 #define MFI_PD_ONLINE 0x18 1058 #define MFI_PD_COPYBACK 0x20 1059 #define MFI_PD_SYSTEM 0x40 1060 uint8_t mar_enc_pd; 1061 uint8_t mar_enc_slot; 1062 } pd[MFI_MAX_PD_ARRAY]; 1063 } __packed; 1064 1065 struct mfi_hotspare { 1066 struct mfi_pd mhs_pd; 1067 uint8_t mhs_type; 1068 #define MFI_PD_HS_DEDICATED 0x01 1069 #define MFI_PD_HS_REVERTIBLE 0x02 1070 #define MFI_PD_HS_ENC_AFFINITY 0x04 1071 uint8_t mhs_res[2]; 1072 uint8_t mhs_array_max; 1073 uint16_t mhs_array_ref[MFI_MAX_ARRAY_DEDICATED]; 1074 } __packed; 1075 1076 struct mfi_conf { 1077 uint32_t mfc_size; 1078 uint16_t mfc_no_array; 1079 uint16_t mfc_array_size; 1080 uint16_t mfc_no_ld; 1081 uint16_t mfc_ld_size; 1082 uint16_t mfc_no_hs; 1083 uint16_t mfc_hs_size; 1084 uint8_t mfc_res[16]; 1085 /* 1086 * XXX this is a ridiculous hack and does not reflect reality 1087 * Structures are actually indexed and therefore need pointer 1088 * math to reach. We need the size of this structure first so 1089 * call it with the size of this structure and then use the returned 1090 * values to allocate memory and do the transfer of the whole structure 1091 * then calculate pointers to each of these structures. 1092 */ 1093 struct mfi_array mfc_array[1]; 1094 struct mfi_ld_cfg mfc_ld[1]; 1095 struct mfi_hotspare mfc_hs[1]; 1096 } __packed; 1097 1098 struct mfi_bbu_capacity_info { 1099 uint16_t relative_charge; 1100 uint16_t absolute_charge; 1101 uint16_t remaining_capacity; 1102 uint16_t full_charge_capacity; 1103 uint16_t run_time_to_empty; 1104 uint16_t average_time_to_empty; 1105 uint16_t average_time_to_full; 1106 uint16_t cycle_count; 1107 uint16_t max_error; 1108 uint16_t remaining_capacity_alarm; 1109 uint16_t remaining_time_alarm; 1110 uint8_t reserved[26]; 1111 } __packed; 1112 1113 struct mfi_bbu_design_info { 1114 uint32_t mfg_date; 1115 uint16_t design_capacity; 1116 uint16_t design_voltage; 1117 uint16_t spec_info; 1118 uint16_t serial_number; 1119 uint16_t pack_stat_config; 1120 uint8_t mfg_name[12]; 1121 uint8_t device_name[8]; 1122 uint8_t device_chemistry[8]; 1123 uint8_t mfg_data[8]; 1124 uint8_t reserved[17]; 1125 } __packed; 1126 1127 struct mfi_ibbu_state { 1128 uint16_t gas_guage_status; 1129 uint16_t relative_charge; 1130 uint16_t charger_system_state; 1131 uint16_t charger_system_ctrl; 1132 uint16_t charging_current; 1133 uint16_t absolute_charge; 1134 uint16_t max_error; 1135 uint8_t reserved[18]; 1136 } __packed; 1137 1138 struct mfi_bbu_state { 1139 uint16_t gas_guage_status; 1140 uint16_t relative_charge; 1141 uint16_t charger_status; 1142 uint16_t remaining_capacity; 1143 uint16_t full_charge_capacity; 1144 uint8_t is_SOH_good; 1145 uint8_t reserved[21]; 1146 } __packed; 1147 1148 struct mfi_bbu_properties { 1149 uint32_t auto_learn_period; 1150 uint32_t next_learn_time; 1151 uint8_t learn_delay_interval; 1152 uint8_t auto_learn_mode; 1153 uint8_t bbu_mode; 1154 uint8_t reserved[21]; 1155 } __packed; 1156 1157 union mfi_bbu_status_detail { 1158 struct mfi_ibbu_state ibbu; 1159 struct mfi_bbu_state bbu; 1160 }; 1161 1162 struct mfi_bbu_status { 1163 uint8_t battery_type; 1164 #define MFI_BBU_TYPE_NONE 0 1165 #define MFI_BBU_TYPE_IBBU 1 1166 #define MFI_BBU_TYPE_BBU 2 1167 uint8_t reserved; 1168 uint16_t voltage; /* mV */ 1169 int16_t current; /* mA */ 1170 uint16_t temperature; /* degC */ 1171 uint32_t fw_status; 1172 #define MFI_BBU_STATE_PACK_MISSING (1 << 0) 1173 #define MFI_BBU_STATE_VOLTAGE_LOW (1 << 1) 1174 #define MFI_BBU_STATE_TEMPERATURE_HIGH (1 << 2) 1175 #define MFI_BBU_STATE_CHARGE_ACTIVE (1 << 3) 1176 #define MFI_BBU_STATE_DISCHARGE_ACTIVE (1 << 4) 1177 #define MFI_BBU_STATE_LEARN_CYC_REQ (1 << 5) 1178 #define MFI_BBU_STATE_LEARN_CYC_ACTIVE (1 << 6) 1179 #define MFI_BBU_STATE_LEARN_CYC_FAIL (1 << 7) 1180 #define MFI_BBU_STATE_LEARN_CYC_TIMEOUT (1 << 8) 1181 #define MFI_BBU_STATE_I2C_ERR_DETECT (1 << 9) 1182 #define MFI_BBU_STATE_REPLACE_PACK (1 << 10) 1183 #define MFI_BBU_STATE_CAPACITY_LOW (1 << 11) 1184 #define MFI_BBU_STATE_LEARN_REQUIRED (1 << 12) 1185 #define MFI_BBU_STATE_FMT "\020" \ 1186 "\001PACK_MISSING" \ 1187 "\002VOLTAGE_LOW" \ 1188 "\003TEMP_HIGH" \ 1189 "\004CHARGE_ACTIVE" \ 1190 "\005DISCHARGE_ACTIVE" \ 1191 "\006LEARN_CYC_REQ" \ 1192 "\007LEARN_CYC_ACTIVE" \ 1193 "\010LEARN_CYC_FAIL" \ 1194 "\011LEARN_CYC_TIMEOUT" \ 1195 "\012I2C_ERR_DETECT" \ 1196 "\013REPLACE_PACK" \ 1197 "\014CAPACITY_LOW" \ 1198 "\015LEARN_REQUIRED" 1199 #define MFI_BBU_STATE_BAD_IBBU ( \ 1200 MFI_BBU_STATE_PACK_MISSING | \ 1201 MFI_BBU_STATE_VOLTAGE_LOW | \ 1202 MFI_BBU_STATE_DISCHARGE_ACTIVE | \ 1203 MFI_BBU_STATE_LEARN_CYC_REQ | \ 1204 MFI_BBU_STATE_LEARN_CYC_ACTIVE | \ 1205 MFI_BBU_STATE_REPLACE_PACK | \ 1206 MFI_BBU_STATE_CAPACITY_LOW) 1207 #define MFI_BBU_STATE_BAD_BBU ( \ 1208 MFI_BBU_STATE_PACK_MISSING | \ 1209 MFI_BBU_STATE_REPLACE_PACK | \ 1210 MFI_BBU_STATE_CAPACITY_LOW) 1211 1212 uint8_t pad[20]; 1213 union mfi_bbu_status_detail detail; 1214 } __packed; 1215 1216 struct mfi_pr_status { 1217 uint32_t num_iteration; 1218 uint8_t state; 1219 uint8_t num_pd_done; 1220 uint8_t reserved[10]; 1221 } __packed; 1222 1223 struct mfi_pr_properties { 1224 uint8_t op_mode; 1225 uint8_t max_pd; 1226 uint8_t reserved; 1227 uint8_t exclude_ld_count; 1228 uint16_t excluded_ld[MFI_MAX_LD]; 1229 uint8_t cur_pd_map[MFI_MAX_PD / 8]; 1230 uint8_t last_pd_map[MFI_MAX_PD / 8]; 1231 uint32_t next_exec; 1232 uint32_t exec_freq; 1233 uint32_t clear_freq; 1234 } __packed; 1235 1236 /* We currently don't know the full details of the following struct */ 1237 struct mfii_foreign_scan_cfg { 1238 char data[24]; 1239 }; 1240 1241 struct mfii_foreign_scan_info { 1242 uint32_t count; /* Number of foreign configs found */ 1243 struct mfii_foreign_scan_cfg cfgs[8]; 1244 };
Cache object: 601b6596a8783362ffac53495e462f91
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