FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/mlxreg.h
1 /* $NetBSD: mlxreg.h,v 1.5 2005/02/27 00:27:02 perry Exp $ */
2
3 /*-
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Andrew Doran.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 /*-
40 * Copyright (c) 1999 Michael Smith
41 * All rights reserved.
42 *
43 * Redistribution and use in source and binary forms, with or without
44 * modification, are permitted provided that the following conditions
45 * are met:
46 * 1. Redistributions of source code must retain the above copyright
47 * notice, this list of conditions and the following disclaimer.
48 * 2. Redistributions in binary form must reproduce the above copyright
49 * notice, this list of conditions and the following disclaimer in the
50 * documentation and/or other materials provided with the distribution.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
55 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
62 * SUCH DAMAGE.
63 *
64 * from FreeBSD: mlxreg.h,v 1.5.2.2 2000/04/24 19:40:50 msmith Exp
65 */
66
67 #ifndef _IC_MLXREG_H_
68 #define _IC_MLXREG_H_
69
70 #define MLX_SECTOR_SIZE 512
71
72 /*
73 * Selected command codes.
74 */
75 #define MLX_CMD_ENQUIRY_OLD 0x05
76 #define MLX_CMD_ENQUIRY 0x53
77 #define MLX_CMD_ENQUIRY2 0x1c
78 #define MLX_CMD_ENQSYSDRIVE 0x19
79 #define MLX_CMD_READSG 0xb6
80 #define MLX_CMD_WRITESG 0xb7
81 #define MLX_CMD_READSG_OLD 0x82
82 #define MLX_CMD_WRITESG_OLD 0x83
83 #define MLX_CMD_FLUSH 0x0a
84 #define MLX_CMD_LOGOP 0x72
85 #define MLX_CMD_REBUILDASYNC 0x16
86 #define MLX_CMD_CHECKASYNC 0x1e
87 #define MLX_CMD_REBUILDSTAT 0x0c
88 #define MLX_CMD_STOPCHANNEL 0x13
89 #define MLX_CMD_STARTCHANNEL 0x12
90 #define MLX_CMD_READ_CONFIG 0x4e
91 #define MLX_CMD_WRITE_CONFIG 0x4f
92 #define MLX_CMD_READ_DK_CONFIG 0x4a
93 #define MLX_CMD_WRITE_DK_CONFIG 0x4b
94 #define MLX_CMD_DIRECT_CDB 0x04
95 #define MLX_CMD_DEVICE_STATE 0x50
96 #define MLX_CMD_READ_CONFIG2 0x3d
97 #define MLX_CMD_WRITE_CONFIG2 0x3c
98
99 #ifdef _KERNEL
100
101 /*
102 * Status values.
103 */
104 #define MLX_STATUS_OK 0x0000
105 #define MLX_STATUS_RDWROFFLINE 0x0002 /* read/write claims drive is offline */
106 #define MLX_STATUS_WEDGED 0xdeaf /* controller not listening */
107 #define MLX_STATUS_LOST 0xdead /* never came back */
108 #define MLX_STATUS_BUSY 0xbabe /* command is in controller */
109
110 /*
111 * V1 (EISA) interface.
112 */
113 #define MLX_V1REG_IE 0x09
114 #define MLX_V1REG_IDB 0x0d
115 #define MLX_V1REG_ODB_EN 0x0e
116 #define MLX_V1REG_ODB 0x0f
117 #define MLX_V1REG_MAILBOX 0x10
118
119 #define MLX_V1_IDB_FULL 0x01 /* mailbox is full */
120 #define MLX_V1_IDB_INIT_BUSY 0x02 /* init in progress */
121
122 #define MLX_V1_IDB_SACK 0x02 /* acknowledge status read */
123 #define MLX_V1_IDB_RESET 0x10 /* reset controller */
124
125 #define MLX_V1_ODB_SAVAIL 0x01 /* status is available */
126 #define MLX_V1_ODB_RESET 0x02 /* reset controller */
127
128 #define MLX_V1_FWERROR_PEND 0x04 /* firmware error pending */
129
130 /*
131 * V2/V3 interface.
132 */
133 #define MLX_V3REG_MAILBOX 0x00
134 #define MLX_V3REG_STATUS_IDENT 0x0d
135 #define MLX_V3REG_STATUS 0x0e
136 #define MLX_V3REG_IDB 0x40
137 #define MLX_V3REG_ODB 0x41
138 #define MLX_V3REG_IE 0x43
139 #define MLX_V3REG_FWERROR 0x3f
140 #define MLX_V3REG_FWERROR_PARAM1 0x00
141 #define MLX_V3REG_FWERROR_PARAM2 0x01
142
143 #define MLX_V3_IDB_FULL 0x01 /* mailbox is full */
144 #define MLX_V3_IDB_INIT_BUSY 0x02 /* init in progress */
145
146 #define MLX_V3_IDB_SACK 0x02 /* acknowledge status read */
147 #define MLX_V3_IDB_RESET 0x08 /* reset controller */
148
149 #define MLX_V3_ODB_SAVAIL 0x01 /* status is available */
150
151 #define MLX_V3_FWERROR_PEND 0x04 /* firmware error pending */
152
153 /*
154 * V4 interface.
155 */
156 #define MLX_V4REG_MAILBOX 0x1000
157 #define MLX_V4REG_STATUS_IDENT 0x1018
158 #define MLX_V4REG_STATUS 0x101a
159 #define MLX_V4REG_IDB 0x0020
160 #define MLX_V4REG_ODB 0x002c
161 #define MLX_V4REG_IE 0x0034
162 #define MLX_V4REG_FWERROR 0x103f
163 #define MLX_V4REG_FWERROR_PARAM1 0x1000
164 #define MLX_V4REG_FWERROR_PARAM2 0x1001
165
166 #define MLX_V4_IDB_FULL 0x01 /* mailbox is full */
167 #define MLX_V4_IDB_INIT_BUSY 0x02 /* initialisation in progress */
168
169 #define MLX_V4_IDB_HWMBOX_CMD 0x01 /* posted hardware mailbox command */
170 #define MLX_V4_IDB_SACK 0x02 /* acknowledge status read */
171 #define MLX_V4_IDB_MEMMBOX_CMD 0x10 /* posted memory mailbox command */
172
173 #define MLX_V4_ODB_HWSAVAIL 0x01 /* status available for hardware m/b */
174 #define MLX_V4_ODB_MEMSAVAIL 0x02 /* status available for memory m/b */
175
176 #define MLX_V4_ODB_HWMBOX_ACK 0x01 /* ack status read from hardware m/b */
177 #define MLX_V4_ODB_MEMMBOX_ACK 0x02 /* ack status read from memory m/b */
178
179 #define MLX_V4_IE_MASK 0xfb /* message unit interrupt mask */
180 #define MLX_V4_IE_DISINT 0x04 /* interrupt disable bit */
181
182 #define MLX_V4_FWERROR_PEND 0x04 /* firmware error pending */
183
184 /*
185 * V5 interface.
186 */
187 #define MLX_V5REG_MAILBOX 0x50
188 #define MLX_V5REG_STATUS_IDENT 0x5d
189 #define MLX_V5REG_STATUS 0x5e
190 #define MLX_V5REG_IDB 0x60
191 #define MLX_V5REG_ODB 0x61
192 #define MLX_V5REG_IE 0x34
193 #define MLX_V5REG_FWERROR 0x63
194 #define MLX_V5REG_FWERROR_PARAM1 0x50
195 #define MLX_V5REG_FWERROR_PARAM2 0x51
196
197 #define MLX_V5_IDB_EMPTY 0x01 /* mailbox is empty */
198 #define MLX_V5_IDB_INIT_DONE 0x02 /* initialisation has completed */
199
200 #define MLX_V5_IDB_HWMBOX_CMD 0x01 /* posted hardware mailbox command */
201 #define MLX_V5_IDB_SACK 0x02 /* acknowledge status read */
202 #define MLX_V5_IDB_RESET 0x08 /* reset request */
203 #define MLX_V5_IDB_MEMMBOX_CMD 0x10 /* posted memory mailbox command */
204
205 #define MLX_V5_ODB_HWSAVAIL 0x01 /* status available for hardware m/b */
206 #define MLX_V5_ODB_MEMSAVAIL 0x02 /* status available for memory m/b */
207
208 #define MLX_V5_ODB_HWMBOX_ACK 0x01 /* ack status read from hardware m/b */
209 #define MLX_V5_ODB_MEMMBOX_ACK 0x02 /* ack status read from memory m/b */
210
211 #define MLX_V5_IE_DISINT 0x04 /* interrupt disable bit */
212
213 #define MLX_V5_FWERROR_PEND 0x04 /* firmware error pending */
214
215 #endif /* _KERNEL */
216
217 /*
218 * Scatter-gather list format, type 1, kind 00.
219 */
220 struct mlx_sgentry {
221 u_int32_t sge_addr;
222 u_int32_t sge_count;
223 } __attribute__ ((packed));
224
225 /*
226 * Command result buffers, as placed in system memory by the controller.
227 */
228 struct mlx_enquiry_old {
229 u_int8_t me_num_sys_drvs;
230 u_int8_t me_res1[3];
231 u_int32_t me_drvsize[8];
232 u_int16_t me_flash_age;
233 u_int8_t me_status_flags;
234 u_int8_t me_free_state_change_count;
235 u_int8_t me_fwminor;
236 u_int8_t me_fwmajor;
237 u_int8_t me_rebuild_flag;
238 u_int8_t me_max_commands;
239 u_int8_t me_offline_sd_count;
240 u_int8_t me_res3;
241 u_int8_t me_critical_sd_count;
242 u_int8_t me_res4[3];
243 u_int8_t me_dead_count;
244 u_int8_t me_res5;
245 u_int8_t me_rebuild_count;
246 u_int8_t me_misc_flags;
247 struct {
248 u_int8_t dd_targ;
249 u_int8_t dd_chan;
250 } __attribute__ ((packed)) me_dead[20];
251 } __attribute__ ((packed));
252
253 struct mlx_enquiry {
254 u_int8_t me_num_sys_drvs;
255 u_int8_t me_res1[3];
256 u_int32_t me_drvsize[32];
257 u_int16_t me_flash_age;
258 u_int8_t me_status_flags;
259 #define MLX_ENQ_SFLAG_DEFWRERR 0x01 /* deferred write error indicator */
260 #define MLX_ENQ_SFLAG_BATTLOW 0x02 /* battery low */
261 u_int8_t me_res2;
262 u_int8_t me_fwminor;
263 u_int8_t me_fwmajor;
264 u_int8_t me_rebuild_flag;
265 u_int8_t me_max_commands;
266 u_int8_t me_offline_sd_count;
267 u_int8_t me_res3;
268 u_int16_t me_event_log_seq_num;
269 u_int8_t me_critical_sd_count;
270 u_int8_t me_res4[3];
271 u_int8_t me_dead_count;
272 u_int8_t me_res5;
273 u_int8_t me_rebuild_count;
274 u_int8_t me_misc_flags;
275 #define MLX_ENQ_MISC_BBU 0x08 /* battery backup present */
276 struct {
277 u_int8_t dd_targ;
278 u_int8_t dd_chan;
279 } __attribute__ ((packed)) me_dead[20];
280 } __attribute__ ((packed));
281
282 struct mlx_enquiry2 {
283 u_int8_t me_hardware_id[4];
284 u_int8_t me_firmware_id[4];
285 u_int32_t me_res1;
286 u_int8_t me_configured_channels;
287 u_int8_t me_actual_channels;
288 u_int8_t me_max_targets;
289 u_int8_t me_max_tags;
290 u_int8_t me_max_sys_drives;
291 u_int8_t me_max_arms;
292 u_int8_t me_max_spans;
293 u_int8_t me_res2;
294 u_int32_t me_res3;
295 u_int32_t me_mem_size;
296 u_int32_t me_cache_size;
297 u_int32_t me_flash_size;
298 u_int32_t me_nvram_size;
299 u_int16_t me_mem_type;
300 u_int16_t me_clock_speed;
301 u_int16_t me_mem_speed;
302 u_int16_t me_hardware_speed;
303 u_int8_t me_res4[12];
304 u_int16_t me_max_commands;
305 u_int16_t me_max_sg;
306 u_int16_t me_max_dp;
307 u_int16_t me_max_iod;
308 u_int16_t me_max_comb;
309 u_int8_t me_latency;
310 u_int8_t me_res5;
311 u_int8_t me_scsi_timeout;
312 u_int8_t me_res6;
313 u_int16_t me_min_freelines;
314 u_int8_t me_res7[8];
315 u_int8_t me_rate_const;
316 u_int8_t me_res8[11];
317 u_int16_t me_physblk;
318 u_int16_t me_logblk;
319 u_int16_t me_maxblk;
320 u_int16_t me_blocking_factor;
321 u_int16_t me_cacheline;
322 u_int8_t me_scsi_cap;
323 u_int8_t me_res9[5];
324 u_int16_t me_firmware_build;
325 u_int8_t me_fault_mgmt_type;
326 u_int8_t me_res10;
327 u_int32_t me_firmware_features;
328 u_int8_t me_res11[8];
329 } __attribute__ ((packed));
330
331 /* MLX_CMD_ENQSYSDRIVE returns an array of 32 of these. */
332 struct mlx_enq_sys_drive {
333 u_int32_t sd_size;
334 u_int8_t sd_state;
335 u_int8_t sd_raidlevel;
336 u_int16_t sd_res1;
337 } __attribute__ ((packed));
338
339 /*
340 * MLX_CMD_LOGOP/MLX_LOGOP_GET
341 *
342 * Bitfields:
343 *
344 * 0-4 el_target SCSI target
345 * 5-7 el_target SCSI channel
346 * 0-6 el_errorcode error code
347 * 7-7 el_errorcode validity (?)
348 * 0-3 el_sense sense key
349 * 4-4 el_sense reserved
350 * 5-5 el_sense ILI
351 * 6-6 el_sense EOM
352 * 7-7 el_sense filemark
353 */
354 struct mlx_eventlog_entry {
355 u_int8_t el_type;
356 u_int8_t el_length;
357 u_int8_t el_target;
358 u_int8_t el_lun;
359 u_int16_t el_seqno;
360 u_int8_t el_errorcode;
361 u_int8_t el_segment;
362 u_int8_t el_sense;
363 u_int8_t el_information[4];
364 u_int8_t el_addsense;
365 u_int8_t el_csi[4];
366 u_int8_t el_asc;
367 u_int8_t el_asq;
368 u_int8_t el_res3[12];
369 } __attribute__ ((packed));
370
371 #define MLX_LOGOP_GET 0x00 /* operation codes for MLX_CMD_LOGOP */
372 #define MLX_LOGMSG_SENSE 0x00 /* log message contents codes */
373
374 struct mlx_rebuild_stat {
375 u_int32_t rb_drive;
376 u_int32_t rb_size;
377 u_int32_t rb_remaining;
378 } __attribute__ ((packed));
379
380 struct mlx_config {
381 u_int16_t cf_flags1;
382 #define MLX_CF2_ACTV_NEG 0x0002
383 #define MLX_CF2_NORSTRTRY 0x0080
384 #define MLX_CF2_STRGWRK 0x0100
385 #define MLX_CF2_HPSUPP 0x0200
386 #define MLX_CF2_NODISCN 0x0400
387 #define MLX_CF2_ARM 0x2000
388 #define MLX_CF2_OFM 0x8000
389 #define MLX_CF2_AEMI (MLX_CF2_ARM | MLX_CF2_OFM)
390 u_int8_t cf_oemid;
391 u_int8_t cf_oem_model;
392 u_int8_t cf_physical_sector;
393 u_int8_t cf_logical_sector;
394 u_int8_t cf_blockfactor;
395 u_int8_t cf_flags2;
396 #define MLX_CF2_READAH 0x01
397 #define MLX_CF2_BIOSDLY 0x02
398 #define MLX_CF2_REASS1S 0x10
399 #define MLX_CF2_FUAENABL 0x40
400 #define MLX_CF2_R5ALLS 0x80
401 u_int8_t cf_rcrate;
402 u_int8_t cf_res1;
403 u_int8_t cf_blocks_per_cache_line;
404 u_int8_t cf_blocks_per_stripe;
405 u_int8_t cf_scsi_param_0;
406 u_int8_t cf_scsi_param_1;
407 u_int8_t cf_scsi_param_2;
408 u_int8_t cf_scsi_param_3;
409 u_int8_t cf_scsi_param_4;
410 u_int8_t cf_scsi_param_5;
411 u_int8_t cf_scsi_initiator_id;
412 u_int8_t cf_res2;
413 u_int8_t cf_startup_mode;
414 u_int8_t cf_simultaneous_spinup_devices;
415 u_int8_t cf_delay_between_spinups;
416 u_int8_t cf_res3;
417 u_int16_t cf_checksum;
418 } __attribute__ ((packed));
419
420 struct mlx_config2 {
421 struct mlx_config cf2_cf;
422 u_int8_t cf2_reserved0[26];
423 u_int8_t cf2_flags;
424 #define MLX_CF2_BIOS_DIS 0x01
425 #define MLX_CF2_CDROM_DIS 0x02
426 #define MLX_CF2_GEOM_255 0x20
427 u_int8_t cf2_reserved1[9];
428 u_int16_t cf2_checksum;
429 } __attribute__ ((__packed__));
430
431 struct mlx_sys_drv_span {
432 u_int32_t sp_start_lba;
433 u_int32_t sp_nblks;
434 u_int8_t sp_arm[8];
435 } __attribute__ ((packed));
436
437 struct mlx_sys_drv {
438 u_int8_t sd_status;
439 u_int8_t sd_ext_status;
440 u_int8_t sd_mod1;
441 u_int8_t sd_mod2;
442 u_int8_t sd_raidlevel;
443 #define MLX_SYS_DRV_WRITEBACK (1<<7)
444 #define MLX_SYS_DRV_RAID0 0
445 #define MLX_SYS_DRV_RAID1 1
446 #define MLX_SYS_DRV_RAID3 3
447 #define MLX_SYS_DRV_RAID5 5
448 #define MLX_SYS_DRV_RAID6 6
449 #define MLX_SYS_DRV_JBOD 7
450 u_int8_t sd_valid_arms;
451 u_int8_t sd_valid_spans;
452 u_int8_t sd_init_state;
453 #define MLX_SYS_DRV_INITTED 0x81;
454 struct mlx_sys_drv_span sd_span[4];
455 } __attribute__ ((packed));
456
457 struct mlx_phys_drv {
458 u_int8_t pd_flags1;
459 #define MLX_PHYS_DRV_PRESENT 0x01
460 u_int8_t pd_flags2;
461 #define MLX_PHYS_DRV_OTHER 0x00
462 #define MLX_PHYS_DRV_DISK 0x01
463 #define MLX_PHYS_DRV_SEQUENTIAL 0x02
464 #define MLX_PHYS_DRV_CDROM 0x03
465 #define MLX_PHYS_DRV_FAST20 0x08
466 #define MLX_PHYS_DRV_SYNC 0x10
467 #define MLX_PHYS_DRV_FAST 0x20
468 #define MLX_PHYS_DRV_WIDE 0x40
469 #define MLX_PHYS_DRV_TAG 0x80
470 u_int8_t pd_status;
471 #define MLX_PHYS_DRV_DEAD 0x00
472 #define MLX_PHYS_DRV_WRONLY 0x02
473 #define MLX_PHYS_DRV_ONLINE 0x03
474 #define MLX_PHYS_DRV_STANDBY 0x10
475 u_int8_t pd_res1;
476 u_int8_t pd_period;
477 u_int8_t pd_offset;
478 u_int32_t pd_config_size;
479 } __attribute__ ((packed));
480
481 struct mlx_core_cfg {
482 u_int8_t cc_num_sys_drives;
483 u_int8_t cc_res1[3];
484 struct mlx_sys_drv cc_sys_drives[32];
485 struct mlx_phys_drv cc_phys_drives[5 * 16];
486 } __attribute__ ((packed));
487
488 /*
489 * Bitfields:
490 *
491 * 0-3 dcdb_target SCSI target
492 * 4-7 dcdb_target SCSI channel
493 * 0-3 dcdb_length CDB length
494 * 4-7 dcdb_length high 4 bits of `datasize'
495 */
496 struct mlx_dcdb {
497 u_int8_t dcdb_target;
498 u_int8_t dcdb_flags;
499 #define MLX_DCDB_NO_DATA 0x00
500 #define MLX_DCDB_DATA_IN 0x01
501 #define MLX_DCDB_DATA_OUT 0x02
502 #define MLX_DCDB_EARLY_STATUS 0x04
503 #define MLX_DCDB_TIMEOUT_10S 0x10 /* This lot is wrong? [ad] */
504 #define MLX_DCDB_TIMEOUT_60S 0x20
505 #define MLX_DCDB_TIMEOUT_20M 0x30
506 #define MLX_DCDB_TIMEOUT_24H 0x40
507 #define MLX_DCDB_NO_AUTO_SENSE 0x40 /* XXX ?? */
508 #define MLX_DCDB_DISCONNECT 0x80
509 u_int16_t dcdb_datasize;
510 u_int32_t dcdb_physaddr;
511 u_int8_t dcdb_length;
512 u_int8_t dcdb_sense_length;
513 u_int8_t dcdb_cdb[12];
514 u_int8_t dcdb_sense[64];
515 u_int8_t dcdb_status;
516 u_int8_t res1;
517 } __attribute__ ((packed));
518
519 struct mlx_bbtable_entry {
520 u_int32_t bbt_block_number;
521 u_int8_t bbt_extent;
522 u_int8_t bbt_res1;
523 u_int8_t bbt_entry_type;
524 u_int8_t bbt_system_drive; /* high 3 bits reserved */
525 } __attribute__ ((packed));
526
527 #endif /* !_IC_MLXREG_H_ */
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