mpireg.h

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    1 /*      $OpenBSD: mpireg.h,v 1.45 2014/03/25 05:41:44 dlg Exp $ */
    2 
    3 /*
    4  * Copyright (c) 2005 David Gwynne <dlg@openbsd.org>
    5  * Copyright (c) 2005 Marco Peereboom <marco@openbsd.org>
    6  *
    7  * Permission to use, copy, modify, and distribute this software for any
    8  * purpose with or without fee is hereby granted, provided that the above
    9  * copyright notice and this permission notice appear in all copies.
   10  *
   11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
   14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
   15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
   16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
   17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
   18  */
   19 
   20 /*
   21  * System Interface Register Set
   22  */
   23 
   24 #define MPI_DOORBELL            0x00
   25 /* doorbell read bits */
   26 #define  MPI_DOORBELL_STATE             (0xf<<28) /* ioc state */
   27 #define  MPI_DOORBELL_STATE_RESET       (0x0<<28)
   28 #define  MPI_DOORBELL_STATE_READY       (0x1<<28)
   29 #define  MPI_DOORBELL_STATE_OPER        (0x2<<28)
   30 #define  MPI_DOORBELL_STATE_FAULT       (0x4<<28)
   31 #define  MPI_DOORBELL_INUSE             (0x1<<27) /* doorbell used */
   32 #define  MPI_DOORBELL_WHOINIT           (0x7<<24) /* last to reset ioc */
   33 #define  MPI_DOORBELL_WHOINIT_NOONE     (0x0<<24) /* not initialized */
   34 #define  MPI_DOORBELL_WHOINIT_SYSBIOS   (0x1<<24) /* system bios */
   35 #define  MPI_DOORBELL_WHOINIT_ROMBIOS   (0x2<<24) /* rom bios */
   36 #define  MPI_DOORBELL_WHOINIT_PCIPEER   (0x3<<24) /* pci peer */
   37 #define  MPI_DOORBELL_WHOINIT_DRIVER    (0x4<<24) /* host driver */
   38 #define  MPI_DOORBELL_WHOINIT_MANUFACT  (0x5<<24) /* manufacturing */
   39 #define  MPI_DOORBELL_FAULT             (0xffff<<0) /* fault code */
   40 #define  MPI_DOORBELL_FAULT_REQ_PCIPAR  0x8111 /* req msg pci parity err */
   41 #define  MPI_DOORBELL_FAULT_REQ_PCIBUS  0x8112 /* req msg pci bus err */
   42 #define  MPI_DOORBELL_FAULT_REP_PCIPAR  0x8113 /* reply msg pci parity err */
   43 #define  MPI_DOORBELL_FAULT_REP_PCIBUS  0x8114 /* reply msg pci bus err */
   44 #define  MPI_DOORBELL_FAULT_SND_PCIPAR  0x8115 /* data send pci parity err */
   45 #define  MPI_DOORBELL_FAULT_SND_PCIBUS  0x8116 /* data send pci bus err */
   46 #define  MPI_DOORBELL_FAULT_RCV_PCIPAR  0x8117 /* data recv pci parity err */
   47 #define  MPI_DOORBELL_FAULT_RCV_PCIBUS  0x8118 /* data recv pci bus err */
   48 /* doorbell write bits */
   49 #define  MPI_DOORBELL_FUNCTION_SHIFT    24
   50 #define  MPI_DOORBELL_FUNCTION_MASK     (0xff << MPI_DOORBELL_FUNCTION_SHIFT)
   51 #define  MPI_DOORBELL_FUNCTION(x)       \
   52     (((x) << MPI_DOORBELL_FUNCTION_SHIFT) & MPI_DOORBELL_FUNCTION_MASK)
   53 #define  MPI_DOORBELL_DWORDS_SHIFT      16
   54 #define  MPI_DOORBELL_DWORDS_MASK       (0xff << MPI_DOORBELL_DWORDS_SHIFT)
   55 #define  MPI_DOORBELL_DWORDS(x)         \
   56     (((x) << MPI_DOORBELL_DWORDS_SHIFT) & MPI_DOORBELL_DWORDS_MASK)
   57 #define  MPI_DOORBELL_DATA_MASK         0xffff
   58 
   59 #define MPI_WRITESEQ            0x04
   60 #define  MPI_WRITESEQ_VALUE             0x0000000f /* key value */
   61 #define  MPI_WRITESEQ_1                 0x04
   62 #define  MPI_WRITESEQ_2                 0x0b
   63 #define  MPI_WRITESEQ_3                 0x02
   64 #define  MPI_WRITESEQ_4                 0x07
   65 #define  MPI_WRITESEQ_5                 0x0d
   66 
   67 #define MPI_HOSTDIAG            0x08
   68 #define  MPI_HOSTDIAG_CLEARFBS          (1<<10) /* clear flash bad sig */
   69 #define  MPI_HOSTDIAG_POICB             (1<<9) /* prevent ioc boot */
   70 #define  MPI_HOSTDIAG_DWRE              (1<<7) /* diag reg write enabled */
   71 #define  MPI_HOSTDIAG_FBS               (1<<6) /* flash bad sig */
   72 #define  MPI_HOSTDIAG_RESET_HIST        (1<<5) /* reset history */
   73 #define  MPI_HOSTDIAG_DIAGWR_EN         (1<<4) /* diagnostic write enabled */
   74 #define  MPI_HOSTDIAG_RESET_ADAPTER     (1<<2) /* reset adapter */
   75 #define  MPI_HOSTDIAG_DISABLE_ARM       (1<<1) /* disable arm */
   76 #define  MPI_HOSTDIAG_DIAGMEM_EN        (1<<0) /* diag mem enable */
   77 
   78 #define MPI_TESTBASE            0x0c
   79 
   80 #define MPI_DIAGRWDATA          0x10
   81 
   82 #define MPI_DIAGRWADDR          0x18
   83 
   84 #define MPI_INTR_STATUS         0x30
   85 #define  MPI_INTR_STATUS_IOCDOORBELL    (1<<31) /* ioc doorbell status */
   86 #define  MPI_INTR_STATUS_REPLY          (1<<3) /* reply message interrupt */
   87 #define  MPI_INTR_STATUS_DOORBELL       (1<<0) /* doorbell interrupt */
   88 
   89 #define MPI_INTR_MASK           0x34
   90 #define  MPI_INTR_MASK_REPLY            (1<<3) /* reply message intr mask */
   91 #define  MPI_INTR_MASK_DOORBELL         (1<<0) /* doorbell interrupt mask */
   92 
   93 #define MPI_REQ_QUEUE           0x40
   94 
   95 #define MPI_REPLY_QUEUE         0x44
   96 #define  MPI_REPLY_QUEUE_ADDRESS        (1<<31) /* address reply */
   97 #define  MPI_REPLY_QUEUE_ADDRESS_MASK   0x7fffffff
   98 #define  MPI_REPLY_QUEUE_TYPE_MASK      (3<<29)
   99 #define  MPI_REPLY_QUEUE_TYPE_INIT      (0<<29) /* scsi initiator reply */
  100 #define  MPI_REPLY_QUEUE_TYPE_TARGET    (1<<29) /* scsi target reply */
  101 #define  MPI_REPLY_QUEUE_TYPE_LAN       (2<<29) /* lan reply */
  102 #define  MPI_REPLY_QUEUE_CONTEXT        0x1fffffff /* not address and type */
  103 
  104 #define MPI_PRIREQ_QUEUE        0x48
  105 
  106 /*
  107  * Scatter Gather Lists
  108  */
  109 
  110 #define MPI_SGE_FL_LAST                 (0x1<<31) /* last element in segment */
  111 #define MPI_SGE_FL_EOB                  (0x1<<30) /* last element of buffer */
  112 #define MPI_SGE_FL_TYPE                 (0x3<<28) /* element type */
  113 #define  MPI_SGE_FL_TYPE_SIMPLE         (0x1<<28) /* simple element */
  114 #define  MPI_SGE_FL_TYPE_CHAIN          (0x3<<28) /* chain element */
  115 #define  MPI_SGE_FL_TYPE_XACTCTX        (0x0<<28) /* transaction context */
  116 #define MPI_SGE_FL_LOCAL                (0x1<<27) /* local address */
  117 #define MPI_SGE_FL_DIR                  (0x1<<26) /* direction */
  118 #define  MPI_SGE_FL_DIR_OUT             (0x1<<26)
  119 #define  MPI_SGE_FL_DIR_IN              (0x0<<26)
  120 #define MPI_SGE_FL_SIZE                 (0x1<<25) /* address size */
  121 #define  MPI_SGE_FL_SIZE_32             (0x0<<25)
  122 #define  MPI_SGE_FL_SIZE_64             (0x1<<25)
  123 #define MPI_SGE_FL_EOL                  (0x1<<24) /* end of list */
  124 #define MPI_SGE_FLAGS_IOC_TO_HOST       (0x00)
  125 #define MPI_SGE_FLAGS_HOST_TO_IOC       (0x04)
  126 
  127 struct mpi_sge {
  128         u_int32_t               sg_hdr;
  129         u_int32_t               sg_addr_lo;
  130         u_int32_t               sg_addr_hi;
  131 } __packed __aligned(4);
  132 
  133 struct mpi_fw_tce {
  134         u_int8_t                reserved1;
  135         u_int8_t                context_size;
  136         u_int8_t                details_length;
  137         u_int8_t                flags;
  138 
  139         u_int32_t               reserved2;
  140 
  141         u_int32_t               image_offset;
  142 
  143         u_int32_t               image_size;
  144 } __packed __aligned(4);
  145 
  146 /*
  147  * Messages
  148  */
  149 
  150 /* functions */
  151 #define MPI_FUNCTION_SCSI_IO_REQUEST                    (0x00)
  152 #define MPI_FUNCTION_SCSI_TASK_MGMT                     (0x01)
  153 #define MPI_FUNCTION_IOC_INIT                           (0x02)
  154 #define MPI_FUNCTION_IOC_FACTS                          (0x03)
  155 #define MPI_FUNCTION_CONFIG                             (0x04)
  156 #define MPI_FUNCTION_PORT_FACTS                         (0x05)
  157 #define MPI_FUNCTION_PORT_ENABLE                        (0x06)
  158 #define MPI_FUNCTION_EVENT_NOTIFICATION                 (0x07)
  159 #define MPI_FUNCTION_EVENT_ACK                          (0x08)
  160 #define MPI_FUNCTION_FW_DOWNLOAD                        (0x09)
  161 #define MPI_FUNCTION_TARGET_CMD_BUFFER_POST             (0x0A)
  162 #define MPI_FUNCTION_TARGET_ASSIST                      (0x0B)
  163 #define MPI_FUNCTION_TARGET_STATUS_SEND                 (0x0C)
  164 #define MPI_FUNCTION_TARGET_MODE_ABORT                  (0x0D)
  165 #define MPI_FUNCTION_TARGET_FC_BUF_POST_LINK_SRVC       (0x0E) /* obsolete */
  166 #define MPI_FUNCTION_TARGET_FC_RSP_LINK_SRVC            (0x0F) /* obsolete */
  167 #define MPI_FUNCTION_TARGET_FC_EX_SEND_LINK_SRVC        (0x10) /* obsolete */
  168 #define MPI_FUNCTION_TARGET_FC_ABORT                    (0x11) /* obsolete */
  169 #define MPI_FUNCTION_FC_LINK_SRVC_BUF_POST              (0x0E)
  170 #define MPI_FUNCTION_FC_LINK_SRVC_RSP                   (0x0F)
  171 #define MPI_FUNCTION_FC_EX_LINK_SRVC_SEND               (0x10)
  172 #define MPI_FUNCTION_FC_ABORT                           (0x11)
  173 #define MPI_FUNCTION_FW_UPLOAD                          (0x12)
  174 #define MPI_FUNCTION_FC_COMMON_TRANSPORT_SEND           (0x13)
  175 #define MPI_FUNCTION_FC_PRIMITIVE_SEND                  (0x14)
  176 
  177 #define MPI_FUNCTION_RAID_ACTION                        (0x15)
  178 #define MPI_FUNCTION_RAID_SCSI_IO_PASSTHROUGH           (0x16)
  179 
  180 #define MPI_FUNCTION_TOOLBOX                            (0x17)
  181 
  182 #define MPI_FUNCTION_SCSI_ENCLOSURE_PROCESSOR           (0x18)
  183 
  184 #define MPI_FUNCTION_MAILBOX                            (0x19)
  185 
  186 #define MPI_FUNCTION_LAN_SEND                           (0x20)
  187 #define MPI_FUNCTION_LAN_RECEIVE                        (0x21)
  188 #define MPI_FUNCTION_LAN_RESET                          (0x22)
  189 
  190 #define MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET             (0x40)
  191 #define MPI_FUNCTION_IO_UNIT_RESET                      (0x41)
  192 #define MPI_FUNCTION_HANDSHAKE                          (0x42)
  193 #define MPI_FUNCTION_REPLY_FRAME_REMOVAL                (0x43)
  194 
  195 /* reply flags */
  196 #define MPI_REP_FLAGS_CONT              (1<<7) /* continuation reply */
  197 
  198 #define MPI_REP_IOCSTATUS_AVAIL         (1<<15) /* logging info available */
  199 #define MPI_REP_IOCSTATUS               (0x7fff) /* status */
  200 
  201 /* Common IOCStatus values for all replies */
  202 #define  MPI_IOCSTATUS_SUCCESS                          (0x0000)
  203 #define  MPI_IOCSTATUS_INVALID_FUNCTION                 (0x0001)
  204 #define  MPI_IOCSTATUS_BUSY                             (0x0002)
  205 #define  MPI_IOCSTATUS_INVALID_SGL                      (0x0003)
  206 #define  MPI_IOCSTATUS_INTERNAL_ERROR                   (0x0004)
  207 #define  MPI_IOCSTATUS_RESERVED                         (0x0005)
  208 #define  MPI_IOCSTATUS_INSUFFICIENT_RESOURCES           (0x0006)
  209 #define  MPI_IOCSTATUS_INVALID_FIELD                    (0x0007)
  210 #define  MPI_IOCSTATUS_INVALID_STATE                    (0x0008)
  211 #define  MPI_IOCSTATUS_OP_STATE_NOT_SUPPORTED           (0x0009)
  212 /* Config IOCStatus values */
  213 #define  MPI_IOCSTATUS_CONFIG_INVALID_ACTION            (0x0020)
  214 #define  MPI_IOCSTATUS_CONFIG_INVALID_TYPE              (0x0021)
  215 #define  MPI_IOCSTATUS_CONFIG_INVALID_PAGE              (0x0022)
  216 #define  MPI_IOCSTATUS_CONFIG_INVALID_DATA              (0x0023)
  217 #define  MPI_IOCSTATUS_CONFIG_NO_DEFAULTS               (0x0024)
  218 #define  MPI_IOCSTATUS_CONFIG_CANT_COMMIT               (0x0025)
  219 /* SCSIIO Reply (SPI & FCP) initiator values */
  220 #define  MPI_IOCSTATUS_SCSI_RECOVERED_ERROR             (0x0040)
  221 #define  MPI_IOCSTATUS_SCSI_INVALID_BUS                 (0x0041)
  222 #define  MPI_IOCSTATUS_SCSI_INVALID_TARGETID            (0x0042)
  223 #define  MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE            (0x0043)
  224 #define  MPI_IOCSTATUS_SCSI_DATA_OVERRUN                (0x0044)
  225 #define  MPI_IOCSTATUS_SCSI_DATA_UNDERRUN               (0x0045)
  226 #define  MPI_IOCSTATUS_SCSI_IO_DATA_ERROR               (0x0046)
  227 #define  MPI_IOCSTATUS_SCSI_PROTOCOL_ERROR              (0x0047)
  228 #define  MPI_IOCSTATUS_SCSI_TASK_TERMINATED             (0x0048)
  229 #define  MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH           (0x0049)
  230 #define  MPI_IOCSTATUS_SCSI_TASK_MGMT_FAILED            (0x004A)
  231 #define  MPI_IOCSTATUS_SCSI_IOC_TERMINATED              (0x004B)
  232 #define  MPI_IOCSTATUS_SCSI_EXT_TERMINATED              (0x004C)
  233 /* For use by SCSI Initiator and SCSI Target end-to-end data protection */
  234 #define  MPI_IOCSTATUS_EEDP_GUARD_ERROR                 (0x004D)
  235 #define  MPI_IOCSTATUS_EEDP_REF_TAG_ERROR               (0x004E)
  236 #define  MPI_IOCSTATUS_EEDP_APP_TAG_ERROR               (0x004F)
  237 /* SCSI (SPI & FCP) target values */
  238 #define  MPI_IOCSTATUS_TARGET_PRIORITY_IO               (0x0060)
  239 #define  MPI_IOCSTATUS_TARGET_INVALID_PORT              (0x0061)
  240 #define  MPI_IOCSTATUS_TARGET_INVALID_IOCINDEX          (0x0062) /* obsolete */
  241 #define  MPI_IOCSTATUS_TARGET_INVALID_IO_INDEX          (0x0062)
  242 #define  MPI_IOCSTATUS_TARGET_ABORTED                   (0x0063)
  243 #define  MPI_IOCSTATUS_TARGET_NO_CONN_RETRYABLE         (0x0064)
  244 #define  MPI_IOCSTATUS_TARGET_NO_CONNECTION             (0x0065)
  245 #define  MPI_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH       (0x006A)
  246 #define  MPI_IOCSTATUS_TARGET_STS_DATA_NOT_SENT         (0x006B)
  247 #define  MPI_IOCSTATUS_TARGET_DATA_OFFSET_ERROR         (0x006D)
  248 #define  MPI_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA       (0x006E)
  249 #define  MPI_IOCSTATUS_TARGET_IU_TOO_SHORT              (0x006F)
  250 /* Additional FCP target values */
  251 #define  MPI_IOCSTATUS_TARGET_FC_ABORTED                (0x0066) /* obsolete */
  252 #define  MPI_IOCSTATUS_TARGET_FC_RX_ID_INVALID          (0x0067) /* obsolete */
  253 #define  MPI_IOCSTATUS_TARGET_FC_DID_INVALID            (0x0068) /* obsolete */
  254 #define  MPI_IOCSTATUS_TARGET_FC_NODE_LOGGED_OUT        (0x0069) /* obsolete */
  255 /* Fibre Channel Direct Access values */
  256 #define  MPI_IOCSTATUS_FC_ABORTED                       (0x0066)
  257 #define  MPI_IOCSTATUS_FC_RX_ID_INVALID                 (0x0067)
  258 #define  MPI_IOCSTATUS_FC_DID_INVALID                   (0x0068)
  259 #define  MPI_IOCSTATUS_FC_NODE_LOGGED_OUT               (0x0069)
  260 #define  MPI_IOCSTATUS_FC_EXCHANGE_CANCELED             (0x006C)
  261 /* LAN values */
  262 #define  MPI_IOCSTATUS_LAN_DEVICE_NOT_FOUND             (0x0080)
  263 #define  MPI_IOCSTATUS_LAN_DEVICE_FAILURE               (0x0081)
  264 #define  MPI_IOCSTATUS_LAN_TRANSMIT_ERROR               (0x0082)
  265 #define  MPI_IOCSTATUS_LAN_TRANSMIT_ABORTED             (0x0083)
  266 #define  MPI_IOCSTATUS_LAN_RECEIVE_ERROR                (0x0084)
  267 #define  MPI_IOCSTATUS_LAN_RECEIVE_ABORTED              (0x0085)
  268 #define  MPI_IOCSTATUS_LAN_PARTIAL_PACKET               (0x0086)
  269 #define  MPI_IOCSTATUS_LAN_CANCELED                     (0x0087)
  270 /* Serial Attached SCSI values */
  271 #define  MPI_IOCSTATUS_SAS_SMP_REQUEST_FAILED           (0x0090)
  272 #define  MPI_IOCSTATUS_SAS_SMP_DATA_OVERRUN             (0x0091)
  273 /* Inband values */
  274 #define  MPI_IOCSTATUS_INBAND_ABORTED                   (0x0098)
  275 #define  MPI_IOCSTATUS_INBAND_NO_CONNECTION             (0x0099)
  276 /* Diagnostic Tools values */
  277 #define  MPI_IOCSTATUS_DIAGNOSTIC_RELEASED              (0x00A0)
  278 
  279 #define MPI_REP_IOCLOGINFO_TYPE         (0xf<<28) /* logging info type */
  280 #define MPI_REP_IOCLOGINFO_TYPE_NONE    (0x0<<28)
  281 #define MPI_REP_IOCLOGINFO_TYPE_SCSI    (0x1<<28)
  282 #define MPI_REP_IOCLOGINFO_TYPE_FC      (0x2<<28)
  283 #define MPI_REP_IOCLOGINFO_TYPE_SAS     (0x3<<28)
  284 #define MPI_REP_IOCLOGINFO_TYPE_ISCSI   (0x4<<28)
  285 #define MPI_REP_IOCLOGINFO_DATA         (0x0fffffff) /* logging info data */
  286 
  287 /* event notification types */
  288 #define MPI_EVENT_NONE                                  0x00
  289 #define MPI_EVENT_LOG_DATA                              0x01
  290 #define MPI_EVENT_STATE_CHANGE                          0x02
  291 #define MPI_EVENT_UNIT_ATTENTION                        0x03
  292 #define MPI_EVENT_IOC_BUS_RESET                         0x04
  293 #define MPI_EVENT_EXT_BUS_RESET                         0x05
  294 #define MPI_EVENT_RESCAN                                0x06
  295 #define MPI_EVENT_LINK_STATUS_CHANGE                    0x07
  296 #define MPI_EVENT_LOOP_STATE_CHANGE                     0x08
  297 #define MPI_EVENT_LOGOUT                                0x09
  298 #define MPI_EVENT_EVENT_CHANGE                          0x0a
  299 #define MPI_EVENT_INTEGRATED_RAID                       0x0b
  300 #define MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE             0x0c
  301 #define MPI_EVENT_ON_BUS_TIMER_EXPIRED                  0x0d
  302 #define MPI_EVENT_QUEUE_FULL                            0x0e
  303 #define MPI_EVENT_SAS_DEVICE_STATUS_CHANGE              0x0f
  304 #define MPI_EVENT_SAS_SES                               0x10
  305 #define MPI_EVENT_PERSISTENT_TABLE_FULL                 0x11
  306 #define MPI_EVENT_SAS_PHY_LINK_STATUS                   0x12
  307 #define MPI_EVENT_SAS_DISCOVERY_ERROR                   0x13
  308 #define MPI_EVENT_IR_RESYNC_UPDATE                      0x14
  309 #define MPI_EVENT_IR2                                   0x15
  310 #define MPI_EVENT_SAS_DISCOVERY                         0x16
  311 #define MPI_EVENT_LOG_ENTRY_ADDED                       0x21
  312 
  313 /* messages */
  314 
  315 #define MPI_WHOINIT_NOONE               0x00
  316 #define MPI_WHOINIT_SYSTEM_BIOS         0x01
  317 #define MPI_WHOINIT_ROM_BIOS            0x02
  318 #define MPI_WHOINIT_PCI_PEER            0x03
  319 #define MPI_WHOINIT_HOST_DRIVER         0x04
  320 #define MPI_WHOINIT_MANUFACTURER        0x05
  321 
  322 /* page address fields */
  323 #define MPI_PAGE_ADDRESS_FC_BTID        (1<<24) /* Bus Target ID */
  324 
  325 /* default messages */
  326 
  327 struct mpi_msg_request {
  328         u_int8_t                reserved1;
  329         u_int8_t                reserved2;
  330         u_int8_t                chain_offset;
  331         u_int8_t                function;
  332 
  333         u_int8_t                reserved3;
  334         u_int8_t                reserved4;
  335         u_int8_t                reserved5;
  336         u_int8_t                msg_flags;
  337 
  338         u_int32_t               msg_context;
  339 } __packed __aligned(4);
  340 
  341 struct mpi_msg_reply {
  342         u_int8_t                reserved1;
  343         u_int8_t                reserved2;
  344         u_int8_t                msg_length;
  345         u_int8_t                function;
  346 
  347         u_int8_t                reserved3;
  348         u_int8_t                reserved4;
  349         u_int8_t                reserved5;
  350         u_int8_t                msg_flags;
  351 
  352         u_int32_t               msg_context;
  353 
  354         u_int8_t                reserved6;
  355         u_int8_t                reserved7;
  356         u_int16_t               ioc_status;
  357 
  358         u_int32_t               ioc_loginfo;
  359 } __packed __aligned(4);
  360 
  361 /* ioc init */
  362 
  363 struct mpi_msg_iocinit_request {
  364         u_int8_t                whoinit;
  365         u_int8_t                reserved1;
  366         u_int8_t                chain_offset;
  367         u_int8_t                function;
  368 
  369         u_int8_t                flags;
  370 #define MPI_IOCINIT_F_DISCARD_FW                        (1<<0)
  371 #define MPI_IOCINIT_F_ENABLE_HOST_FIFO                  (1<<1)
  372 #define MPI_IOCINIT_F_HOST_PG_BUF_PERSIST               (1<<2)
  373         u_int8_t                max_devices;
  374         u_int8_t                max_buses;
  375         u_int8_t                msg_flags;
  376 
  377         u_int32_t               msg_context;
  378 
  379         u_int16_t               reply_frame_size;
  380         u_int16_t               reserved2;
  381 
  382         u_int32_t               host_mfa_hi_addr;
  383 
  384         u_int32_t               sense_buffer_hi_addr;
  385 
  386         u_int32_t               reply_fifo_host_signalling_addr;
  387 
  388         struct mpi_sge          host_page_buffer_sge;
  389 
  390         u_int8_t                msg_version_min;
  391         u_int8_t                msg_version_maj;
  392 
  393         u_int8_t                hdr_version_unit;
  394         u_int8_t                hdr_version_dev;
  395 } __packed __aligned(4);
  396 
  397 struct mpi_msg_iocinit_reply {
  398         u_int8_t                whoinit;
  399         u_int8_t                reserved1;
  400         u_int8_t                msg_length;
  401         u_int8_t                function;
  402 
  403         u_int8_t                flags;
  404         u_int8_t                max_devices;
  405         u_int8_t                max_buses;
  406         u_int8_t                msg_flags;
  407 
  408         u_int32_t               msg_context;
  409 
  410         u_int16_t               reserved2;
  411         u_int16_t               ioc_status;
  412 
  413         u_int32_t               ioc_loginfo;
  414 } __packed __aligned(4);
  415 
  416 
  417 /* ioc facts */
  418 struct mpi_msg_iocfacts_request {
  419         u_int8_t                reserved1;
  420         u_int8_t                reserved2;
  421         u_int8_t                chain_offset;
  422         u_int8_t                function;
  423 
  424         u_int8_t                reserved3;
  425         u_int8_t                reserved4;
  426         u_int8_t                reserved5;
  427         u_int8_t                msg_flags;
  428 
  429         u_int32_t               msg_context;
  430 } __packed __aligned(4);
  431 
  432 struct mpi_msg_iocfacts_reply {
  433         u_int8_t                msg_version_min;
  434         u_int8_t                msg_version_maj;
  435         u_int8_t                msg_length;
  436         u_int8_t                function;
  437 
  438         u_int8_t                header_version_min;
  439         u_int8_t                header_version_maj;
  440         u_int8_t                ioc_number;
  441         u_int8_t                msg_flags;
  442 
  443         u_int32_t               msg_context;
  444 
  445         u_int16_t               ioc_exceptions;
  446 #define MPI_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL        (1<<0)
  447 #define MPI_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID         (1<<1)
  448 #define MPI_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL            (1<<2)
  449 #define MPI_IOCFACTS_EXCEPT_PERSISTENT_TABLE_FULL       (1<<3)
  450         u_int16_t               ioc_status;
  451 
  452         u_int32_t               ioc_loginfo;
  453 
  454         u_int8_t                max_chain_depth;
  455         u_int8_t                whoinit;
  456         u_int8_t                block_size;
  457         u_int8_t                flags;
  458 #define MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT             (1<<0)
  459 #define MPI_IOCFACTS_FLAGS_REPLY_FIFO_HOST_SIGNAL       (1<<1)
  460 #define MPI_IOCFACTS_FLAGS_HOST_PAGE_BUFFER_PERSISTENT  (1<<2)
  461 
  462         u_int16_t               reply_queue_depth;
  463         u_int16_t               request_frame_size;
  464 
  465         u_int16_t               reserved1;
  466         u_int16_t               product_id;     /* product id */
  467 
  468         u_int32_t               current_host_mfa_hi_addr;
  469 
  470         u_int16_t               global_credits;
  471         u_int8_t                number_of_ports;
  472         u_int8_t                event_state;
  473 
  474         u_int32_t               current_sense_buffer_hi_addr;
  475 
  476         u_int16_t               current_reply_frame_size;
  477         u_int8_t                max_devices;
  478         u_int8_t                max_buses;
  479 
  480         u_int32_t               fw_image_size;
  481 
  482         u_int32_t               ioc_capabilities;
  483 #define MPI_IOCFACTS_CAPABILITY_HIGH_PRI_Q              (1<<0)
  484 #define MPI_IOCFACTS_CAPABILITY_REPLY_HOST_SIGNAL       (1<<1)
  485 #define MPI_IOCFACTS_CAPABILITY_QUEUE_FULL_HANDLING     (1<<2)
  486 #define MPI_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER       (1<<3)
  487 #define MPI_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER         (1<<4)
  488 #define MPI_IOCFACTS_CAPABILITY_EXTENDED_BUFFER         (1<<5)
  489 #define MPI_IOCFACTS_CAPABILITY_EEDP                    (1<<6)
  490 #define MPI_IOCFACTS_CAPABILITY_BIDIRECTIONAL           (1<<7)
  491 #define MPI_IOCFACTS_CAPABILITY_MULTICAST               (1<<8)
  492 #define MPI_IOCFACTS_CAPABILITY_SCSIIO32                (1<<9)
  493 #define MPI_IOCFACTS_CAPABILITY_NO_SCSIIO16             (1<<10)
  494 
  495         u_int8_t                fw_version_dev;
  496         u_int8_t                fw_version_unit;
  497         u_int8_t                fw_version_min;
  498         u_int8_t                fw_version_maj;
  499 
  500         u_int16_t               hi_priority_queue_depth;
  501         u_int16_t               reserved2;
  502 
  503         struct mpi_sge          host_page_buffer_sge;
  504 
  505         u_int32_t               reply_fifo_host_signalling_addr;
  506 } __packed __aligned(4);
  507 
  508 struct mpi_msg_portfacts_request {
  509         u_int8_t                reserved1;
  510         u_int8_t                reserved2;
  511         u_int8_t                chain_offset;
  512         u_int8_t                function;
  513 
  514         u_int8_t                reserved3;
  515         u_int8_t                reserved4;
  516         u_int8_t                port_number;
  517         u_int8_t                msg_flags;
  518 
  519         u_int32_t               msg_context;
  520 
  521 } __packed __aligned(4);
  522 
  523 struct mpi_msg_portfacts_reply {
  524         u_int16_t               reserved1;
  525         u_int8_t                msg_length;
  526         u_int8_t                function;
  527 
  528         u_int16_t               reserved2;
  529         u_int8_t                port_number;
  530         u_int8_t                msg_flags;
  531 
  532         u_int32_t               msg_context;
  533 
  534         u_int16_t               reserved3;
  535         u_int16_t               ioc_status;
  536 
  537         u_int32_t               ioc_loginfo;
  538 
  539         u_int8_t                reserved4;
  540         u_int8_t                port_type;
  541 #define MPI_PORTFACTS_PORTTYPE_INACTIVE                 0x00
  542 #define MPI_PORTFACTS_PORTTYPE_SCSI                     0x01
  543 #define MPI_PORTFACTS_PORTTYPE_FC                       0x10
  544 #define MPI_PORTFACTS_PORTTYPE_ISCSI                    0x20
  545 #define MPI_PORTFACTS_PORTTYPE_SAS                      0x30
  546 
  547         u_int16_t               max_devices;
  548 
  549         u_int16_t               port_scsi_id;
  550         u_int16_t               protocol_flags;
  551 #define MPI_PORTFACTS_PROTOCOL_LOGBUSADDR               (1<<0)
  552 #define MPI_PORTFACTS_PROTOCOL_LAN                      (1<<1)
  553 #define MPI_PORTFACTS_PROTOCOL_TARGET                   (1<<2)
  554 #define MPI_PORTFACTS_PROTOCOL_INITIATOR                (1<<3)
  555 
  556         u_int16_t               max_posted_cmd_buffers;
  557         u_int16_t               max_persistent_ids;
  558 
  559         u_int16_t               max_lan_buckets;
  560         u_int16_t               reserved5;
  561 
  562         u_int32_t               reserved6;
  563 } __packed __aligned(4);
  564 
  565 struct mpi_msg_portenable_request {
  566         u_int16_t               reserved1;
  567         u_int8_t                chain_offset;
  568         u_int8_t                function;
  569 
  570         u_int16_t               reserved2;
  571         u_int8_t                port_number;
  572         u_int8_t                msg_flags;
  573 
  574         u_int32_t               msg_context;
  575 } __packed __aligned(4);
  576 
  577 struct mpi_msg_portenable_reply {
  578         u_int16_t               reserved1;
  579         u_int8_t                msg_length;
  580         u_int8_t                function;
  581 
  582         u_int16_t               reserved2;
  583         u_int8_t                port_number;
  584         u_int8_t                msg_flags;
  585 
  586         u_int32_t               msg_context;
  587 
  588         u_int16_t               reserved3;
  589         u_int16_t               ioc_status;
  590 
  591         u_int32_t               ioc_loginfo;
  592 } __packed __aligned(4);
  593 
  594 struct mpi_msg_event_request {
  595         u_int8_t                event_switch;
  596 #define MPI_EVENT_SWITCH_ON                             (0x01)
  597 #define MPI_EVENT_SWITCH_OFF                            (0x00)
  598         u_int8_t                reserved1;
  599         u_int8_t                chain_offset;
  600         u_int8_t                function;
  601 
  602         u_int8_t                reserved2[3];
  603         u_int8_t                msg_flags;
  604 
  605         u_int32_t               msg_context;
  606 } __packed __aligned(4);
  607 
  608 struct mpi_msg_event_reply {
  609         u_int16_t               data_length;
  610         u_int8_t                msg_length;
  611         u_int8_t                function;
  612 
  613         u_int16_t               reserved1;
  614         u_int8_t                ack_required;
  615 #define MPI_EVENT_ACK_REQUIRED                          (0x01)
  616         u_int8_t                msg_flags;
  617 #define MPI_EVENT_FLAGS_REPLY_KEPT                      (1<<7)
  618 
  619         u_int32_t               msg_context;
  620 
  621         u_int16_t               reserved2;
  622         u_int16_t               ioc_status;
  623 
  624         u_int32_t               ioc_loginfo;
  625 
  626         u_int32_t               event;
  627 
  628         u_int32_t               event_context;
  629 
  630         /* event data follows */
  631 } __packed __aligned(4);
  632 
  633 struct mpi_evt_change {
  634         u_int8_t                event_state;
  635         u_int8_t                reserved[3];
  636 } __packed __aligned(4);
  637 
  638 struct mpi_evt_link_status_change {
  639         u_int8_t                state;
  640 #define MPI_EVT_LINK_STATUS_CHANGE_OFFLINE              0x00
  641 #define MPI_EVT_LINK_STATUS_CHANGE_ACTIVE               0x01
  642         u_int8_t                _reserved1[3];
  643 
  644         u_int8_t                _reserved2[1];
  645         u_int8_t                port;
  646         u_int8_t                _reserved3[2];
  647 } __packed __aligned(4);
  648 
  649 struct mpi_evt_loop_status_change {
  650         u_int8_t                character4;
  651         u_int8_t                character3;
  652         u_int8_t                type;
  653 #define MPI_EVT_LOOP_STATUS_CHANGE_TYPE_LIP             0x01
  654 #define MPI_EVT_LOOP_STATUS_CHANGE_TYPE_LPE             0x02
  655 #define MPI_EVT_LOOP_STATUS_CHANGE_TYPE_LPB             0x03
  656         u_int8_t                _reserved1[1];
  657 
  658         u_int8_t                _reserved2[1];
  659         u_int8_t                port;
  660         u_int8_t                _reserved3[2];
  661 } __packed __aligned(4);
  662 
  663 struct mpi_evt_logout {
  664         u_int32_t               n_portid;
  665 
  666         u_int8_t                alias_index;
  667         u_int8_t                port;
  668         u_int8_t                _reserved[2];
  669 } __packed __aligned(4);
  670 
  671 struct mpi_evt_sas_phy {
  672         u_int8_t                phy_num;
  673         u_int8_t                link_rates;
  674 #define MPI_EVT_SASPHY_LINK_CUR(x)                      (((x) & 0xf0) >> 4)
  675 #define MPI_EVT_SASPHY_LINK_PREV(x)                     ((x) & 0x0f)
  676 #define MPI_EVT_SASPHY_LINK_ENABLED                     0x0
  677 #define MPI_EVT_SASPHY_LINK_DISABLED                    0x1
  678 #define MPI_EVT_SASPHY_LINK_NEGFAIL                     0x2
  679 #define MPI_EVT_SASPHY_LINK_SATAOOB                     0x3
  680 #define MPI_EVT_SASPHY_LINK_1_5GBPS                     0x8
  681 #define MPI_EVT_SASPHY_LINK_3_0GBPS                     0x9
  682         u_int16_t               dev_handle;
  683 
  684         u_int64_t               sas_addr;
  685 } __packed __aligned(4);
  686 
  687 struct mpi_evt_sas_change {
  688         u_int8_t                target;
  689         u_int8_t                bus;
  690         u_int8_t                reason;
  691 #define MPI_EVT_SASCH_REASON_ADDED                      0x03
  692 #define MPI_EVT_SASCH_REASON_NOT_RESPONDING             0x04
  693 #define MPI_EVT_SASCH_REASON_SMART_DATA                 0x05
  694 #define MPI_EVT_SASCH_REASON_NO_PERSIST_ADDED           0x06
  695 #define MPI_EVT_SASCH_REASON_UNSUPPORTED                0x07
  696 #define MPI_EVT_SASCH_REASON_INTERNAL_RESET             0x08
  697         u_int8_t                reserved1;
  698 
  699         u_int8_t                asc;
  700         u_int8_t                ascq;
  701         u_int16_t               dev_handle;
  702 
  703         u_int32_t               device_info;
  704 #define MPI_EVT_SASCH_INFO_ATAPI                        (1<<13)
  705 #define MPI_EVT_SASCH_INFO_LSI                          (1<<12)
  706 #define MPI_EVT_SASCH_INFO_DIRECT_ATTACHED              (1<<11)
  707 #define MPI_EVT_SASCH_INFO_SSP                          (1<<10)
  708 #define MPI_EVT_SASCH_INFO_STP                          (1<<9)
  709 #define MPI_EVT_SASCH_INFO_SMP                          (1<<8)
  710 #define MPI_EVT_SASCH_INFO_SATA                         (1<<7)
  711 #define MPI_EVT_SASCH_INFO_SSP_INITIATOR                (1<<6)
  712 #define MPI_EVT_SASCH_INFO_STP_INITIATOR                (1<<5)
  713 #define MPI_EVT_SASCH_INFO_SMP_INITIATOR                (1<<4)
  714 #define MPI_EVT_SASCH_INFO_SATA_HOST                    (1<<3)
  715 #define MPI_EVT_SASCH_INFO_TYPE_MASK                    0x7
  716 #define MPI_EVT_SASCH_INFO_TYPE_NONE                    0x0
  717 #define MPI_EVT_SASCH_INFO_TYPE_END                     0x1
  718 #define MPI_EVT_SASCH_INFO_TYPE_EDGE                    0x2
  719 #define MPI_EVT_SASCH_INFO_TYPE_FANOUT                  0x3
  720 
  721         u_int16_t               parent_dev_handle;
  722         u_int8_t                phy_num;
  723         u_int8_t                reserved2;
  724 
  725         u_int64_t               sas_addr;
  726 } __packed __aligned(4);
  727 
  728 struct mpi_msg_eventack_request {
  729         u_int16_t               reserved1;
  730         u_int8_t                chain_offset;
  731         u_int8_t                function;
  732 
  733         u_int8_t                reserved2[3];
  734         u_int8_t                msg_flags;
  735 
  736         u_int32_t               msg_context;
  737 
  738         u_int32_t               event;
  739 
  740         u_int32_t               event_context;
  741 } __packed __aligned(4);
  742 
  743 struct mpi_msg_eventack_reply {
  744         u_int16_t               reserved1;
  745         u_int8_t                msg_length;
  746         u_int8_t                function;
  747 
  748         u_int8_t                reserved2[3];
  749         u_int8_t                msg_flags;
  750 
  751         u_int32_t               msg_context;
  752 
  753         u_int16_t               reserved3;
  754         u_int32_t               ioc_status;
  755 
  756         u_int32_t               ioc_loginfo;
  757 } __packed __aligned(4);
  758 
  759 struct mpi_msg_fwupload_request {
  760         u_int8_t                image_type;
  761 #define MPI_FWUPLOAD_IMAGETYPE_IOC_FW                   (0x00)
  762 #define MPI_FWUPLOAD_IMAGETYPE_NV_FW                    (0x01)
  763 #define MPI_FWUPLOAD_IMAGETYPE_MPI_NV_FW                (0x02)
  764 #define MPI_FWUPLOAD_IMAGETYPE_NV_DATA                  (0x03)
  765 #define MPI_FWUPLOAD_IMAGETYPE_BOOT                     (0x04)
  766 #define MPI_FWUPLOAD_IMAGETYPE_NV_BACKUP                (0x05)
  767         u_int8_t                reserved1;
  768         u_int8_t                chain_offset;
  769         u_int8_t                function;
  770 
  771         u_int8_t                reserved2[3];
  772         u_int8_t                msg_flags;
  773 
  774         u_int32_t               msg_context;
  775 
  776         struct mpi_fw_tce       tce;
  777 
  778         /* followed by an sgl */
  779 } __packed __aligned(4);
  780 
  781 struct mpi_msg_fwupload_reply {
  782         u_int8_t                image_type;
  783         u_int8_t                reserved1;
  784         u_int8_t                msg_length;
  785         u_int8_t                function;
  786 
  787         u_int8_t                reserved2[3];
  788         u_int8_t                msg_flags;
  789 
  790         u_int32_t               msg_context;
  791 
  792         u_int16_t               reserved3;
  793         u_int16_t               ioc_status;
  794 
  795         u_int32_t               ioc_loginfo;
  796 
  797         u_int32_t               actual_image_size;
  798 } __packed __aligned(4);
  799 
  800 struct mpi_msg_scsi_io {
  801         u_int8_t                target_id;
  802         u_int8_t                bus;
  803         u_int8_t                chain_offset;
  804         u_int8_t                function;
  805 
  806         u_int8_t                cdb_length;
  807         u_int8_t                sense_buf_len;
  808         u_int8_t                reserved1;
  809         u_int8_t                msg_flags;
  810 #define MPI_SCSIIO_EEDP                                 0xf0
  811 #define MPI_SCSIIO_CMD_DATA_DIR                         (1<<2)
  812 #define MPI_SCSIIO_SENSE_BUF_LOC                        (1<<1)
  813 #define MPI_SCSIIO_SENSE_BUF_ADDR_WIDTH                 (1<<0)
  814 #define  MPI_SCSIIO_SENSE_BUF_ADDR_WIDTH_32             (0<<0)
  815 #define  MPI_SCSIIO_SENSE_BUF_ADDR_WIDTH_64             (1<<0)
  816 
  817         u_int32_t               msg_context;
  818 
  819         u_int16_t               lun[4];
  820 
  821         u_int8_t                reserved2;
  822         u_int8_t                tagging;
  823 #define MPI_SCSIIO_ATTR_SIMPLE_Q                        (0x0)
  824 #define MPI_SCSIIO_ATTR_HEAD_OF_Q                       (0x1)
  825 #define MPI_SCSIIO_ATTR_ORDERED_Q                       (0x2)
  826 #define MPI_SCSIIO_ATTR_ACA_Q                           (0x4)
  827 #define MPI_SCSIIO_ATTR_UNTAGGED                        (0x5)
  828 #define MPI_SCSIIO_ATTR_NO_DISCONNECT                   (0x7)
  829         u_int8_t                reserved3;
  830         u_int8_t                direction;
  831 #define MPI_SCSIIO_DIR_NONE                             (0x0)
  832 #define MPI_SCSIIO_DIR_WRITE                            (0x1)
  833 #define MPI_SCSIIO_DIR_READ                             (0x2)
  834 
  835 #define MPI_CDB_LEN                                     16
  836         u_int8_t                cdb[MPI_CDB_LEN];
  837 
  838         u_int32_t               data_length;
  839 
  840         u_int32_t               sense_buf_low_addr;
  841 
  842         /* followed by an sgl */
  843 } __packed __aligned(4);
  844 
  845 struct mpi_msg_scsi_io_error {
  846         u_int8_t                target_id;
  847         u_int8_t                bus;
  848         u_int8_t                msg_length;
  849         u_int8_t                function;
  850 
  851         u_int8_t                cdb_length;
  852         u_int8_t                sense_buf_len;
  853         u_int8_t                reserved1;
  854         u_int8_t                msg_flags;
  855 
  856         u_int32_t               msg_context;
  857 
  858         u_int8_t                scsi_status;
  859 #if notyet
  860 #define MPI_SCSIIO_ERR_STATUS_SUCCESS
  861 #define MPI_SCSIIO_ERR_STATUS_CHECK_COND
  862 #define MPI_SCSIIO_ERR_STATUS_BUSY
  863 #define MPI_SCSIIO_ERR_STATUS_INTERMEDIATE
  864 #define MPI_SCSIIO_ERR_STATUS_INTERMEDIATE_CONDMET
  865 #define MPI_SCSIIO_ERR_STATUS_RESERVATION_CONFLICT
  866 #define MPI_SCSIIO_ERR_STATUS_CMD_TERM
  867 #define MPI_SCSIIO_ERR_STATUS_TASK_SET_FULL
  868 #define MPI_SCSIIO_ERR_STATUS_ACA_ACTIVE
  869 #endif
  870         u_int8_t                scsi_state;
  871 #define MPI_SCSIIO_ERR_STATE_AUTOSENSE_VALID            (1<<0)
  872 #define MPI_SCSIIO_ERR_STATE_AUTOSENSE_FAILED           (1<<2)
  873 #define MPI_SCSIIO_ERR_STATE_NO_SCSI_STATUS             (1<<3)
  874 #define MPI_SCSIIO_ERR_STATE_TERMINATED                 (1<<4)
  875 #define MPI_SCSIIO_ERR_STATE_RESPONSE_INFO_VALID        (1<<5)
  876 #define MPI_SCSIIO_ERR_STATE_QUEUE_TAG_REJECTED         (1<<6)
  877         u_int16_t               ioc_status;
  878 
  879         u_int32_t               ioc_loginfo;
  880 
  881         u_int32_t               transfer_count;
  882 
  883         u_int32_t               sense_count;
  884 
  885         u_int32_t               response_info;
  886 
  887         u_int16_t               tag;
  888         u_int16_t               reserved2;
  889 } __packed __aligned(4);
  890 
  891 struct mpi_msg_scsi_task_request {
  892         u_int8_t                target_id;
  893         u_int8_t                bus;
  894         u_int8_t                chain_offset;
  895         u_int8_t                function;
  896 
  897         u_int8_t                reserved1;
  898         u_int8_t                task_type;
  899 #define MPI_MSG_SCSI_TASK_TYPE_ABORT_TASK               (0x01)
  900 #define MPI_MSG_SCSI_TASK_TYPE_ABRT_TASK_SET            (0x02)
  901 #define MPI_MSG_SCSI_TASK_TYPE_TARGET_RESET             (0x03)
  902 #define MPI_MSG_SCSI_TASK_TYPE_RESET_BUS                (0x04)
  903 #define MPI_MSG_SCSI_TASK_TYPE_LOGICAL_UNIT_RESET       (0x05)
  904         u_int8_t                reserved2;
  905         u_int8_t                msg_flags;
  906 
  907         u_int32_t               msg_context;
  908 
  909         u_int16_t               lun[4];
  910 
  911         u_int32_t               reserved3[7]; /* wtf? */
  912 
  913         u_int32_t               target_msg_context;
  914 } __packed __aligned(4);
  915 
  916 struct mpi_msg_scsi_task_reply {
  917         u_int8_t                target_id;
  918         u_int8_t                bus;
  919         u_int8_t                msg_length;
  920         u_int8_t                function;
  921 
  922         u_int8_t                response_code;
  923         u_int8_t                task_type;
  924         u_int8_t                reserved1;
  925         u_int8_t                msg_flags;
  926 
  927         u_int32_t               msg_context;
  928 
  929         u_int16_t               reserved2;
  930         u_int16_t               ioc_status;
  931 
  932         u_int32_t               ioc_loginfo;
  933 
  934         u_int32_t               termination_count;
  935 } __packed __aligned(4);
  936 
  937 struct mpi_msg_raid_action_request {
  938         u_int8_t                action;
  939 #define MPI_MSG_RAID_ACTION_STATUS                      (0x00)
  940 #define MPI_MSG_RAID_ACTION_INDICATOR_STRUCT            (0x01)
  941 #define MPI_MSG_RAID_ACTION_CREATE_VOLUME               (0x02)
  942 #define MPI_MSG_RAID_ACTION_DELETE_VOLUME               (0x03)
  943 #define MPI_MSG_RAID_ACTION_DISABLE_VOLUME              (0x04)
  944 #define MPI_MSG_RAID_ACTION_ENABLE_VOLUME               (0x05)
  945 #define MPI_MSG_RAID_ACTION_QUIESCE_PHYSIO              (0x06)
  946 #define MPI_MSG_RAID_ACTION_ENABLE_PHYSIO               (0x07)
  947 #define MPI_MSG_RAID_ACTION_CH_VOL_SETTINGS             (0x08)
  948 #define MPI_MSG_RAID_ACTION_PHYSDISK_OFFLINE            (0x0a)
  949 #define MPI_MSG_RAID_ACTION_PHYSDISK_ONLINE             (0x0b)
  950 #define MPI_MSG_RAID_ACTION_CH_PHYSDISK_SETTINGS        (0x0c)
  951 #define MPI_MSG_RAID_ACTION_CREATE_PHYSDISK             (0x0d)
  952 #define MPI_MSG_RAID_ACTION_DELETE_PHYSDISK             (0x0e)
  953 #define MPI_MSG_RAID_ACTION_PHYSDISK_FAIL               (0x0f)
  954 #define MPI_MSG_RAID_ACTION_ACTIVATE_VOLUME             (0x11)
  955 #define MPI_MSG_RAID_ACTION_DEACTIVATE_VOLUME           (0x12)
  956 #define MPI_MSG_RAID_ACTION_SET_RESYNC_RATE             (0x13)
  957 #define MPI_MSG_RAID_ACTION_SET_SCRUB_RATE              (0x14)
  958 #define MPI_MSG_RAID_ACTION_DEVICE_FW_UPDATE_MODE       (0x15)
  959 #define MPI_MSG_RAID_ACTION_SET_VOL_NAME                (0x16)
  960         u_int8_t                _reserved1;
  961         u_int8_t                chain_offset;
  962         u_int8_t                function;
  963 
  964         u_int8_t                vol_id;
  965         u_int8_t                vol_bus;
  966         u_int8_t                phys_disk_num;
  967         u_int8_t                message_flags;
  968 
  969         u_int32_t               msg_context;
  970 
  971         u_int32_t               _reserved2;
  972 
  973         u_int32_t               data_word;
  974         u_int32_t               data_sge;
  975 } __packed __aligned(4);
  976 
  977 struct mpi_msg_raid_action_reply {
  978         u_int8_t                action;
  979         u_int8_t                _reserved1;
  980         u_int8_t                message_length;
  981         u_int8_t                function;
  982 
  983         u_int8_t                vol_id;
  984         u_int8_t                vol_bus;
  985         u_int8_t                phys_disk_num;
  986         u_int8_t                message_flags;
  987 
  988         u_int32_t               message_context;
  989 
  990         u_int16_t               action_status;
  991 #define MPI_RAID_ACTION_STATUS_OK                       (0x0000)
  992 #define MPI_RAID_ACTION_STATUS_INVALID                  (0x0001)
  993 #define MPI_RAID_ACTION_STATUS_FAILURE                  (0x0002)
  994 #define MPI_RAID_ACTION_STATUS_IN_PROGRESS              (0x0004)
  995         u_int16_t               ioc_status;
  996 
  997         u_int32_t               ioc_log_info;
  998 
  999         u_int32_t               volume_status;
 1000 
 1001         u_int32_t               action_data;
 1002 } __packed __aligned(4);
 1003 
 1004 struct mpi_cfg_hdr {
 1005         u_int8_t                page_version;
 1006         u_int8_t                page_length;
 1007         u_int8_t                page_number;
 1008         u_int8_t                page_type;
 1009 #define MPI_CONFIG_REQ_PAGE_TYPE_ATTRIBUTE              (0xf0)
 1010 #define MPI_CONFIG_REQ_PAGE_TYPE_MASK                   (0x0f)
 1011 #define MPI_CONFIG_REQ_PAGE_TYPE_IO_UNIT                (0x00)
 1012 #define MPI_CONFIG_REQ_PAGE_TYPE_IOC                    (0x01)
 1013 #define MPI_CONFIG_REQ_PAGE_TYPE_BIOS                   (0x02)
 1014 #define MPI_CONFIG_REQ_PAGE_TYPE_SCSI_SPI_PORT          (0x03)
 1015 #define MPI_CONFIG_REQ_PAGE_TYPE_SCSI_SPI_DEV           (0x04)
 1016 #define MPI_CONFIG_REQ_PAGE_TYPE_FC_PORT                (0x05)
 1017 #define MPI_CONFIG_REQ_PAGE_TYPE_FC_DEV                 (0x06)
 1018 #define MPI_CONFIG_REQ_PAGE_TYPE_LAN                    (0x07)
 1019 #define MPI_CONFIG_REQ_PAGE_TYPE_RAID_VOL               (0x08)
 1020 #define MPI_CONFIG_REQ_PAGE_TYPE_MANUFACTURING          (0x09)
 1021 #define MPI_CONFIG_REQ_PAGE_TYPE_RAID_PD                (0x0A)
 1022 #define MPI_CONFIG_REQ_PAGE_TYPE_INBAND                 (0x0B)
 1023 #define MPI_CONFIG_REQ_PAGE_TYPE_EXTENDED               (0x0F)
 1024 } __packed __aligned(4);
 1025 
 1026 struct mpi_ecfg_hdr {
 1027         u_int8_t                page_version;
 1028         u_int8_t                reserved1;
 1029         u_int8_t                page_number;
 1030         u_int8_t                page_type;
 1031 
 1032         u_int16_t               ext_page_length;
 1033         u_int8_t                ext_page_type;
 1034         u_int8_t                reserved2;
 1035 } __packed __aligned(4);
 1036 
 1037 struct mpi_msg_config_request {
 1038         u_int8_t                action;
 1039 #define MPI_CONFIG_REQ_ACTION_PAGE_HEADER               (0x00)
 1040 #define MPI_CONFIG_REQ_ACTION_PAGE_READ_CURRENT         (0x01)
 1041 #define MPI_CONFIG_REQ_ACTION_PAGE_WRITE_CURRENT        (0x02)
 1042 #define MPI_CONFIG_REQ_ACTION_PAGE_DEFAULT              (0x03)
 1043 #define MPI_CONFIG_REQ_ACTION_PAGE_WRITE_NVRAM          (0x04)
 1044 #define MPI_CONFIG_REQ_ACTION_PAGE_READ_DEFAULT         (0x05)
 1045 #define MPI_CONFIG_REQ_ACTION_PAGE_READ_NVRAM           (0x06)
 1046         u_int8_t                reserved1;
 1047         u_int8_t                chain_offset;
 1048         u_int8_t                function;
 1049 
 1050         u_int16_t               ext_page_len;
 1051         u_int8_t                ext_page_type;
 1052 #define MPI_CONFIG_REQ_EXTPAGE_TYPE_SAS_IO_UNIT         (0x10)
 1053 #define MPI_CONFIG_REQ_EXTPAGE_TYPE_SAS_EXPANDER        (0x11)
 1054 #define MPI_CONFIG_REQ_EXTPAGE_TYPE_SAS_DEVICE          (0x12)
 1055 #define MPI_CONFIG_REQ_EXTPAGE_TYPE_SAS_PHY             (0x13)
 1056 #define MPI_CONFIG_REQ_EXTPAGE_TYPE_LOG                 (0x14)
 1057         u_int8_t                msg_flags;
 1058 
 1059         u_int32_t               msg_context;
 1060 
 1061         u_int32_t               reserved2[2];
 1062 
 1063         struct mpi_cfg_hdr      config_header;
 1064 
 1065         u_int32_t               page_address;
 1066 /* XXX lots of defns here */
 1067 
 1068         struct mpi_sge          page_buffer;
 1069 } __packed __aligned(4);
 1070 
 1071 struct mpi_msg_config_reply {
 1072         u_int8_t                action;
 1073         u_int8_t                reserved1;
 1074         u_int8_t                msg_length;
 1075         u_int8_t                function;
 1076 
 1077         u_int16_t               ext_page_length;
 1078         u_int8_t                ext_page_type;
 1079         u_int8_t                msg_flags;
 1080 
 1081         u_int32_t               msg_context;
 1082 
 1083         u_int16_t               reserved2;
 1084         u_int16_t               ioc_status;
 1085 
 1086         u_int32_t               ioc_loginfo;
 1087 
 1088         struct mpi_cfg_hdr      config_header;
 1089 } __packed __aligned(4);
 1090 
 1091 struct mpi_cfg_spi_port_pg0 {
 1092         struct mpi_cfg_hdr      config_header;
 1093 
 1094         u_int8_t                capabilities1;
 1095 #define MPI_CFG_SPI_PORT_0_CAPABILITIES_PACKETIZED      (1<<0)
 1096 #define MPI_CFG_SPI_PORT_0_CAPABILITIES_DT              (1<<1)
 1097 #define MPI_CFG_SPI_PORT_0_CAPABILITIES_QAS             (1<<2)
 1098         u_int8_t                min_period;
 1099         u_int8_t                max_offset;
 1100         u_int8_t                capabilities2;
 1101 #define MPI_CFG_SPI_PORT_0_CAPABILITIES_IDP             (1<<3)
 1102 #define MPI_CFG_SPI_PORT_0_CAPABILITIES_WIDTH           (1<<5)
 1103 #define  MPI_CFG_SPI_PORT_0_CAPABILITIES_WIDTH_NARROW   (0<<5)
 1104 #define  MPI_CFG_SPI_PORT_0_CAPABILITIES_WIDTH_WIDE     (1<<5)
 1105 #define MPI_CFG_SPI_PORT_0_CAPABILITIES_AIP             (1<<7)
 1106 
 1107         u_int8_t                signalling_type;
 1108 #define MPI_CFG_SPI_PORT_0_SIGNAL_HVD                   (0x1)
 1109 #define MPI_CFG_SPI_PORT_0_SIGNAL_SE                    (0x2)
 1110 #define MPI_CFG_SPI_PORT_0_SIGNAL_LVD                   (0x3)
 1111         u_int16_t               reserved;
 1112         u_int8_t                connected_id;
 1113 #define  MPI_CFG_SPI_PORT_0_CONNECTEDID_BUSFREE         (0xfe)
 1114 #define  MPI_CFG_SPI_PORT_0_CONNECTEDID_UNKNOWN         (0xff)
 1115 } __packed __aligned(4);
 1116 
 1117 struct mpi_cfg_spi_port_pg1 {
 1118         struct mpi_cfg_hdr      config_header;
 1119 
 1120         /* configuration */
 1121         u_int8_t                port_scsi_id;
 1122         u_int8_t                reserved1;
 1123         u_int16_t               port_resp_ids;
 1124 
 1125         u_int32_t               on_bus_timer_value;
 1126 
 1127         u_int8_t                target_config;
 1128 #define MPI_CFG_SPI_PORT_1_TARGCFG_TARGET_ONLY          (0x01)
 1129 #define MPI_CFG_SPI_PORT_1_TARGCFG_INIT_TARGET          (0x02)
 1130         u_int8_t                reserved2;
 1131         u_int16_t               id_config;
 1132 } __packed __aligned(4);
 1133 
 1134 struct mpi_cfg_spi_port_pg2 {
 1135         struct mpi_cfg_hdr      config_header;
 1136 
 1137         u_int32_t               port_flags;
 1138 #define MPI_CFG_SPI_PORT_2_PORT_FLAGS_SCAN_HI2LOW       (1<<0)
 1139 #define MPI_CFG_SPI_PORT_2_PORT_FLAGS_AVOID_RESET       (1<<2)
 1140 #define MPI_CFG_SPI_PORT_2_PORT_FLAGS_ALT_CHS           (1<<3)
 1141 #define MPI_CFG_SPI_PORT_2_PORT_FLAGS_TERM_DISABLED     (1<<4)
 1142 #define MPI_CFG_SPI_PORT_2_PORT_FLAGS_DV_CTL            (0x3<<5)
 1143 #define  MPI_CFG_SPI_PORT_2_PORT_FLAGS_DV_HOST_BE       (0x0<<5)
 1144 #define  MPI_CFG_SPI_PORT_2_PORT_FLAGS_DV_HOST_B        (0x1<<5)
 1145 #define  MPI_CFG_SPI_PORT_2_PORT_FLAGS_DV_HOST_NONE     (0x3<<5)
 1146 
 1147         u_int32_t               port_settings;
 1148 #define MPI_CFG_SPI_PORT_2_PORT_SET_HOST_ID             (0x7<<0)
 1149 #define MPI_CFG_SPI_PORT_2_PORT_SET_INIT_HBA            (0x3<<4)
 1150 #define  MPI_CFG_SPI_PORT_2_PORT_SET_INIT_HBA_DISABLED  (0x0<<4)
 1151 #define  MPI_CFG_SPI_PORT_2_PORT_SET_INIT_HBA_BIOS      (0x1<<4)
 1152 #define  MPI_CFG_SPI_PORT_2_PORT_SET_INIT_HBA_OS        (0x2<<4)
 1153 #define  MPI_CFG_SPI_PORT_2_PORT_SET_INIT_HBA_BIOS_OS   (0x3<<4)
 1154 #define MPI_CFG_SPI_PORT_2_PORT_SET_REMOVABLE           (0x3<<6)
 1155 #define MPI_CFG_SPI_PORT_2_PORT_SET_SPINUP_DELAY        (0xf<<8)
 1156 #define MPI_CFG_SPI_PORT_2_PORT_SET_SYNC                (0x3<<12)
 1157 #define  MPI_CFG_SPI_PORT_2_PORT_SET_NEG_SUPPORTED      (0x0<<12)
 1158 #define  MPI_CFG_SPI_PORT_2_PORT_SET_NEG_NONE           (0x1<<12)
 1159 #define  MPI_CFG_SPI_PORT_2_PORT_SET_NEG_ALL            (0x3<<12)
 1160 
 1161         struct {
 1162                 u_int8_t                timeout;
 1163                 u_int8_t                sync_factor;
 1164                 u_int16_t               device_flags;
 1165 #define MPI_CFG_SPI_PORT_2_DEV_FLAG_DISCONNECT_EN       (1<<0)
 1166 #define MPI_CFG_SPI_PORT_2_DEV_FLAG_SCAN_ID_EN          (1<<1)
 1167 #define MPI_CFG_SPI_PORT_2_DEV_FLAG_SCAN_LUN_EN         (1<<2)
 1168 #define MPI_CFG_SPI_PORT_2_DEV_FLAG_TAQ_Q_EN            (1<<3)
 1169 #define MPI_CFG_SPI_PORT_2_DEV_FLAG_WIDE_DIS            (1<<4)
 1170 #define MPI_CFG_SPI_PORT_2_DEV_FLAG_BOOT_CHOICE         (1<<5)
 1171         } __packed              device_settings[16];
 1172 };
 1173 
 1174 struct mpi_cfg_spi_dev_pg0 {
 1175         struct mpi_cfg_hdr      config_header;
 1176 
 1177         u_int8_t                neg_params1;
 1178 #define MPI_CFG_SPI_DEV_0_NEGPARAMS_PACKETIZED          (1<<0)
 1179 #define MPI_CFG_SPI_DEV_0_NEGPARAMS_DUALXFERS           (1<<1)
 1180 #define MPI_CFG_SPI_DEV_0_NEGPARAMS_QAS                 (1<<2)
 1181 #define MPI_CFG_SPI_DEV_0_NEGPARAMS_HOLD_MCS            (1<<3)
 1182 #define MPI_CFG_SPI_DEV_0_NEGPARAMS_WR_FLOW             (1<<4)
 1183 #define MPI_CFG_SPI_DEV_0_NEGPARAMS_RD_STRM             (1<<5)
 1184 #define MPI_CFG_SPI_DEV_0_NEGPARAMS_RTI                 (1<<6)
 1185 #define MPI_CFG_SPI_DEV_0_NEGPARAMS_PCOMP_EN            (1<<7)
 1186         u_int8_t                neg_period;
 1187         u_int8_t                neg_offset;
 1188         u_int8_t                neg_params2;
 1189 #define MPI_CFG_SPI_DEV_0_NEGPARAMS_IDP_EN              (1<<3)
 1190 #define MPI_CFG_SPI_DEV_0_NEGPARAMS_WIDTH               (1<<5)
 1191 #define  MPI_CFG_SPI_DEV_0_NEGPARAMS_WIDTH_NARROW       (0<<5)
 1192 #define  MPI_CFG_SPI_DEV_0_NEGPARAMS_WIDTH_WIDE         (1<<5)
 1193 #define MPI_CFG_SPI_DEV_0_NEGPARAMS_AIP                 (1<<7)
 1194 
 1195         u_int32_t               information;
 1196 #define MPI_CFG_SPI_DEV_0_INFO_NEG_OCCURRED             (1<<0)
 1197 #define MPI_CFG_SPI_DEV_0_INFO_SDTR_REJECTED            (1<<1)
 1198 #define MPI_CFG_SPI_DEV_0_INFO_WDTR_REJECTED            (1<<2)
 1199 #define MPI_CFG_SPI_DEV_0_INFO_PPR_REJECTED             (1<<3)
 1200 } __packed __aligned(4);
 1201 
 1202 struct mpi_cfg_spi_dev_pg1 {
 1203         struct mpi_cfg_hdr      config_header;
 1204 
 1205         u_int8_t                req_params1;
 1206 #define MPI_CFG_SPI_DEV_1_REQPARAMS_PACKETIZED          (1<<0)
 1207 #define MPI_CFG_SPI_DEV_1_REQPARAMS_DUALXFERS           (1<<1)
 1208 #define MPI_CFG_SPI_DEV_1_REQPARAMS_QAS                 (1<<2)
 1209 #define MPI_CFG_SPI_DEV_1_REQPARAMS_HOLD_MCS            (1<<3)
 1210 #define MPI_CFG_SPI_DEV_1_REQPARAMS_WR_FLOW             (1<<4)
 1211 #define MPI_CFG_SPI_DEV_1_REQPARAMS_RD_STRM             (1<<5)
 1212 #define MPI_CFG_SPI_DEV_1_REQPARAMS_RTI                 (1<<6)
 1213 #define MPI_CFG_SPI_DEV_1_REQPARAMS_PCOMP_EN            (1<<7)
 1214         u_int8_t                req_period;
 1215         u_int8_t                req_offset;
 1216         u_int8_t                req_params2;
 1217 #define MPI_CFG_SPI_DEV_1_REQPARAMS_IDP_EN              (1<<3)
 1218 #define MPI_CFG_SPI_DEV_1_REQPARAMS_WIDTH               (1<<5)
 1219 #define  MPI_CFG_SPI_DEV_1_REQPARAMS_WIDTH_NARROW       (0<<5)
 1220 #define  MPI_CFG_SPI_DEV_1_REQPARAMS_WIDTH_WIDE         (1<<5)
 1221 #define MPI_CFG_SPI_DEV_1_REQPARAMS_AIP                 (1<<7)
 1222 
 1223         u_int32_t               reserved;
 1224 
 1225         u_int32_t               configuration;
 1226 #define MPI_CFG_SPI_DEV_1_CONF_WDTR_DISALLOWED          (1<<1)
 1227 #define MPI_CFG_SPI_DEV_1_CONF_SDTR_DISALLOWED          (1<<2)
 1228 #define MPI_CFG_SPI_DEV_1_CONF_EXTPARAMS                (1<<3)
 1229 #define MPI_CFG_SPI_DEV_1_CONF_FORCE_PPR                (1<<4)
 1230 } __packed __aligned(4);
 1231 
 1232 struct mpi_cfg_spi_dev_pg2 {
 1233         struct mpi_cfg_hdr      config_header;
 1234 
 1235         u_int32_t               domain_validation;
 1236 #define MPI_CFG_SPI_DEV_2_DV_ISI_ENABLED                (1<<4)
 1237 #define MPI_CFG_SPI_DEV_2_DV_SECONDARY_DRV_EN           (1<<5)
 1238 #define MPI_CFG_SPI_DEV_2_DV_SLEW_RATE_CTL              (0x7<<7)
 1239 #define MPI_CFG_SPI_DEV_2_DV_PRIMARY_DRV_STRENGTH       (0x7<<10)
 1240 #define MPI_CFG_SPI_DEV_2_DV_XCLKH_ST                   (1<<28)
 1241 #define MPI_CFG_SPI_DEV_2_DV_XCLKS_ST                   (1<<29)
 1242 #define MPI_CFG_SPI_DEV_2_DV_XCLKH_DT                   (1<<30)
 1243 #define MPI_CFG_SPI_DEV_2_DV_XCLKS_DT                   (1<<31)
 1244 
 1245         u_int32_t               parity_pipe_select;
 1246 #define MPI_CFG_SPI_DEV_2_PARITY_PIPE_SELECT            (0x3)
 1247 
 1248         u_int32_t               data_pipe_select;
 1249 #define MPI_CFG_SPI_DEV_2_DATA_PIPE_SELECT(x)           (0x3<<((x)*2))
 1250 
 1251 } __packed __aligned(4);
 1252 
 1253 struct mpi_cfg_spi_dev_pg3 {
 1254         struct mpi_cfg_hdr      config_header;
 1255 
 1256         u_int16_t               msg_reject_count;
 1257         u_int16_t               phase_error_count;
 1258 
 1259         u_int16_t               parity_error_count;
 1260         u_int16_t               reserved;
 1261 } __packed __aligned(4);
 1262 
 1263 struct mpi_cfg_manufacturing_pg0 {
 1264         struct mpi_cfg_hdr      config_header;
 1265 
 1266         char                    chip_name[16];
 1267         char                    chip_revision[8];
 1268         char                    board_name[16];
 1269         char                    board_assembly[16];
 1270         char                    board_tracer_number[16];
 1271 } __packed __aligned(4);
 1272 
 1273 struct mpi_cfg_ioc_pg1 {
 1274         struct mpi_cfg_hdr      config_header;
 1275 
 1276         u_int32_t               flags;
 1277 #define MPI_CFG_IOC_1_REPLY_COALESCING                  (1<<0)
 1278 #define MPI_CFG_IOC_1_CTX_REPLY_DISABLE                 (1<<4)
 1279 
 1280         u_int32_t               coalescing_timeout;
 1281 
 1282         u_int8_t                coalescing_depth;
 1283         u_int8_t                pci_slot_num;
 1284         u_int8_t                _reserved[2];
 1285 } __packed __aligned(4);
 1286 
 1287 struct mpi_cfg_ioc_pg2 {
 1288         struct mpi_cfg_hdr      config_header;
 1289 
 1290         u_int32_t               capabilities;
 1291 #define MPI_CFG_IOC_2_CAPABILITIES_IS                   (1<<0)
 1292 #define MPI_CFG_IOC_2_CAPABILITIES_IME                  (1<<1)
 1293 #define MPI_CFG_IOC_2_CAPABILITIES_IM                   (1<<2)
 1294 #define  MPI_CFG_IOC_2_CAPABILITIES_RAID                ( \
 1295     MPI_CFG_IOC_2_CAPABILITIES_IS | MPI_CFG_IOC_2_CAPABILITIES_IME | \
 1296     MPI_CFG_IOC_2_CAPABILITIES_IM)
 1297 #define MPI_CFG_IOC_2_CAPABILITIES_SES                  (1<<29)
 1298 #define MPI_CFG_IOC_2_CAPABILITIES_SAFTE                (1<<30)
 1299 #define MPI_CFG_IOC_2_CAPABILITIES_XCHANNEL             (1<<31)
 1300 
 1301         u_int8_t                active_vols;
 1302         u_int8_t                max_vols;
 1303         u_int8_t                active_physdisks;
 1304         u_int8_t                max_physdisks;
 1305 
 1306         /* followed by a list of mpi_cfg_raid_vol structs */
 1307 } __packed __aligned(4);
 1308 
 1309 struct mpi_cfg_raid_vol {
 1310         u_int8_t                vol_id;
 1311         u_int8_t                vol_bus;
 1312         u_int8_t                vol_ioc;
 1313         u_int8_t                vol_page;
 1314 
 1315         u_int8_t                vol_type;
 1316 #define MPI_CFG_RAID_TYPE_RAID_IS                       (0x00)
 1317 #define MPI_CFG_RAID_TYPE_RAID_IME                      (0x01)
 1318 #define MPI_CFG_RAID_TYPE_RAID_IM                       (0x02)
 1319 #define MPI_CFG_RAID_TYPE_RAID_5                        (0x03)
 1320 #define MPI_CFG_RAID_TYPE_RAID_6                        (0x04)
 1321 #define MPI_CFG_RAID_TYPE_RAID_10                       (0x05)
 1322 #define MPI_CFG_RAID_TYPE_RAID_50                       (0x06)
 1323         u_int8_t                flags;
 1324 #define MPI_CFG_RAID_VOL_INACTIVE       (1<<3)
 1325         u_int16_t               reserved;
 1326 } __packed __aligned(4);
 1327 
 1328 struct mpi_cfg_ioc_pg3 {
 1329         struct mpi_cfg_hdr      config_header;
 1330 
 1331         u_int8_t                no_phys_disks;
 1332         u_int8_t                reserved[3];
 1333 
 1334         /* followed by a list of mpi_cfg_raid_physdisk structs */
 1335 } __packed __aligned(4);
 1336 
 1337 struct mpi_cfg_raid_physdisk {
 1338         u_int8_t                phys_disk_id;
 1339         u_int8_t                phys_disk_bus;
 1340         u_int8_t                phys_disk_ioc;
 1341         u_int8_t                phys_disk_num;
 1342 } __packed __aligned(4);
 1343 
 1344 struct mpi_cfg_fc_port_pg0 {
 1345         struct mpi_cfg_hdr      config_header;
 1346 
 1347         u_int32_t               flags;
 1348 
 1349         u_int8_t                mpi_port_nr;
 1350         u_int8_t                link_type;
 1351         u_int8_t                port_state;
 1352         u_int8_t                reserved1;
 1353 
 1354         u_int32_t               port_id;
 1355 
 1356         u_int64_t               wwnn;
 1357 
 1358         u_int64_t               wwpn;
 1359 
 1360         u_int32_t               supported_service_class;
 1361 
 1362         u_int32_t               supported_speeds;
 1363 
 1364         u_int32_t               current_speed;
 1365 
 1366         u_int32_t               max_frame_size;
 1367 
 1368         u_int64_t               fabric_wwnn;
 1369 
 1370         u_int64_t               fabric_wwpn;
 1371 
 1372         u_int32_t               discovered_port_count;
 1373 
 1374         u_int32_t               max_initiators;
 1375 
 1376         u_int8_t                max_aliases_supported;
 1377         u_int8_t                max_hard_aliases_supported;
 1378         u_int8_t                num_current_aliases;
 1379         u_int8_t                reserved2;
 1380 } __packed __aligned(4);
 1381 
 1382 struct mpi_cfg_fc_port_pg1 {
 1383         struct mpi_cfg_hdr      config_header;
 1384 
 1385         u_int32_t               flags;
 1386 #define MPI_CFG_FC_PORT_0_FLAGS_MAP_BY_D_ID             (1<<0)
 1387 #define MPI_CFG_FC_PORT_0_FLAGS_MAINTAIN_LOGINS         (1<<1)
 1388 #define MPI_CFG_FC_PORT_0_FLAGS_PLOGI_AFTER_LOGO        (1<<2)
 1389 #define MPI_CFG_FC_PORT_0_FLAGS_SUPPRESS_PROT_REG       (1<<3)
 1390 #define MPI_CFG_FC_PORT_0_FLAGS_MASK_RR_TOV_UNITS       (0x7<<4)
 1391 #define MPI_CFG_FC_PORT_0_FLAGS_MASK_RR_TOV_UNIT_NONE           (0x0<<4)
 1392 #define MPI_CFG_FC_PORT_0_FLAGS_MASK_RR_TOV_UNIT_0_001_SEC      (0x1<<4)
 1393 #define MPI_CFG_FC_PORT_0_FLAGS_MASK_RR_TOV_UNIT_0_1_SEC        (0x3<<4)
 1394 #define MPI_CFG_FC_PORT_0_FLAGS_MASK_RR_TOV_UNIT_10_SEC         (0x5<<4)
 1395 #define MPI_CFG_FC_PORT_0_FLAGS_TGT_LARGE_CDB_EN        (1<<7)
 1396 #define MPI_CFG_FC_PORT_0_FLAGS_SOFT_ALPA_FALLBACK      (1<<21)
 1397 #define MPI_CFG_FC_PORT_0_FLAGS_PORT_OFFLINE            (1<<22)
 1398 #define MPI_CFG_FC_PORT_0_FLAGS_TGT_MODE_OXID           (1<<23)
 1399 #define MPI_CFG_FC_PORT_0_FLAGS_VERBOSE_RESCAN          (1<<24)
 1400 #define MPI_CFG_FC_PORT_0_FLAGS_FORCE_NOSEEPROM_WWNS    (1<<25)
 1401 #define MPI_CFG_FC_PORT_0_FLAGS_IMMEDIATE_ERROR         (1<<26)
 1402 #define MPI_CFG_FC_PORT_0_FLAGS_EXT_FCP_STATUS_EN       (1<<27)
 1403 #define MPI_CFG_FC_PORT_0_FLAGS_REQ_PROT_LOG_BUS_ADDR   (1<<28)
 1404 #define MPI_CFG_FC_PORT_0_FLAGS_REQ_PROT_LAN            (1<<29)
 1405 #define MPI_CFG_FC_PORT_0_FLAGS_REQ_PROT_TARGET         (1<<30)
 1406 #define MPI_CFG_FC_PORT_0_FLAGS_REQ_PROT_INITIATOR      (1<<31)
 1407 
 1408         u_int64_t               noseepromwwnn;
 1409 
 1410         u_int64_t               noseepromwwpn;
 1411 
 1412         u_int8_t                hard_alpa;
 1413         u_int8_t                link_config;
 1414         u_int8_t                topology_config;
 1415         u_int8_t                alt_connector;
 1416 
 1417         u_int8_t                num_req_aliases;
 1418         u_int8_t                rr_tov;
 1419         u_int8_t                initiator_dev_to;
 1420         u_int8_t                initiator_lo_pend_to;
 1421 } __packed __aligned(4);
 1422 
 1423 struct mpi_cfg_fc_device_pg0 {
 1424         struct mpi_cfg_hdr      config_header;
 1425 
 1426         u_int64_t               wwnn;
 1427 
 1428         u_int64_t               wwpn;
 1429 
 1430         u_int32_t               port_id;
 1431 
 1432         u_int8_t                protocol;
 1433         u_int8_t                flags;
 1434 #define MPI_CFG_FC_DEV_0_FLAGS_BUSADDR_VALID            (1<<0)
 1435 #define MPI_CFG_FC_DEV_0_FLAGS_PLOGI_INVALID            (1<<1)
 1436 #define MPI_CFG_FC_DEV_0_FLAGS_PRLI_INVALID             (1<<2)
 1437         u_int16_t               bb_credit;
 1438 
 1439         u_int16_t               max_rx_frame_size;
 1440         u_int8_t                adisc_hard_alpa;
 1441         u_int8_t                port_nr;
 1442 
 1443         u_int8_t                fc_ph_low_version;
 1444         u_int8_t                fc_ph_high_version;
 1445         u_int8_t                current_target_id;
 1446         u_int8_t                current_bus;
 1447 } __packed __aligned(4);
 1448 
 1449 struct mpi_raid_settings {
 1450         u_int16_t               volume_settings;
 1451 #define MPI_CFG_RAID_VOL_0_SETTINGS_WRITE_CACHE_EN      (1<<0)
 1452 #define MPI_CFG_RAID_VOL_0_SETTINGS_OFFLINE_SMART_ERR   (1<<1)
 1453 #define MPI_CFG_RAID_VOL_0_SETTINGS_OFFLINE_SMART       (1<<2)
 1454 #define MPI_CFG_RAID_VOL_0_SETTINGS_AUTO_SWAP           (1<<3)
 1455 #define MPI_CFG_RAID_VOL_0_SETTINGS_HI_PRI_RESYNC       (1<<4)
 1456 #define MPI_CFG_RAID_VOL_0_SETTINGS_PROD_SUFFIX         (1<<5)
 1457 #define MPI_CFG_RAID_VOL_0_SETTINGS_FAST_SCRUB          (1<<6) /* obsolete */
 1458 #define MPI_CFG_RAID_VOL_0_SETTINGS_DEFAULTS            (1<<15)
 1459         u_int8_t                hot_spare_pool;
 1460         u_int8_t                reserved2;
 1461 } __packed __aligned(4);
 1462 
 1463 struct mpi_cfg_raid_vol_pg0 {
 1464         struct mpi_cfg_hdr      config_header;
 1465 
 1466         u_int8_t                volume_id;
 1467         u_int8_t                volume_bus;
 1468         u_int8_t                volume_ioc;
 1469         u_int8_t                volume_type;
 1470 
 1471         u_int8_t                volume_status;
 1472 #define MPI_CFG_RAID_VOL_0_STATUS_ENABLED               (1<<0)
 1473 #define MPI_CFG_RAID_VOL_0_STATUS_QUIESCED              (1<<1)
 1474 #define MPI_CFG_RAID_VOL_0_STATUS_RESYNCING             (1<<2)
 1475 #define MPI_CFG_RAID_VOL_0_STATUS_ACTIVE                (1<<3)
 1476 #define MPI_CFG_RAID_VOL_0_STATUS_BADBLOCK_FULL         (1<<4)
 1477         u_int8_t                volume_state;
 1478 #define MPI_CFG_RAID_VOL_0_STATE_OPTIMAL                (0x00)
 1479 #define MPI_CFG_RAID_VOL_0_STATE_DEGRADED               (0x01)
 1480 #define MPI_CFG_RAID_VOL_0_STATE_FAILED                 (0x02)
 1481 #define MPI_CFG_RAID_VOL_0_STATE_MISSING                (0x03)
 1482         u_int16_t               _reserved1;
 1483 
 1484         struct mpi_raid_settings settings;
 1485 
 1486         u_int32_t               max_lba;
 1487 
 1488         u_int32_t               _reserved2;
 1489 
 1490         u_int32_t               stripe_size;
 1491 
 1492         u_int32_t               _reserved3;
 1493 
 1494         u_int32_t               _reserved4;
 1495 
 1496         u_int8_t                num_phys_disks;
 1497         u_int8_t                data_scrub_rate;
 1498         u_int8_t                resync_rate;
 1499         u_int8_t                inactive_status;
 1500 #define MPI_CFG_RAID_VOL_0_INACTIVE_UNKNOWN             (0x00)
 1501 #define MPI_CFG_RAID_VOL_0_INACTIVE_STALE_META          (0x01)
 1502 #define MPI_CFG_RAID_VOL_0_INACTIVE_FOREIGN_VOL         (0x02)
 1503 #define MPI_CFG_RAID_VOL_0_INACTIVE_NO_RESOURCES        (0x03)
 1504 #define MPI_CFG_RAID_VOL_0_INACTIVE_CLONED_VOL          (0x04)
 1505 #define MPI_CFG_RAID_VOL_0_INACTIVE_INSUF_META          (0x05)
 1506 
 1507         /* followed by a list of mpi_cfg_raid_vol_pg0_physdisk structs */
 1508 } __packed __aligned(4);
 1509 
 1510 struct mpi_cfg_raid_vol_pg0_physdisk {
 1511         u_int16_t               reserved;
 1512         u_int8_t                phys_disk_map;
 1513         u_int8_t                phys_disk_num;
 1514 } __packed __aligned(4);
 1515 
 1516 struct mpi_cfg_raid_vol_pg1 {
 1517         struct mpi_cfg_hdr      config_header;
 1518 
 1519         u_int8_t                volume_id;
 1520         u_int8_t                volume_bus;
 1521         u_int8_t                volume_ioc;
 1522         u_int8_t                reserved1;
 1523 
 1524         u_int8_t                guid[24];
 1525 
 1526         u_int8_t                name[32];
 1527 
 1528         u_int64_t               wwid;
 1529 
 1530         u_int32_t               reserved2;
 1531 
 1532         u_int32_t               reserved3;
 1533 } __packed __aligned(4);
 1534 
 1535 struct mpi_cfg_raid_physdisk_pg0 {
 1536         struct mpi_cfg_hdr      config_header;
 1537 
 1538         u_int8_t                phys_disk_id;
 1539         u_int8_t                phys_disk_bus;
 1540         u_int8_t                phys_disk_ioc;
 1541         u_int8_t                phys_disk_num;
 1542 
 1543         u_int8_t                enc_id;
 1544         u_int8_t                enc_bus;
 1545         u_int8_t                hot_spare_pool;
 1546         u_int8_t                enc_type;
 1547 #define MPI_CFG_RAID_PHYDISK_0_ENCTYPE_NONE             (0x0)
 1548 #define MPI_CFG_RAID_PHYDISK_0_ENCTYPE_SAFTE            (0x1)
 1549 #define MPI_CFG_RAID_PHYDISK_0_ENCTYPE_SES              (0x2)
 1550 
 1551         u_int32_t               reserved1;
 1552 
 1553         u_int8_t                ext_disk_id[8];
 1554 
 1555         u_int8_t                disk_id[16];
 1556 
 1557         u_int8_t                vendor_id[8];
 1558 
 1559         u_int8_t                product_id[16];
 1560 
 1561         u_int8_t                product_rev[4];
 1562 
 1563         u_int8_t                info[32];
 1564 
 1565         u_int8_t                phys_disk_status;
 1566 #define MPI_CFG_RAID_PHYDISK_0_STATUS_OUTOFSYNC         (1<<0)
 1567 #define MPI_CFG_RAID_PHYDISK_0_STATUS_QUIESCED          (1<<1)
 1568         u_int8_t                phys_disk_state;
 1569 #define MPI_CFG_RAID_PHYDISK_0_STATE_ONLINE             (0x00)
 1570 #define MPI_CFG_RAID_PHYDISK_0_STATE_MISSING            (0x01)
 1571 #define MPI_CFG_RAID_PHYDISK_0_STATE_INCOMPAT           (0x02)
 1572 #define MPI_CFG_RAID_PHYDISK_0_STATE_FAILED             (0x03)
 1573 #define MPI_CFG_RAID_PHYDISK_0_STATE_INIT               (0x04)
 1574 #define MPI_CFG_RAID_PHYDISK_0_STATE_OFFLINE            (0x05)
 1575 #define MPI_CFG_RAID_PHYDISK_0_STATE_HOSTFAIL           (0x06)
 1576 #define MPI_CFG_RAID_PHYDISK_0_STATE_OTHER              (0xff)
 1577         u_int16_t               reserved2;
 1578 
 1579         u_int32_t               max_lba;
 1580 
 1581         u_int8_t                error_cdb_byte;
 1582         u_int8_t                error_sense_key;
 1583         u_int16_t               reserved3;
 1584 
 1585         u_int16_t               error_count;
 1586         u_int8_t                error_asc;
 1587         u_int8_t                error_ascq;
 1588 
 1589         u_int16_t               smart_count;
 1590         u_int8_t                smart_asc;
 1591         u_int8_t                smart_ascq;
 1592 } __packed __aligned(4);
 1593 
 1594 struct mpi_cfg_raid_physdisk_pg1 {
 1595         struct mpi_cfg_hdr      config_header;
 1596 
 1597         u_int8_t                num_phys_disk_paths;
 1598         u_int8_t                phys_disk_num;
 1599         u_int16_t               reserved1;
 1600 
 1601         u_int32_t               reserved2;
 1602 
 1603         /* followed by mpi_cfg_raid_physdisk_path structs */
 1604 } __packed __aligned(4);
 1605 
 1606 struct mpi_cfg_raid_physdisk_path {
 1607         u_int8_t                phys_disk_id;
 1608         u_int8_t                phys_disk_bus;
 1609         u_int16_t               reserved1;
 1610 
 1611         u_int64_t               wwwid;
 1612 
 1613         u_int64_t               owner_wwid;
 1614 
 1615         u_int8_t                ownder_id;
 1616         u_int8_t                reserved2;
 1617         u_int16_t               flags;
 1618 #define MPI_CFG_RAID_PHYDISK_PATH_INVALID               (1<<0)
 1619 #define MPI_CFG_RAID_PHYDISK_PATH_BROKEN                (1<<1)
 1620 } __packed __aligned(4);
 1621 
 1622 struct mpi_cfg_sas_iou_pg0 {
 1623         struct mpi_ecfg_hdr     config_header;
 1624 
 1625         u_int16_t               nvdata_version_default;
 1626         u_int16_t               nvdata_version_persistent;
 1627 
 1628         u_int8_t                num_phys;
 1629         u_int8_t                _reserved1[3];
 1630 
 1631         /* followed by mpi_cfg_sas_iou_pg0_phy structs */
 1632 } __packed __aligned(4);
 1633 
 1634 struct mpi_cfg_sas_iou_pg0_phy {
 1635         u_int8_t                port;
 1636         u_int8_t                port_flags;
 1637         u_int8_t                phy_flags;
 1638         u_int8_t                negotiated_link_rate;
 1639 
 1640         u_int32_t               controller_phy_dev_info;
 1641 
 1642         u_int16_t               attached_dev_handle;
 1643         u_int16_t               controller_dev_handle;
 1644 
 1645         u_int32_t               discovery_status;
 1646 } __packed __aligned(4);
 1647 
 1648 struct mpi_cfg_sas_iou_pg1 {
 1649         struct mpi_ecfg_hdr     config_header;
 1650 
 1651         u_int16_t               control_flags;
 1652         u_int16_t               max_sata_targets;
 1653 
 1654         u_int16_t               additional_control_flags;
 1655         u_int16_t               _reserved1;
 1656 
 1657         u_int8_t                num_phys;
 1658         u_int8_t                max_sata_q_depth;
 1659         u_int8_t                report_dev_missing_delay;
 1660         u_int8_t                io_dev_missing_delay;
 1661 
 1662         /* followed by mpi_cfg_sas_iou_pg1_phy structs */
 1663 } __packed __aligned(4);
 1664 
 1665 struct mpi_cfg_sas_iou_pg1_phy {
 1666         u_int8_t                port;
 1667         u_int8_t                port_flags;
 1668         u_int8_t                phy_flags;
 1669         u_int8_t                max_min_link_rate;
 1670 
 1671         u_int32_t               controller_phy_dev_info;
 1672 
 1673         u_int16_t               max_target_port_connect_time;
 1674         u_int16_t               _reserved1;
 1675 } __packed __aligned(4);
 1676 
 1677 #define MPI_CFG_SAS_DEV_ADDR_NEXT               (0<<28)
 1678 #define MPI_CFG_SAS_DEV_ADDR_BUS                (1<<28)
 1679 #define MPI_CFG_SAS_DEV_ADDR_HANDLE             (2<<28)
 1680 
 1681 struct mpi_cfg_sas_dev_pg0 {
 1682         struct mpi_ecfg_hdr     config_header;
 1683 
 1684         u_int16_t               slot;
 1685         u_int16_t               enc_handle;
 1686 
 1687         u_int64_t               sas_addr;
 1688 
 1689         u_int16_t               parent_dev_handle;
 1690         u_int8_t                phy_num;
 1691         u_int8_t                access_status;
 1692 
 1693         u_int16_t               dev_handle;
 1694         u_int8_t                target;
 1695         u_int8_t                bus;
 1696 
 1697         u_int32_t               device_info;
 1698 #define MPI_CFG_SAS_DEV_0_DEVINFO_TYPE                  (0x7)
 1699 #define MPI_CFG_SAS_DEV_0_DEVINFO_TYPE_NONE             (0x0)
 1700 #define MPI_CFG_SAS_DEV_0_DEVINFO_TYPE_END              (0x1)
 1701 #define MPI_CFG_SAS_DEV_0_DEVINFO_TYPE_EDGE_EXPANDER    (0x2)
 1702 #define MPI_CFG_SAS_DEV_0_DEVINFO_TYPE_FANOUT_EXPANDER  (0x3)
 1703 #define MPI_CFG_SAS_DEV_0_DEVINFO_SATA_HOST             (1<<3)
 1704 #define MPI_CFG_SAS_DEV_0_DEVINFO_SMP_INITIATOR         (1<<4)
 1705 #define MPI_CFG_SAS_DEV_0_DEVINFO_STP_INITIATOR         (1<<5)
 1706 #define MPI_CFG_SAS_DEV_0_DEVINFO_SSP_INITIATOR         (1<<6)
 1707 #define MPI_CFG_SAS_DEV_0_DEVINFO_SATA_DEVICE           (1<<7)
 1708 #define MPI_CFG_SAS_DEV_0_DEVINFO_SMP_TARGET            (1<<8)
 1709 #define MPI_CFG_SAS_DEV_0_DEVINFO_STP_TARGET            (1<<9)
 1710 #define MPI_CFG_SAS_DEV_0_DEVINFO_SSP_TARGET            (1<<10)
 1711 #define MPI_CFG_SAS_DEV_0_DEVINFO_DIRECT_ATTACHED       (1<<11)
 1712 #define MPI_CFG_SAS_DEV_0_DEVINFO_LSI_DEVICE            (1<<12)
 1713 #define MPI_CFG_SAS_DEV_0_DEVINFO_ATAPI_DEVICE          (1<<13)
 1714 #define MPI_CFG_SAS_DEV_0_DEVINFO_SEP_DEVICE            (1<<14)
 1715 
 1716         u_int16_t               flags;
 1717 #define MPI_CFG_SAS_DEV_0_FLAGS_DEV_PRESENT             (1<<0)
 1718 #define MPI_CFG_SAS_DEV_0_FLAGS_DEV_MAPPED              (1<<1)
 1719 #define MPI_CFG_SAS_DEV_0_FLAGS_DEV_MAPPED_PERSISTENT   (1<<2)
 1720 #define MPI_CFG_SAS_DEV_0_FLAGS_SATA_PORT_SELECTOR      (1<<3)
 1721 #define MPI_CFG_SAS_DEV_0_FLAGS_SATA_FUA                (1<<4)
 1722 #define MPI_CFG_SAS_DEV_0_FLAGS_SATA_NCQ                (1<<5)
 1723 #define MPI_CFG_SAS_DEV_0_FLAGS_SATA_SMART              (1<<6)
 1724 #define MPI_CFG_SAS_DEV_0_FLAGS_SATA_LBA48              (1<<7)
 1725 #define MPI_CFG_SAS_DEV_0_FLAGS_UNSUPPORTED             (1<<8)
 1726 #define MPI_CFG_SAS_DEV_0_FLAGS_SATA_SETTINGS           (1<<9)
 1727         u_int8_t                physical_port;
 1728         u_int8_t                reserved;
 1729 } __packed __aligned(4);
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FreeBSD/Linux Kernel Cross Reference sys/dev/ic/mpireg.h

FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/mpireg.h
