The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/ncr5380reg.h

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    1 /*      $NetBSD: ncr5380reg.h,v 1.7 2005/12/11 12:21:28 christos Exp $  */
    2 
    3 /*
    4  * Mach Operating System
    5  * Copyright (c) 1991,1990,1989 Carnegie Mellon University
    6  * All Rights Reserved.
    7  *
    8  * Permission to use, copy, modify and distribute this software and its
    9  * documentation is hereby granted, provided that both the copyright
   10  * notice and this permission notice appear in all copies of the
   11  * software, derivative works or modified versions, and any portions
   12  * thereof, and that both notices appear in supporting documentation.
   13  *
   14  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
   15  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
   16  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
   17  *
   18  * Carnegie Mellon requests users of this software to return to
   19  *
   20  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
   21  *  School of Computer Science
   22  *  Carnegie Mellon University
   23  *  Pittsburgh PA 15213-3890
   24  *
   25  * any improvements or extensions that they make and grant Carnegie the
   26  * rights to redistribute these changes.
   27  */
   28 /*
   29  * HISTORY (mach3)
   30  * Revision 2.3  91/08/24  12:25:10  af
   31  *      Moved padding of regmap in impl file.
   32  *      [91/08/02  04:22:39  af]
   33  *
   34  * Revision 2.2  91/06/19  16:28:35  rvb
   35  *      From the NCR data sheets
   36  *      "NCR 5380 Family, SCSI Protocol Controller Data Manual"
   37  *      NCR Microelectronics Division, Colorado Spring, 6/98 T01891L
   38  *      [91/04/21            af]
   39  *
   40  */
   41 
   42 /*
   43  *      File: scsi_5380.h
   44  *      Author: Alessandro Forin, Carnegie Mellon University
   45  *      Date:   5/91
   46  *
   47  *      Defines for the NCR 5380 (SCSI chip), aka Am5380
   48  */
   49 
   50 /*
   51  * Register map:  Note not declared here anymore!
   52  * All the 5380 registers are accessed through individual
   53  * pointers initialized by MD code.  This allows the 5380
   54  * MI functions to be shared between MD drivers that have
   55  * different padding between the registers (i.e. amiga).
   56  */
   57 #if 0   /* example only */
   58 struct ncr5380regs {
   59         volatile u_char sci_r0;
   60         volatile u_char sci_r1;
   61         volatile u_char sci_r2;
   62         volatile u_char sci_r3;
   63         volatile u_char sci_r4;
   64         volatile u_char sci_r5;
   65         volatile u_char sci_r6;
   66         volatile u_char sci_r7;
   67 };
   68 #endif
   69 
   70 /*
   71  * Machine-independent code uses these names:
   72  */
   73 #define sci_data        sci_r0  /* r:  Current data */
   74 #define sci_odata       sci_r0  /* w:  Out data */
   75 
   76 #define sci_icmd        sci_r1  /* rw: Initiator command */
   77 #define sci_mode        sci_r2  /* rw: Mode */
   78 #define sci_tcmd        sci_r3  /* rw: Target command */
   79 
   80 #define sci_bus_csr     sci_r4  /* r:  Bus Status */
   81 #define sci_sel_enb sci_r4      /* w:  Select enable */
   82 
   83 #define sci_csr          sci_r5 /* r:  Status */
   84 #define sci_dma_send sci_r5     /* w:  Start DMA send data */
   85 
   86 #define sci_idata       sci_r6  /* r:  Input data */
   87 #define sci_trecv       sci_r6  /* w:  Start DMA receive, target */
   88 
   89 #define sci_iack        sci_r7  /* r:  Interrupt Acknowledge  */
   90 #define sci_irecv       sci_r7  /* w:  Start DMA receive, initiator */
   91 
   92 
   93 /*
   94  * R1: Initiator command register
   95  */
   96 #define SCI_ICMD_DATA           0x01            /* rw: Assert data bus   */
   97 #define SCI_ICMD_ATN            0x02            /* rw: Assert ATN signal */
   98 #define SCI_ICMD_SEL            0x04            /* rw: Assert SEL signal */
   99 #define SCI_ICMD_BSY            0x08            /* rw: Assert BSY signal */
  100 #define SCI_ICMD_ACK            0x10            /* rw: Assert ACK signal */
  101 #define SCI_ICMD_LST            0x20            /* r:  Lost arbitration */
  102 #define SCI_ICMD_DIFF   SCI_ICMD_LST            /* w:  Differential cable */
  103 #define SCI_ICMD_AIP            0x40            /* r:  Arbitration in progress */
  104 #define SCI_ICMD_TEST   SCI_ICMD_AIP            /* w:  Test mode */
  105 #define SCI_ICMD_RST            0x80            /* rw: Assert RST signal */
  106 /* Bits to keep when doing read/modify/write (leave out RST) */
  107 #define SCI_ICMD_RMASK          0x1F
  108 
  109 
  110 /*
  111  * R2: Mode register
  112  */
  113 #define SCI_MODE_ARB            0x01            /* rw: Start arbitration */
  114 #define SCI_MODE_DMA            0x02            /* rw: Enable DMA xfers */
  115 #define SCI_MODE_MONBSY         0x04            /* rw: Monitor BSY signal */
  116 #define SCI_MODE_DMA_IE         0x08            /* rw: Enable DMA complete interrupt */
  117 #define SCI_MODE_PERR_IE        0x10            /* rw: Interrupt on parity errors */
  118 #define SCI_MODE_PAR_CHK        0x20            /* rw: Check parity */
  119 #define SCI_MODE_TARGET         0x40            /* rw: Target mode (Initiator if 0) */
  120 #define SCI_MODE_BLOCKDMA       0x80            /* rw: Block-mode DMA handshake */
  121 
  122 
  123 /*
  124  * R3: Target command register
  125  */
  126 #define SCI_TCMD_IO             0x01            /* rw: Assert I/O signal */
  127 #define SCI_TCMD_CD             0x02            /* rw: Assert C/D signal */
  128 #define SCI_TCMD_MSG            0x04            /* rw: Assert MSG signal */
  129 #define SCI_TCMD_PHASE_MASK     0x07            /* r:  Mask for current bus phase */
  130 #define SCI_TCMD_REQ            0x08            /* rw: Assert REQ signal */
  131 #define SCI_TCMD_LAST_SENT      0x80            /* ro: Last byte was xferred
  132                                                  *     (not on 5380/1) */
  133 
  134 #define SCI_TCMD_PHASE(x)               ((x) & 0x7)
  135 
  136 /*
  137  * R4: Current (SCSI) Bus status (.sci_bus_csr)
  138  */
  139 #define SCI_BUS_DBP             0x01            /* r:  Data Bus parity */
  140 #define SCI_BUS_SEL             0x02            /* r:  SEL signal */
  141 #define SCI_BUS_IO              0x04            /* r:  I/O signal */
  142 #define SCI_BUS_CD              0x08            /* r:  C/D signal */
  143 #define SCI_BUS_MSG             0x10            /* r:  MSG signal */
  144 #define SCI_BUS_REQ             0x20            /* r:  REQ signal */
  145 #define SCI_BUS_BSY             0x40            /* r:  BSY signal */
  146 #define SCI_BUS_RST             0x80            /* r:  RST signal */
  147 
  148 #define SCI_BUS_PHASE(x)        (((x) >> 2) & 7)
  149 
  150 /*
  151  * R5: Bus and Status register (.sci_csr)
  152  */
  153 #define SCI_CSR_ACK             0x01            /* r:  ACK signal */
  154 #define SCI_CSR_ATN             0x02            /* r:  ATN signal */
  155 #define SCI_CSR_DISC            0x04            /* r:  Disconnected (BSY==0) */
  156 #define SCI_CSR_PHASE_MATCH     0x08            /* r:  Bus and SCI_TCMD match */
  157 #define SCI_CSR_INT             0x10            /* r:  Interrupt request */
  158 #define SCI_CSR_PERR            0x20            /* r:  Parity error */
  159 #define SCI_CSR_DREQ            0x40            /* r:  DMA request */
  160 #define SCI_CSR_DONE            0x80            /* r:  DMA count is zero */

Cache object: 55af0ed46fd170c56c0bf8d91d3ae0de


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