The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/ncr5380var.h

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    1 /*      $NetBSD: ncr5380var.h,v 1.28 2005/02/04 02:10:36 perry Exp $    */
    2 
    3 /*
    4  * Copyright (c) 1995 David Jones, Gordon W. Ross
    5  * Copyright (c) 1994 Jarle Greipsland
    6  * All rights reserved.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  * 3. The name of the authors may not be used to endorse or promote products
   17  *    derived from this software without specific prior written permission.
   18  * 4. All advertising materials mentioning features or use of this software
   19  *    must display the following acknowledgement:
   20  *      This product includes software developed by
   21  *      David Jones and Gordon Ross
   22  *
   23  * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
   24  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   25  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   26  * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
   27  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   28  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   29  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   30  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   32  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   33  */
   34 
   35 /*
   36  * This file defines the interface between the machine-dependent
   37  * module and the machine-independent ncr5380sbc.c module.
   38  */
   39 
   40 /*
   41  * Currently acorn26, amd64, alpha, i386, mips, news68k, sparc, sun2, and vax
   42  * use real bus space:
   43  *      acorn32: csa driver; easy to convert
   44  *      mac68k: sbc driver; easy to convert
   45  *      pc532: ncr driver; need bus.h first
   46  *      sun3: si driver; need bus.h first
   47  */
   48 #if defined(acorn26) || \
   49     defined(__alpha__) || \
   50     defined(__amd64__) || \
   51     defined(__i386__) || \
   52     defined(__mips__) || \
   53     defined(news68k) || \
   54     defined(__sparc__) || \
   55     defined(sun2) || \
   56     defined(__vax__)
   57 # define NCR5380_USE_BUS_SPACE
   58 #endif
   59 
   60 /*
   61  * Handy read/write macros
   62  */
   63 #ifdef NCR5380_USE_BUS_SPACE
   64 # include <machine/bus.h>
   65 /* bus_space() variety */
   66 # define NCR5380_READ(sc, reg)          bus_space_read_1(sc->sc_regt, \
   67                                             sc->sc_regh, sc->reg)
   68 # define NCR5380_WRITE(sc, reg, val)    bus_space_write_1(sc->sc_regt, \
   69                                             sc->sc_regh, sc->reg, val)
   70 #else
   71 /* legacy memory-mapped variety */
   72 # define NCR5380_READ(sc, reg)          (*sc->reg)
   73 # define NCR5380_WRITE(sc, reg, val)    do { *(sc->reg) = val; } while (0)
   74 #endif
   75 
   76 #define SCI_CLR_INTR(sc)        NCR5380_READ(sc, sci_iack)
   77 #define SCI_BUSY(sc)            (NCR5380_READ(sc, sci_bus_csr) & SCI_BUS_BSY)
   78 
   79 /* These are NOT artibtrary, but map to bits in sci_tcmd */
   80 #define PHASE_DATA_OUT  0x0
   81 #define PHASE_DATA_IN   0x1
   82 #define PHASE_COMMAND   0x2
   83 #define PHASE_STATUS    0x3
   84 #define PHASE_UNSPEC1   0x4
   85 #define PHASE_UNSPEC2   0x5
   86 #define PHASE_MSG_OUT   0x6
   87 #define PHASE_MSG_IN    0x7
   88 
   89 /*
   90  * This illegal phase is used to prevent the 5380 from having
   91  * a phase-match condition when we don't want one, such as
   92  * when setting up the DMA engine or whatever...
   93  */
   94 #define PHASE_INVALID   PHASE_UNSPEC1
   95 
   96 
   97 /* Per-request state.  This is required in order to support reselection. */
   98 struct sci_req {
   99         struct          scsipi_xfer *sr_xs;     /* Pointer to xfer struct, NULL=unused */
  100         int             sr_target, sr_lun;      /* For fast access */
  101         void            *sr_dma_hand;           /* Current DMA hnadle */
  102         u_char          *sr_dataptr;            /* Saved data pointer */
  103         int             sr_datalen;
  104         int             sr_flags;               /* Internal error code */
  105 #define SR_IMMED                        1       /* Immediate command */
  106 #define SR_SENSE                        2       /* We are getting sense */
  107 #define SR_OVERDUE                      4       /* Timeout while not current */
  108 #define SR_ERROR                        8       /* Error occurred */
  109         int             sr_status;              /* Status code from last cmd */
  110 };
  111 #define SCI_OPENINGS    16              /* How many commands we can enqueue. */
  112 
  113 
  114 struct ncr5380_softc {
  115         struct device           sc_dev;
  116         struct scsipi_adapter   sc_adapter;
  117         struct scsipi_channel   sc_channel;
  118 
  119 #ifdef NCR5380_USE_BUS_SPACE
  120         /* Pointers to bus_space */
  121         bus_space_tag_t         sc_regt;
  122         bus_space_handle_t      sc_regh;
  123 
  124         /* Pointers to 5380 registers.  */
  125         bus_size_t      sci_r0;
  126         bus_size_t      sci_r1;
  127         bus_size_t      sci_r2;
  128         bus_size_t      sci_r3;
  129         bus_size_t      sci_r4;
  130         bus_size_t      sci_r5;
  131         bus_size_t      sci_r6;
  132         bus_size_t      sci_r7;
  133 #else
  134         /* Pointers to 5380 registers.  See ncr5380reg.h */
  135         volatile u_char *sci_r0;
  136         volatile u_char *sci_r1;
  137         volatile u_char *sci_r2;
  138         volatile u_char *sci_r3;
  139         volatile u_char *sci_r4;
  140         volatile u_char *sci_r5;
  141         volatile u_char *sci_r6;
  142         volatile u_char *sci_r7;
  143 #endif
  144 
  145         /* Functions set from MD code */
  146         int             (*sc_pio_out)(struct ncr5380_softc *,
  147                                            int, int, u_char *);
  148         int             (*sc_pio_in)(struct ncr5380_softc *,
  149                                           int, int, u_char *);
  150         void            (*sc_dma_alloc)(struct ncr5380_softc *);
  151         void            (*sc_dma_free)(struct ncr5380_softc *);
  152 
  153         void            (*sc_dma_setup)(struct ncr5380_softc *);
  154         void            (*sc_dma_start)(struct ncr5380_softc *);
  155         void            (*sc_dma_poll)(struct ncr5380_softc *);
  156         void            (*sc_dma_eop)(struct ncr5380_softc *);
  157         void            (*sc_dma_stop)(struct ncr5380_softc *);
  158 
  159         void            (*sc_intr_on)(struct ncr5380_softc *);
  160         void            (*sc_intr_off)(struct ncr5380_softc *);
  161 
  162         int             sc_flags;       /* Misc. flags and capabilities */
  163 #define NCR5380_FORCE_POLLING   1       /* Do not use interrupts. */
  164 
  165         /* Set bits in this to disable disconnect per-target. */
  166         int     sc_no_disconnect;
  167 
  168         /* Set bits in this to disable parity for some target. */
  169         int             sc_parity_disable;
  170 
  171         int     sc_min_dma_len; /* Smaller than this is done with PIO */
  172 
  173         /* Begin MI shared data */
  174 
  175         int             sc_state;
  176 #define NCR_IDLE                   0    /* Ready for new work. */
  177 #define NCR_WORKING     0x01    /* Some command is in progress. */
  178 #define NCR_ABORTING    0x02    /* Bailing out */
  179 #define NCR_DOINGDMA    0x04    /* The FIFO data path is active! */
  180 #define NCR_DROP_MSGIN  0x10    /* Discard all msgs (parity err detected) */
  181 
  182         /* The request that has the bus now. */
  183         struct          sci_req *sc_current;
  184 
  185         /* Active data pointer for current SCSI command. */
  186         u_char          *sc_dataptr;
  187         int             sc_datalen;
  188 
  189         /* Begin MI private data */
  190 
  191         /* The number of operations in progress on the bus */
  192         volatile int    sc_ncmds;
  193 
  194         /* Ring buffer of pending/active requests */
  195         struct          sci_req sc_ring[SCI_OPENINGS];
  196         int             sc_rr;          /* Round-robin scan pointer */
  197 
  198         /* Active requests, by target/LUN */
  199         struct          sci_req *sc_matrix[8][8];
  200 
  201         /* Message stuff */
  202         int     sc_prevphase;
  203 
  204         u_int   sc_msgpriq;     /* Messages we want to send */
  205         u_int   sc_msgoutq;     /* Messages sent during last MESSAGE OUT */
  206         u_int   sc_msgout;      /* Message last transmitted */
  207 #define SEND_DEV_RESET          0x01
  208 #define SEND_PARITY_ERROR       0x02
  209 #define SEND_ABORT              0x04
  210 #define SEND_REJECT             0x08
  211 #define SEND_INIT_DET_ERR       0x10
  212 #define SEND_IDENTIFY           0x20
  213 #define SEND_SDTR               0x40
  214 #define SEND_WDTR               0x80
  215 #define NCR_MAX_MSG_LEN 8
  216         u_char  sc_omess[NCR_MAX_MSG_LEN];
  217         u_char  *sc_omp;                /* Outgoing message pointer */
  218         u_char  sc_imess[NCR_MAX_MSG_LEN];
  219         u_char  *sc_imp;                /* Incoming message pointer */
  220         int     sc_rev;                 /* Chip revision */
  221 #define NCR_VARIANT_NCR5380     0
  222 #define NCR_VARIANT_DP8490      1
  223 #define NCR_VARIANT_NCR53C400   2
  224 #define NCR_VARIANT_PAS16       3
  225 #define NCR_VARIANT_CXD1180     4
  226 
  227 };
  228 
  229 void    ncr5380_attach(struct ncr5380_softc *);
  230 int     ncr5380_detach(struct ncr5380_softc *, int);
  231 int     ncr5380_intr(void *);
  232 void    ncr5380_scsipi_request(struct scsipi_channel *,
  233             scsipi_adapter_req_t, void *);
  234 int     ncr5380_pio_in(struct ncr5380_softc *, int, int, u_char *);
  235 int     ncr5380_pio_out(struct ncr5380_softc *, int, int, u_char *);
  236 void    ncr5380_init(struct ncr5380_softc *);
  237 
  238 #ifdef  NCR5380_DEBUG
  239 struct ncr5380_softc *ncr5380_debug_sc;
  240 void ncr5380_trace(char *msg, long val);
  241 #define NCR_TRACE(msg, val) ncr5380_trace(msg, val)
  242 #else   /* NCR5380_DEBUG */
  243 #define NCR_TRACE(msg, val)     /* nada */
  244 #endif  /* NCR5380_DEBUG */

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