1 /* $NetBSD: ncr53c400reg.h,v 1.1 2000/03/18 13:05:21 mycroft Exp $ */
2
3 /*-
4 * Copyright (c) 1998 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by John M. Ruschmeyer.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 /*
40 * Definitions for 53C400 SCSI-controller chip.
41 *
42 * Derived from Linux NCR-5380 generic driver sources (by Drew Eckhardt).
43 *
44 * Copyright (C) 1994 Serge Vakulenko (vak@cronyx.ru)
45 *
46 * Redistribution and use in source and binary forms, with or without
47 * modification, are permitted provided that the following conditions
48 * are met:
49 * 1. Redistributions of source code must retain the above copyright
50 * notice, this list of conditions and the following disclaimer.
51 * 2. Redistributions in binary form must reproduce the above copyright
52 * notice, this list of conditions and the following disclaimer in the
53 * documentation and/or other materials provided with the distribution.
54 *
55 * THIS SOFTWARE IS PROVIDED BY THE DEVELOPERS ``AS IS'' AND
56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
58 * ARE DISCLAIMED. IN NO EVENT SHALL THE DEVELOPERS BE LIABLE
59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
65 * SUCH DAMAGE.
66 */
67
68 /*
69 * NCR5380 registers
70 */
71 #define C80_CSDR 0 /* ro - Current SCSI Data Reg. */
72 #define C80_ODR 0 /* wo - Output Data Reg. */
73 #define C80_ICR 1 /* rw - Initiator Command Reg. */
74 #define C80_MR 2 /* rw - Mode Reg. */
75 #define C80_TCR 3 /* rw - Target Command Reg. */
76 #define C80_CSBR 4 /* ro - Current SCSI Bus Status Reg. */
77 #define C80_SER 4 /* wo - Select Enable Reg. */
78 #define C80_BSR 5 /* ro - Bus and Status Reg. */
79 #define C80_SDSR 5 /* wo - Start DMA Send Reg. */
80 #define C80_IDR 6 /* ro - Input Data Reg. */
81 #define C80_SDTR 6 /* wo - Start DMA Target Receive Reg. */
82 #define C80_RPIR 7 /* ro - Reset Parity/Interrupt Reg. */
83 #define C80_SDIR 7 /* wo - Start DMA Initiator Receive Reg. */
84
85
86 #define C400_CSR 0 /* rw - Control and Status Reg. */
87 # define C400_CSR_5380_ENABLE 0x80
88 # define C400_CSR_TRANSFER_DIRECTION 0x40
89 # define C400_CSR_TRANSFER_READY_INTR 0x20
90 # define C400_CSR_5380_INTR 0x10
91 # define C400_CSR_SHARED_INTR 0x08
92 # define C400_CSR_HOST_BUF_NOT_READY 0x04 /* read only */
93 # define C400_CSR_SCSI_BUF_READY 0x02 /* read only */
94 # define C400_CSR_5380_GATED_IRQ 0x01 /* read only */
95 # define C400_CSR_BITS "\2\1irq\2sbrdy\3hbrdy\4shintr\5intr\6tintr\7tdir\10enable"
96
97 #define C400_CCR 1 /* rw - Clock Counter Reg. */
98
99 #define C400_HBR 4 /* rw - Host Buffer Reg. */
100
101 #define C400_5380_REG_OFFSET 8 /* Offset of 5380 registers. */
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