The Design and Implementation of the FreeBSD Operating System, Second Edition
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sys/dev/ic/ncr53c9xvar.h

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    1 /*      $NetBSD: ncr53c9xvar.h,v 1.43 2003/11/02 11:07:45 wiz Exp $     */
    2 
    3 /*-
    4  * Copyright (c) 1997 The NetBSD Foundation, Inc.
    5  * All rights reserved.
    6  *
    7  * This code is derived from software contributed to The NetBSD Foundation
    8  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
    9  * NASA Ames Research Center.
   10  *
   11  * Redistribution and use in source and binary forms, with or without
   12  * modification, are permitted provided that the following conditions
   13  * are met:
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions and the following disclaimer.
   16  * 2. Redistributions in binary form must reproduce the above copyright
   17  *    notice, this list of conditions and the following disclaimer in the
   18  *    documentation and/or other materials provided with the distribution.
   19  * 3. All advertising materials mentioning features or use of this software
   20  *    must display the following acknowledgement:
   21  *      This product includes software developed by the NetBSD
   22  *      Foundation, Inc. and its contributors.
   23  * 4. Neither the name of The NetBSD Foundation nor the names of its
   24  *    contributors may be used to endorse or promote products derived
   25  *    from this software without specific prior written permission.
   26  *
   27  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   29  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   30  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   37  * POSSIBILITY OF SUCH DAMAGE.
   38  */
   39 
   40 /*
   41  * Copyright (c) 1994 Peter Galbavy.  All rights reserved.
   42  *
   43  * Redistribution and use in source and binary forms, with or without
   44  * modification, are permitted provided that the following conditions
   45  * are met:
   46  * 1. Redistributions of source code must retain the above copyright
   47  *    notice, this list of conditions and the following disclaimer.
   48  * 2. Redistributions in binary form must reproduce the above copyright
   49  *    notice, this list of conditions and the following disclaimer in the
   50  *    documentation and/or other materials provided with the distribution.
   51  * 3. All advertising materials mentioning features or use of this software
   52  *    must display the following acknowledgement:
   53  *      This product includes software developed by Peter Galbavy.
   54  * 4. The name of the author may not be used to endorse or promote products
   55  *    derived from this software without specific prior written permission.
   56  *
   57  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   58  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   59  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   60  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   61  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   62  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   63  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   64  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   65  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   66  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   67  */
   68 
   69 #ifndef _DEV_IC_NCR53C9XVAR_H_
   70 #define _DEV_IC_NCR53C9XVAR_H_
   71 
   72 #include <sys/lock.h>
   73 
   74 /* Set this to 1 for normal debug, or 2 for per-target tracing. */
   75 /* #define NCR53C9X_DEBUG               1 */
   76 
   77 /* Wide or differential can have 16 targets */
   78 #define NCR_NLUN                8
   79 
   80 #define NCR_ABORT_TIMEOUT       2000    /* time to wait for abort */
   81 #define NCR_SENSE_TIMEOUT       1000    /* time to wait for sense */
   82 
   83 #define FREQTOCCF(freq) (((freq + 4) / 5))
   84 
   85 /*
   86  * NCR 53c9x variants.  Note, these values are used as indexes into
   87  * a table; don't modify them unless you know what you're doing.
   88  */
   89 #define NCR_VARIANT_ESP100              0
   90 #define NCR_VARIANT_ESP100A             1
   91 #define NCR_VARIANT_ESP200              2
   92 #define NCR_VARIANT_NCR53C94            3
   93 #define NCR_VARIANT_NCR53C96            4
   94 #define NCR_VARIANT_ESP406              5
   95 #define NCR_VARIANT_FAS408              6
   96 #define NCR_VARIANT_FAS216              7
   97 #define NCR_VARIANT_AM53C974            8
   98 #define NCR_VARIANT_FAS366              9
   99 #define NCR_VARIANT_NCR53C90_86C01      10
  100 #define NCR_VARIANT_MAX                 11
  101 
  102 /*
  103  * ECB. Holds additional information for each SCSI command Comments: We
  104  * need a separate scsi command block because we may need to overwrite it
  105  * with a request sense command.  Basicly, we refrain from fiddling with
  106  * the scsipi_xfer struct (except do the expected updating of return values).
  107  * We'll generally update: xs->{flags,resid,error,sense,status} and
  108  * occasionally xs->retries.
  109  */
  110 struct ncr53c9x_ecb {
  111         TAILQ_ENTRY(ncr53c9x_ecb) chain;
  112         struct scsipi_xfer *xs; /* SCSI xfer ctrl block from above */
  113         int flags;
  114 #define ECB_ALLOC               0x01
  115 #define ECB_READY               0x02
  116 #define ECB_SENSE               0x04
  117 #define ECB_ABORT               0x40
  118 #define ECB_RESET               0x80
  119 #define ECB_TENTATIVE_DONE      0x100
  120         int timeout;
  121 
  122         struct {
  123                 u_char  msg[3];                 /* Selection Id msg and tags */
  124                 struct scsi_generic cmd;        /* SCSI command block */
  125         } cmd;
  126         char    *daddr;         /* Saved data pointer */
  127         int      clen;          /* Size of command in cmd.cmd */
  128         int      dleft;         /* Residue */
  129         u_char   stat;          /* SCSI status byte */
  130         u_char   tag[2];        /* TAG bytes */
  131         u_char   pad[1];
  132 
  133 #if NCR53C9X_DEBUG > 1
  134         char trace[1000];
  135 #endif
  136 };
  137 #if NCR53C9X_DEBUG > 1
  138 #define ECB_TRACE(ecb, msg, a, b) do { \
  139         const char *f = "[" msg "]"; \
  140         int n = strlen((ecb)->trace); \
  141         if (n < (sizeof((ecb)->trace)-100)) \
  142                 sprintf((ecb)->trace + n, f,  a, b); \
  143 } while(0)
  144 #else
  145 #define ECB_TRACE(ecb, msg, a, b)
  146 #endif
  147 
  148 /*
  149  * Some info about each (possible) target and LUN on the SCSI bus.
  150  *
  151  * SCSI I and II devices can have up to 8 LUNs, each with up to 256
  152  * outstanding tags.  SCSI III devices have 64-bit LUN identifiers
  153  * that can be sparsely allocated.
  154  *
  155  * Since SCSI II devices can have up to 8 LUNs, we use an array
  156  * of 8 pointers to ncr53c9x_linfo structures for fast lookup.
  157  * Longer LUNs need to traverse the linked list.
  158  */
  159 
  160 struct ncr53c9x_linfo {
  161         int64_t                 lun;
  162         LIST_ENTRY(ncr53c9x_linfo) link;
  163         time_t                  last_used;
  164         unsigned char           used;   /* # slots in use */
  165         unsigned char           avail;  /* where to start scanning */
  166         unsigned char           busy;
  167         struct ncr53c9x_ecb     *untagged;
  168         struct ncr53c9x_ecb     *queued[256];
  169 };
  170 
  171 struct ncr53c9x_tinfo {
  172         int     cmds;           /* # of commands processed */
  173         int     dconns;         /* # of disconnects */
  174         int     touts;          /* # of timeouts */
  175         int     perrs;          /* # of parity errors */
  176         int     senses;         /* # of request sense commands sent */
  177         u_char  flags;
  178 #define T_NEGOTIATE     0x02    /* (Re)Negotiate synchronous options */
  179 #define T_SYNCMODE      0x08    /* SYNC mode has been negotiated */
  180 #define T_SYNCHOFF      0x10    /* SYNC mode for is permanently off */
  181 #define T_RSELECTOFF    0x20    /* RE-SELECT mode is off */
  182 #define T_TAG           0x40    /* Turn on TAG QUEUEs */
  183 #define T_WIDE          0x80    /* Negotiate wide options */
  184 #define T_WDTRSENT      0x04    /* WDTR message has been sent to */
  185         u_char  period;         /* Period suggestion */
  186         u_char  offset;         /* Offset suggestion */
  187         u_char  cfg3;           /* per target config 3  */
  188         u_char  nextag;         /* Next available tag */
  189         u_char  width;          /* width suggesion */
  190         LIST_HEAD(lun_list, ncr53c9x_linfo) luns;
  191         struct ncr53c9x_linfo *lun[NCR_NLUN]; /* For speedy lookups */
  192 };
  193 
  194 /* Look up a lun in a tinfo */
  195 #define TINFO_LUN(t, l) (                                       \
  196         (((l) < NCR_NLUN) && (((t)->lun[(l)]) != NULL))         \
  197                 ? ((t)->lun[(l)])                               \
  198                 : ncr53c9x_lunsearch((t), (int64_t)(l))         \
  199 )
  200 
  201 /* Register a linenumber (for debugging) */
  202 #define LOGLINE(p)
  203 
  204 #define NCR_SHOWECBS    0x01
  205 #define NCR_SHOWINTS    0x02
  206 #define NCR_SHOWCMDS    0x04
  207 #define NCR_SHOWMISC    0x08
  208 #define NCR_SHOWTRAC    0x10
  209 #define NCR_SHOWSTART   0x20
  210 #define NCR_SHOWPHASE   0x40
  211 #define NCR_SHOWDMA     0x80
  212 #define NCR_SHOWCCMDS   0x100
  213 #define NCR_SHOWMSGS    0x200
  214 
  215 #ifdef NCR53C9X_DEBUG
  216 extern int ncr53c9x_debug;
  217 #define NCR_ECBS(str)   \
  218         do {if (ncr53c9x_debug & NCR_SHOWECBS) printf str;} while (0)
  219 #define NCR_MISC(str)   \
  220         do {if (ncr53c9x_debug & NCR_SHOWMISC) printf str;} while (0)
  221 #define NCR_INTS(str)   \
  222         do {if (ncr53c9x_debug & NCR_SHOWINTS) printf str;} while (0)
  223 #define NCR_TRACE(str)  \
  224         do {if (ncr53c9x_debug & NCR_SHOWTRAC) printf str;} while (0)
  225 #define NCR_CMDS(str)   \
  226         do {if (ncr53c9x_debug & NCR_SHOWCMDS) printf str;} while (0)
  227 #define NCR_START(str)  \
  228         do {if (ncr53c9x_debug & NCR_SHOWSTART) printf str;}while (0)
  229 #define NCR_PHASE(str)  \
  230         do {if (ncr53c9x_debug & NCR_SHOWPHASE) printf str;}while (0)
  231 #define NCR_DMA(str)    \
  232         do {if (ncr53c9x_debug & NCR_SHOWDMA) printf str;}while (0)
  233 #define NCR_MSGS(str)   \
  234         do {if (ncr53c9x_debug & NCR_SHOWMSGS) printf str;}while (0)
  235 #else
  236 #define NCR_ECBS(str)
  237 #define NCR_MISC(str)
  238 #define NCR_INTS(str)
  239 #define NCR_TRACE(str)
  240 #define NCR_CMDS(str)
  241 #define NCR_START(str)
  242 #define NCR_PHASE(str)
  243 #define NCR_DMA(str)
  244 #define NCR_MSGS(str)
  245 #endif
  246 
  247 #define NCR_MAX_MSG_LEN 8
  248 
  249 struct ncr53c9x_softc;
  250 
  251 /*
  252  * Function switch used as glue to MD code.
  253  */
  254 struct ncr53c9x_glue {
  255         /* Mandatory entry points. */
  256         u_char  (*gl_read_reg)(struct ncr53c9x_softc *, int);
  257         void    (*gl_write_reg)(struct ncr53c9x_softc *, int, u_char);
  258         int     (*gl_dma_isintr)(struct ncr53c9x_softc *);
  259         void    (*gl_dma_reset)(struct ncr53c9x_softc *);
  260         int     (*gl_dma_intr)(struct ncr53c9x_softc *);
  261         int     (*gl_dma_setup)(struct ncr53c9x_softc *,
  262                     caddr_t *, size_t *, int, size_t *);
  263         void    (*gl_dma_go)(struct ncr53c9x_softc *);
  264         void    (*gl_dma_stop)(struct ncr53c9x_softc *);
  265         int     (*gl_dma_isactive)(struct ncr53c9x_softc *);
  266 
  267         /* Optional entry points. */
  268         void    (*gl_clear_latched_intr)(struct ncr53c9x_softc *);
  269 };
  270 
  271 struct ncr53c9x_softc {
  272         struct device sc_dev;                   /* us as a device */
  273 
  274         struct evcnt sc_intrcnt;                /* intr count */
  275         struct scsipi_adapter sc_adapter;       /* out scsipi adapter */
  276         struct scsipi_channel sc_channel;       /* our scsipi channel */
  277         struct device *sc_child;                /* attached scsibus, if any */
  278         struct callout sc_watchdog;             /* periodic timer */
  279 
  280         struct ncr53c9x_glue *sc_glue;          /* glue to MD code */
  281 
  282         int     sc_cfflags;                     /* Copy of config flags */
  283 
  284         /* register defaults */
  285         u_char  sc_cfg1;                        /* Config 1 */
  286         u_char  sc_cfg2;                        /* Config 2, not ESP100 */
  287         u_char  sc_cfg3;                        /* Config 3, ESP200,FAS */
  288         u_char  sc_cfg3_fscsi;                  /* Chip-specific FSCSI bit */
  289         u_char  sc_cfg4;                        /* Config 4, only ESP200 */
  290         u_char  sc_cfg5;                        /* Config 5, only ESP200 */
  291         u_char  sc_ccf;                         /* Clock Conversion */
  292         u_char  sc_timeout;
  293 
  294         /* register copies, see espreadregs() */
  295         u_char  sc_espintr;
  296         u_char  sc_espstat;
  297         u_char  sc_espstep;
  298         u_char  sc_espstat2;
  299         u_char  sc_espfflags;
  300 
  301         /* Lists of command blocks */
  302         TAILQ_HEAD(ecb_list, ncr53c9x_ecb)
  303                 ready_list;
  304 
  305         struct ncr53c9x_ecb *sc_nexus;          /* Current command */
  306         int     sc_ntarg;
  307         struct ncr53c9x_tinfo *sc_tinfo;
  308 
  309         /* Data about the current nexus (updated for every cmd switch) */
  310         caddr_t sc_dp;          /* Current data pointer */
  311         ssize_t sc_dleft;       /* Data left to transfer */
  312 
  313         /* Adapter state */
  314         int     sc_phase;       /* Copy of what bus phase we are in */
  315         int     sc_prevphase;   /* Copy of what bus phase we were in */
  316         u_char  sc_state;       /* State applicable to the adapter */
  317         u_char  sc_flags;       /* See below */
  318         u_char  sc_selid;
  319         u_char  sc_lastcmd;
  320 
  321         /* Message stuff */
  322         u_short sc_msgify;      /* IDENTIFY message associated with this nexus */
  323         u_short sc_msgout;      /* What message is on its way out? */
  324         u_short sc_msgpriq;     /* One or more messages to send (encoded) */
  325         u_short sc_msgoutq;     /* What messages have been sent so far? */
  326 
  327         u_char  *sc_omess;      /* MSGOUT buffer */
  328         caddr_t sc_omp;         /* Message pointer (for multibyte messages) */
  329         size_t  sc_omlen;
  330         u_char  *sc_imess;      /* MSGIN buffer */
  331         caddr_t sc_imp;         /* Message pointer (for multibyte messages) */
  332         size_t  sc_imlen;
  333 
  334         caddr_t sc_cmdp;        /* Command pointer (for DMAed commands) */
  335         size_t  sc_cmdlen;      /* Size of command in transit */
  336 
  337         /* Hardware attributes */
  338         int sc_freq;            /* SCSI bus frequency in MHz */
  339         int sc_id;              /* Our SCSI id */
  340         int sc_rev;             /* Chip revision */
  341         int sc_features;        /* Chip features */
  342         int sc_minsync;         /* Minimum sync period / 4 */
  343         int sc_maxxfer;         /* Maximum transfer size */
  344 
  345         struct simplelock sc_lock;/* driver mutex */
  346 };
  347 
  348 /* values for sc_state */
  349 #define NCR_IDLE        1       /* waiting for something to do */
  350 #define NCR_SELECTING   2       /* SCSI command is arbiting  */
  351 #define NCR_RESELECTED  3       /* Has been reselected */
  352 #define NCR_IDENTIFIED  4       /* Has gotten IFY but not TAG */
  353 #define NCR_CONNECTED   5       /* Actively using the SCSI bus */
  354 #define NCR_DISCONNECT  6       /* MSG_DISCONNECT received */
  355 #define NCR_CMDCOMPLETE 7       /* MSG_CMDCOMPLETE received */
  356 #define NCR_CLEANING    8
  357 #define NCR_SBR         9       /* Expect a SCSI RST because we commanded it */
  358 
  359 /* values for sc_flags */
  360 #define NCR_DROP_MSGI   0x01    /* Discard all msgs (parity err detected) */
  361 #define NCR_ABORTING    0x02    /* Bailing out */
  362 #define NCR_DOINGDMA    0x04    /* The FIFO data path is active! */
  363 #define NCR_SYNCHNEGO   0x08    /* Synch negotiation in progress. */
  364 #define NCR_ICCS        0x10    /* Expect status phase results */
  365 #define NCR_WAITI       0x20    /* Waiting for non-DMA data to arrive */
  366 #define NCR_ATN         0x40    /* ATN asserted */
  367 #define NCR_EXPECT_ILLCMD       0x80    /* Expect Illegal Command Interrupt */
  368 
  369 /* values for sc_features */
  370 #define NCR_F_HASCFG3   0x01    /* chip has CFG3 register */
  371 #define NCR_F_FASTSCSI  0x02    /* chip supports Fast mode */
  372 #define NCR_F_DMASELECT 0x04    /*      can do dmaselect */
  373 #define NCR_F_SELATN3   0x08    /* chip supports SELATN3 command */
  374 
  375 /* values for sc_msgout */
  376 #define SEND_DEV_RESET          0x0001
  377 #define SEND_PARITY_ERROR       0x0002
  378 #define SEND_INIT_DET_ERR       0x0004
  379 #define SEND_REJECT             0x0008
  380 #define SEND_IDENTIFY           0x0010
  381 #define SEND_ABORT              0x0020
  382 #define SEND_WDTR               0x0040
  383 #define SEND_SDTR               0x0080
  384 #define SEND_TAG                0x0100
  385 
  386 /* SCSI Status codes */
  387 #define ST_MASK                 0x3e /* bit 0,6,7 is reserved */
  388 
  389 /* phase bits */
  390 #define IOI                     0x01
  391 #define CDI                     0x02
  392 #define MSGI                    0x04
  393 
  394 /* Information transfer phases */
  395 #define DATA_OUT_PHASE          (0)
  396 #define DATA_IN_PHASE           (IOI)
  397 #define COMMAND_PHASE           (CDI)
  398 #define STATUS_PHASE            (CDI|IOI)
  399 #define MESSAGE_OUT_PHASE       (MSGI|CDI)
  400 #define MESSAGE_IN_PHASE        (MSGI|CDI|IOI)
  401 
  402 #define PHASE_MASK              (MSGI|CDI|IOI)
  403 
  404 /* Some pseudo phases for getphase()*/
  405 #define BUSFREE_PHASE           0x100   /* Re/Selection no longer valid */
  406 #define INVALID_PHASE           0x101   /* Re/Selection valid, but no REQ yet */
  407 #define PSEUDO_PHASE            0x100   /* "pseudo" bit */
  408 
  409 /*
  410  * Macros to read and write the chip's registers.
  411  */
  412 #define NCR_READ_REG(sc, reg)           \
  413         (*(sc)->sc_glue->gl_read_reg)((sc), (reg))
  414 #define NCR_WRITE_REG(sc, reg, val)     \
  415         (*(sc)->sc_glue->gl_write_reg)((sc), (reg), (val))
  416 
  417 #ifdef NCR53C9X_DEBUG
  418 #define NCRCMD(sc, cmd) do {                                            \
  419         if ((ncr53c9x_debug & NCR_SHOWCCMDS) != 0)                      \
  420                 printf("<CMD:0x%x %d>", (unsigned)cmd, __LINE__);       \
  421         sc->sc_lastcmd = cmd;                                           \
  422         NCR_WRITE_REG(sc, NCR_CMD, cmd);                                \
  423 } while (0)
  424 #else
  425 #define NCRCMD(sc, cmd)         NCR_WRITE_REG(sc, NCR_CMD, cmd)
  426 #endif
  427 
  428 /*
  429  * DMA macros for NCR53c9x
  430  */
  431 #define NCRDMA_ISINTR(sc)       (*(sc)->sc_glue->gl_dma_isintr)((sc))
  432 #define NCRDMA_RESET(sc)        (*(sc)->sc_glue->gl_dma_reset)((sc))
  433 #define NCRDMA_INTR(sc)         (*(sc)->sc_glue->gl_dma_intr)((sc))
  434 #define NCRDMA_SETUP(sc, addr, len, datain, dmasize)    \
  435      (*(sc)->sc_glue->gl_dma_setup)((sc), (addr), (len), (datain), (dmasize))
  436 #define NCRDMA_GO(sc)           (*(sc)->sc_glue->gl_dma_go)((sc))
  437 #define NCRDMA_ISACTIVE(sc)     (*(sc)->sc_glue->gl_dma_isactive)((sc))
  438 
  439 /*
  440  * Macro to convert the chip register Clock Per Byte value to
  441  * Synchronous Transfer Period.
  442  */
  443 #define ncr53c9x_cpb2stp(sc, cpb)       \
  444         ((250 * (cpb)) / (sc)->sc_freq)
  445 
  446 void    ncr53c9x_attach __P((struct ncr53c9x_softc *));
  447 int     ncr53c9x_detach __P((struct ncr53c9x_softc *, int));
  448 void    ncr53c9x_scsipi_request __P((struct scsipi_channel *chan,
  449             scsipi_adapter_req_t req, void *));
  450 void    ncr53c9x_reset __P((struct ncr53c9x_softc *));
  451 int     ncr53c9x_intr __P((void *));
  452 void    ncr53c9x_init __P((struct ncr53c9x_softc *, int));
  453 
  454 #endif /* _DEV_IC_NCR53C9XVAR_H_ */

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