The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/nec765.h

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    1 /*-
    2  * Copyright (c) 1991 The Regents of the University of California.
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 4. Neither the name of the University nor the names of its contributors
   14  *    may be used to endorse or promote products derived from this software
   15  *    without specific prior written permission.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  *
   29  *      from: @(#)nec765.h      7.1 (Berkeley) 5/9/91
   30  * $FreeBSD: stable/11/sys/dev/ic/nec765.h 331722 2018-03-29 02:50:57Z eadler $
   31  */
   32 
   33 /*
   34  * Nec 765 floppy disc controller definitions
   35  */
   36 
   37 /* Main status register */
   38 #define NE7_DAB         0x01    /* Diskette drive A is seeking, thus busy */
   39 #define NE7_DBB         0x02    /* Diskette drive B is seeking, thus busy */
   40 #define NE7_CB          0x10    /* Diskette Controller Busy */
   41 #define NE7_NDM         0x20    /* Diskette Controller in Non Dma Mode */
   42 #define NE7_DIO         0x40    /* Diskette Controller Data register I/O */
   43 #define NE7_RQM         0x80    /* Diskette Controller ReQuest for Master */
   44 
   45 /* Status register ST0 */
   46 #define NE7_ST0BITS     "\020\010invld\007abnrml\006seek_cmplt\005equ_chck\004drive_notrdy\003top_head"
   47 
   48 #define NE7_ST0_IC      0xc0    /* interrupt completion code */
   49 
   50 #define NE7_ST0_IC_RC   0xc0    /* terminated due to ready changed, n/a */
   51 #define NE7_ST0_IC_IV   0x80    /* invalid command; must reset FDC */
   52 #define NE7_ST0_IC_AT   0x40    /* abnormal termination, check error stat */
   53 #define NE7_ST0_IC_NT   0x00    /* normal termination */
   54 
   55 #define NE7_ST0_SE      0x20    /* seek end */
   56 #define NE7_ST0_EC      0x10    /* equipment check, recalibrated but no trk0 */
   57 #define NE7_ST0_NR      0x08    /* not ready (n/a) */
   58 #define NE7_ST0_HD      0x04    /* upper head selected */
   59 #define NE7_ST0_DR      0x03    /* drive code */
   60 
   61 /* Status register ST1 */
   62 #define NE7_ST1BITS     "\020\010end_of_cyl\006bad_crc\005data_overrun\003sec_not_fnd\002write_protect\001no_am"
   63 
   64 #define NE7_ST1_EN      0x80    /* end of cylinder, access past last record */
   65 #define NE7_ST1_DE      0x20    /* data error, CRC fail in ID or data */
   66 #define NE7_ST1_OR      0x10    /* DMA overrun, DMA failed to do i/o quickly */
   67 #define NE7_ST1_ND      0x04    /* no data, sector not found or CRC in ID f. */
   68 #define NE7_ST1_NW      0x02    /* not writeable, attempt to violate WP */
   69 #define NE7_ST1_MA      0x01    /* missing address mark (in ID or data field)*/
   70 
   71 /* Status register ST2 */
   72 #define NE7_ST2BITS     "\020\007ctrl_mrk\006bad_crc\005wrong_cyl\004scn_eq\003scn_not_fnd\002bad_cyl\001no_dam"
   73 
   74 #define NE7_ST2_CM      0x40    /* control mark; found deleted data */
   75 #define NE7_ST2_DD      0x20    /* data error in data field, CRC fail */
   76 #define NE7_ST2_WC      0x10    /* wrong cylinder, ID field mismatches cmd */
   77 #define NE7_ST2_SH      0x08    /* scan equal hit */
   78 #define NE7_ST2_SN      0x04    /* scan not satisfied */
   79 #define NE7_ST2_BC      0x02    /* bad cylinder, cylinder marked 0xff */
   80 #define NE7_ST2_MD      0x01    /* missing address mark in data field */
   81 
   82 /* Status register ST3 */
   83 #define NE7_ST3BITS     "\020\010fault\007write_protect\006drdy\005tk0\004two_side\003side_sel\002"
   84 
   85 #define NE7_ST3_FT      0x80    /* fault; PC: n/a */
   86 #define NE7_ST3_WP      0x40    /* write protected */
   87 #define NE7_ST3_RD      0x20    /* ready; PC: always true */
   88 #define NE7_ST3_T0      0x10    /* track 0 */
   89 #define NE7_ST3_TS      0x08    /* two-sided; PC: n/a */
   90 #define NE7_ST3_HD      0x04    /* upper head select */
   91 #define NE7_ST3_US      0x03    /* unit select */
   92 
   93 /* Data Rate Select Register DSR (enhanced controller) */
   94 #define I8207X_DSR_SR   0x80    /* software reset */
   95 #define I8207X_DSR_LP   0x40    /* low power */
   96 #define I8207X_DSR_PS   0x1c    /* precompensation select */
   97 #define I8207X_DSR_RS   0x03    /* data rate select */
   98 
   99 /* Commands */
  100 /*
  101  * the top three bits -- where appropriate -- are set as follows:
  102  *
  103  * MT  - multi-track; allow both sides to be handled in single cmd
  104  * MFM - modified frequency modulation; use MFM encoding
  105  * SK  - skip; skip sectors marked as "deleted"
  106  */
  107 
  108 #define NE7CMD_MT       0x80    /* READ, WRITE, WRITEDEL, READDEL, SCAN* */
  109 #define NE7CMD_MFM      0x40    /* same as MT, plus READTRK, READID, FORMAT */
  110 #define NE7CMD_SK       0x20    /* READ, READDEL, SCAN* */
  111 
  112 #define NE7CMD_READTRK  0x02    /*  read whole track */
  113 #define NE7CMD_SPECIFY  0x03    /*  specify drive parameters - requires unit
  114                                  *  parameters byte */
  115 #define NE7CMD_SENSED   0x04    /*  sense drive - requires unit select byte */
  116 #define NE7CMD_WRITE    0x05    /*  write - requires eight additional bytes */
  117 #define NE7CMD_READ     0x06    /*  read - requires eight additional bytes */
  118 #define NE7CMD_RECAL    0x07    /*  recalibrate drive - requires
  119                                  *  unit select byte */
  120 #define NE7CMD_SENSEI   0x08    /*  sense controller interrupt status */
  121 #define NE7CMD_WRITEDEL 0x09    /*  write deleted data */
  122 #define NE7CMD_READID   0x0a    /*  read ID field */
  123 #define NE7CMD_READDEL  0x0c    /*  read deleted data */
  124 #define NE7CMD_FORMAT   0x0d    /*  format - requires five additional bytes */
  125 #define NE7CMD_SEEK     0x0f    /*  seek drive - requires unit select byte
  126                                  *  and new cyl byte */
  127 #define NE7CMD_VERSION  0x10    /*  get version */
  128 #define NE7CMD_SCNEQU   0x11    /*  scan equal */
  129 #define NE7CMD_SCNLE    0x19    /*  scan less or equal */
  130 #define NE7CMD_SCNGE    0x1d    /*  scan greater or equal */
  131 
  132 /*
  133  * Enhanced controller commands:
  134  */
  135 #define I8207X_DUMPREG  0x0e    /*  dump internal registers */
  136 #define I8207X_CONFIG   0x13    /*  configure enhanced features */
  137 
  138 /*
  139  * "specify" definitions
  140  *
  141  * acronyms (times are relative to a FDC clock of 8 MHz):
  142  * srt - step rate; PC usually 3 ms
  143  * hut - head unload time; PC usually maximum of 240 ms
  144  * hlt - head load time; PC usually minimum of 2 ms
  145  * nd  - no DMA flag; PC usually not set (0)
  146  */
  147 
  148 #define NE7_SPEC_1(srt, hut)    (((16 - (srt)) << 4) | (((hut) / 16)))
  149 #define NE7_SPEC_2(hlt, nd)     (((hlt) & 0xFE) | ((nd) & 1))

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