1 /* $NetBSD: ninjaata32.c,v 1.5.2.1 2007/03/08 18:29:16 bouyer Exp $ */
2
3 /*
4 * Copyright (c) 2006 ITOH Yasufumi <itohy@NetBSD.org>.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS''
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26 * THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: ninjaata32.c,v 1.5.2.1 2007/03/08 18:29:16 bouyer Exp $");
31
32 #include <sys/param.h>
33 #include <sys/kernel.h>
34 #include <sys/device.h>
35
36 #include <machine/bus.h>
37 #include <machine/intr.h>
38
39 #include <uvm/uvm_extern.h>
40
41 #include <dev/ata/atavar.h>
42 #include <dev/ic/wdcreg.h>
43 #include <dev/ic/wdcvar.h>
44
45 #include <dev/ic/ninjaata32reg.h>
46 #include <dev/ic/ninjaata32var.h>
47
48 #ifdef NJATA32_DEBUG
49 #define DPRINTF(x) printf x
50 #else
51 #define DPRINTF(x)
52 #endif
53
54 static void njata32_init(struct njata32_softc *, int nosleep);
55 static void njata32_irqack(struct ata_channel *);
56 static void njata32_clearirq(struct ata_channel *, int);
57 static void njata32_setup_channel(struct ata_channel *);
58 static int njata32_dma_init(void *, int channel, int drive,
59 void *databuf, size_t datalen, int flags);
60 static void njata32_piobm_start(void *, int channel, int drive, int skip,
61 int xferlen, int flags);
62 static int njata32_dma_finish(void *, int channel, int drive, int force);
63 static void njata32_piobm_done(void *, int channel, int drive);
64
65 #if 0 /* ATA DMA is currently unused */
66 static const uint8_t njata32_timing_dma[NJATA32_MODE_MAX_DMA + 1] = {
67 NJATA32_TIMING_DMA0, NJATA32_TIMING_DMA1, NJATA32_TIMING_DMA2
68 };
69 #endif
70 static const uint8_t njata32_timing_pio[NJATA32_MODE_MAX_PIO + 1] = {
71 NJATA32_TIMING_PIO0, NJATA32_TIMING_PIO1, NJATA32_TIMING_PIO2,
72 NJATA32_TIMING_PIO3, NJATA32_TIMING_PIO4
73 };
74
75 static void
76 njata32_init(sc, nosleep)
77 struct njata32_softc *sc;
78 int nosleep; /* can't sleep (during cold boot and in interrupt) */
79 {
80
81 /* disable interrupts */
82 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
83 NJATA32_REG_IRQ_SELECT, 0);
84
85 /* bus reset */
86 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_AS,
87 NJATA32_AS_WAIT0 | NJATA32_AS_BUS_RESET);
88 if (nosleep)
89 delay(50000);
90 else
91 tsleep(sc, PRIBIO, "njaini", mstohz(50));
92 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_AS,
93 NJATA32_AS_WAIT0);
94
95 /* initial transfer speed */
96 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
97 NJATA32_REG_TIMING, NJATA32_TIMING_PIO0 + sc->sc_atawait);
98
99 /* setup busmaster mode */
100 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_IOBM,
101 NJATA32_IOBM_DEFAULT);
102
103 /* enable interrupts */
104 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
105 NJATA32_REG_IRQ_SELECT, NJATA32_IRQ_XFER | NJATA32_IRQ_DEV);
106 }
107
108 void
109 njata32_attach(sc)
110 struct njata32_softc *sc;
111 {
112 bus_addr_t dmaaddr;
113 int i, devno, error;
114 struct wdc_regs *wdr;
115
116 /*
117 * allocate DMA resource
118 */
119 if ((error = bus_dmamem_alloc(sc->sc_dmat,
120 sizeof(struct njata32_dma_page), PAGE_SIZE, 0,
121 &sc->sc_sgt_seg, 1, &sc->sc_sgt_nsegs, BUS_DMA_NOWAIT)) != 0) {
122 printf("%s: unable to allocate sgt page, error = %d\n",
123 NJATA32NAME(sc), error);
124 return;
125 }
126 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_sgt_seg,
127 sc->sc_sgt_nsegs, sizeof(struct njata32_dma_page),
128 (caddr_t *)&sc->sc_sgtpg,
129 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
130 printf("%s: unable to map sgt page, error = %d\n",
131 NJATA32NAME(sc), error);
132 goto fail1;
133 }
134 if ((error = bus_dmamap_create(sc->sc_dmat,
135 sizeof(struct njata32_dma_page), 1,
136 sizeof(struct njata32_dma_page), 0, BUS_DMA_NOWAIT,
137 &sc->sc_dmamap_sgt)) != 0) {
138 printf("%s: unable to create sgt DMA map, error = %d\n",
139 NJATA32NAME(sc), error);
140 goto fail2;
141 }
142 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_sgt,
143 sc->sc_sgtpg, sizeof(struct njata32_dma_page),
144 NULL, BUS_DMA_NOWAIT)) != 0) {
145 printf("%s: unable to load sgt DMA map, error = %d\n",
146 NJATA32NAME(sc), error);
147 goto fail3;
148 }
149
150 dmaaddr = sc->sc_dmamap_sgt->dm_segs[0].ds_addr;
151
152 for (devno = 0; devno < NJATA32_NUM_DEV; devno++) {
153 sc->sc_dev[devno].d_sgt = sc->sc_sgtpg->dp_sg[devno];
154 sc->sc_dev[devno].d_sgt_dma = dmaaddr +
155 offsetof(struct njata32_dma_page, dp_sg[devno]);
156
157 error = bus_dmamap_create(sc->sc_dmat,
158 NJATA32_MAX_XFER, /* max total map size */
159 NJATA32_NUM_SG, /* max number of segments */
160 NJATA32_SGT_MAXSEGLEN, /* max size of a segment */
161 0, /* boundary */
162 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
163 &sc->sc_dev[devno].d_dmamap_xfer);
164 if (error) {
165 printf("%s: failed to create DMA map (error = %d)\n",
166 NJATA32NAME(sc), error);
167 goto fail4;
168 }
169 }
170
171 /* device properties */
172 sc->sc_wdcdev.sc_atac.atac_cap =
173 ATAC_CAP_DATA16 | ATAC_CAP_DATA32 | ATAC_CAP_PIOBM;
174 sc->sc_wdcdev.irqack = njata32_irqack;
175 sc->sc_wdcdev.sc_atac.atac_channels = sc->sc_wdc_chanarray;
176 sc->sc_wdcdev.sc_atac.atac_nchannels = NJATA32_NCHAN; /* 1 */
177 sc->sc_wdcdev.sc_atac.atac_pio_cap = NJATA32_MODE_MAX_PIO;
178 #if 0 /* ATA DMA is currently unused */
179 sc->sc_wdcdev.sc_atac.atac_dma_cap = NJATA32_MODE_MAX_DMA;
180 #endif
181 sc->sc_wdcdev.sc_atac.atac_set_modes = njata32_setup_channel;
182
183 /* DMA control functions */
184 sc->sc_wdcdev.dma_arg = sc;
185 sc->sc_wdcdev.dma_init = njata32_dma_init;
186 sc->sc_wdcdev.piobm_start = njata32_piobm_start;
187 sc->sc_wdcdev.dma_finish = njata32_dma_finish;
188 sc->sc_wdcdev.piobm_done = njata32_piobm_done;
189
190 sc->sc_wdcdev.cap |= WDC_CAPABILITY_NO_EXTRA_RESETS;
191
192 sc->sc_wdcdev.regs = wdr = &sc->sc_wdc_regs;
193
194 /* only one channel */
195 sc->sc_wdc_chanarray[0] = &sc->sc_ch[0].ch_ata_channel;
196 sc->sc_ch[0].ch_ata_channel.ch_channel = 0;
197 sc->sc_ch[0].ch_ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
198 sc->sc_ch[0].ch_ata_channel.ch_queue = &sc->sc_wdc_chqueue;
199 sc->sc_ch[0].ch_ata_channel.ch_ndrive = 2; /* max number of drives */
200
201 /* map ATA registers */
202 for (i = 0; i < WDC_NREG; i++) {
203 if (bus_space_subregion(NJATA32_REGT(sc), NJATA32_REGH(sc),
204 NJATA32_OFFSET_WDCREGS + i,
205 i == wd_data ? 4 : 1, &wdr->cmd_iohs[i]) != 0) {
206 aprint_error("%s: couldn't subregion cmd regs\n",
207 NJATA32NAME(sc));
208 goto fail4;
209 }
210 }
211 wdc_init_shadow_regs(&sc->sc_ch[0].ch_ata_channel);
212 wdr->data32iot = NJATA32_REGT(sc);
213 wdr->data32ioh = wdr->cmd_iohs[wd_data];
214
215 /* map ATA ctl reg */
216 wdr->ctl_iot = NJATA32_REGT(sc);
217 if (bus_space_subregion(NJATA32_REGT(sc), NJATA32_REGH(sc),
218 NJATA32_REG_WD_ALTSTATUS, 1, &wdr->ctl_ioh) != 0) {
219 aprint_error("%s: couldn't subregion ctl regs\n",
220 NJATA32NAME(sc));
221 goto fail4;
222 }
223
224 sc->sc_flags |= NJATA32_CMDPG_MAPPED;
225
226 /* use flags value as busmaster wait */
227 if ((sc->sc_atawait =
228 (uint8_t)device_cfdata(&sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags))
229 aprint_normal("%s: ATA wait = %#x\n",
230 NJATA32NAME(sc), sc->sc_atawait);
231
232 njata32_init(sc, cold);
233
234 wdcattach(&sc->sc_ch[0].ch_ata_channel);
235
236 return;
237
238 /*
239 * cleanup
240 */
241 fail4: while (--devno >= 0) {
242 bus_dmamap_destroy(sc->sc_dmat,
243 sc->sc_dev[devno].d_dmamap_xfer);
244 }
245 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_sgt);
246 fail3: bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_sgt);
247 fail2: bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_sgtpg,
248 sizeof(struct njata32_dma_page));
249 fail1: bus_dmamem_free(sc->sc_dmat, &sc->sc_sgt_seg, sc->sc_sgt_nsegs);
250 }
251
252 int
253 njata32_detach(sc, flags)
254 struct njata32_softc *sc;
255 int flags;
256 {
257 int rv, devno;
258
259 if (sc->sc_flags & NJATA32_CMDPG_MAPPED) {
260 if ((rv = wdcdetach(&sc->sc_wdcdev.sc_atac.atac_dev, flags)))
261 return rv;
262
263 /* free DMA resource */
264 for (devno = 0; devno < NJATA32_NUM_DEV; devno++) {
265 bus_dmamap_destroy(sc->sc_dmat,
266 sc->sc_dev[devno].d_dmamap_xfer);
267 }
268 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_sgt);
269 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_sgt);
270 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_sgtpg,
271 sizeof(struct njata32_dma_page));
272 bus_dmamem_free(sc->sc_dmat, &sc->sc_sgt_seg, sc->sc_sgt_nsegs);
273 }
274
275 return 0;
276 }
277
278 static void
279 njata32_irqack(chp)
280 struct ata_channel *chp;
281 {
282 struct njata32_softc *sc = (void *)chp->ch_atac;
283
284 /* disable busmaster */
285 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
286 NJATA32_REG_BM, NJATA32_BM_WAIT0);
287 }
288
289 static void
290 njata32_clearirq(chp, irq)
291 struct ata_channel *chp;
292 int irq;
293 {
294 struct njata32_softc *sc = (void *)chp->ch_atac;
295
296 printf("%s: unhandled intr: irq %#x, bm %#x, ",
297 NJATA32NAME(sc), irq,
298 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
299 NJATA32_REG_BM));
300
301 /* disable busmaster */
302 njata32_irqack(chp);
303
304 /* clear device interrupt */
305 printf("err %#x, seccnt %#x, cyl %#x, sdh %#x, ",
306 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
307 NJATA32_REG_WD_ERROR),
308 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
309 NJATA32_REG_WD_SECCNT),
310 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
311 NJATA32_REG_WD_CYL_LO) |
312 (bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
313 NJATA32_REG_WD_CYL_HI) << 8),
314 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
315 NJATA32_REG_WD_SDH));
316 printf("status %#x\n",
317 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
318 NJATA32_REG_WD_STATUS));
319 }
320
321 static void
322 njata32_setup_channel(chp)
323 struct ata_channel *chp;
324 {
325 struct njata32_softc *sc = (void *)chp->ch_atac;
326 struct ata_drive_datas *drvp;
327 int drive;
328 uint8_t mode;
329
330 KASSERT(chp->ch_ndrive != 0);
331
332 sc->sc_timing_pio = 0;
333 #if 0 /* ATA DMA is currently unused */
334 sc->sc_timing_dma = 0;
335 #endif
336
337 for (drive = 0; drive < chp->ch_ndrive; drive++) {
338 drvp = &chp->ch_drive[drive];
339 if ((drvp->drive_flags & DRIVE) == 0)
340 continue; /* no drive */
341
342 #if 0 /* ATA DMA is currently unused */
343 if ((drvp->drive_flags & DRIVE_DMA) != 0) {
344 /*
345 * Multiword DMA
346 */
347 if ((mode = drvp->DMA_mode) > NJATA32_MODE_MAX_DMA)
348 mode = NJATA32_MODE_MAX_DMA;
349 if (sc->sc_timing_dma < njata32_timing_dma[mode])
350 sc->sc_timing_dma = njata32_timing_dma[mode];
351 }
352 #endif
353 /*
354 * PIO
355 */
356 if ((mode = drvp->PIO_mode) > NJATA32_MODE_MAX_PIO)
357 mode = NJATA32_MODE_MAX_PIO;
358 if (sc->sc_timing_pio < njata32_timing_pio[mode])
359 sc->sc_timing_pio = njata32_timing_pio[mode];
360 }
361
362 sc->sc_timing_pio += sc->sc_atawait;
363
364 /* set timing for PIO */
365 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
366 NJATA32_REG_TIMING, sc->sc_timing_pio);
367 }
368
369 /*
370 * map DMA buffer
371 */
372 int
373 njata32_dma_init(void *v, int channel, int drive, void *databuf,
374 size_t datalen, int flags)
375 {
376 struct njata32_softc *sc = v;
377 int error;
378 struct njata32_device *dev = &sc->sc_dev[drive];
379
380 KASSERT(channel == 0);
381 KASSERT((dev->d_flags & NJATA32_DEV_DMA_MAPPED) == 0);
382 KASSERT((dev->d_flags & NJATA32_DEV_DMA_STARTED) == 0);
383
384 KASSERT(flags & (WDC_DMA_PIOBM_ATA | WDC_DMA_PIOBM_ATAPI));
385
386 /* use PIO for short transfer */
387 if (datalen < 64 /* needs tune */) {
388 DPRINTF(("%s: njata32_dma_init: short transfer (%u)\n",
389 NJATA32NAME(sc), (unsigned)datalen));
390 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
391 NJATA32_REG_TIMING, sc->sc_timing_pio);
392 return EINVAL;
393 }
394
395 /* use PIO for unaligned transfer (word alignment seems OK) */
396 if (((uintptr_t)databuf & 1) || (datalen & 1)) {
397 DPRINTF(("%s: njata32_dma_init: unaligned: buf %p, len %u\n",
398 NJATA32NAME(sc), databuf, (unsigned)datalen));
399 return EINVAL;
400 }
401
402 DPRINTF(("%s: njata32_dma_init: %s: databuf %p, datalen %u\n",
403 NJATA32NAME(sc), (flags & WDC_DMA_READ) ? "read" : "write",
404 databuf, (unsigned)datalen));
405
406 error = bus_dmamap_load(sc->sc_dmat, dev->d_dmamap_xfer,
407 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING |
408 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE));
409 if (error) {
410 printf("%s: load xfer failed, error %d\n",
411 NJATA32NAME(sc), error);
412 return error;
413 }
414
415 bus_dmamap_sync(sc->sc_dmat, dev->d_dmamap_xfer, 0,
416 dev->d_dmamap_xfer->dm_mapsize,
417 (flags & WDC_DMA_READ) ?
418 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
419
420 dev->d_flags =
421 ((flags & WDC_DMA_READ) ? NJATA32_DEV_DMA_READ : 0) |
422 ((flags & WDC_DMA_PIOBM_ATAPI) ? NJATA32_DEV_DMA_ATAPI : 0) |
423 NJATA32_DEV_DMA_MAPPED;
424
425 return 0;
426 }
427
428 /*
429 * start DMA
430 *
431 * top: databuf + skip
432 * size: xferlen
433 */
434 void
435 njata32_piobm_start(void *v, int channel, int drive,
436 int skip, int xferlen, int flags)
437 {
438 struct njata32_softc *sc = v;
439 struct njata32_device *dev = &sc->sc_dev[drive];
440 int i, nsegs, seglen;
441 uint8_t bmreg;
442
443 DPRINTF(("%s: njata32_piobm_start: ch%d, dv%d, skip %d, xferlen %d\n",
444 NJATA32NAME(sc), channel, drive, skip, xferlen));
445
446 KASSERT(channel == 0);
447 KASSERT(dev->d_flags & NJATA32_DEV_DMA_MAPPED);
448 KASSERT((dev->d_flags & NJATA32_DEV_DMA_STARTED) == 0);
449
450 /*
451 * create scatter/gather table
452 * XXX this code may be slow
453 */
454 for (i = nsegs = 0;
455 i < dev->d_dmamap_xfer->dm_nsegs && xferlen > 0; i++) {
456 if (dev->d_dmamap_xfer->dm_segs[i].ds_len <= skip) {
457 skip -= dev->d_dmamap_xfer->dm_segs[i].ds_len;
458 continue;
459 }
460
461 seglen = dev->d_dmamap_xfer->dm_segs[i].ds_len - skip;
462 if (seglen > xferlen)
463 seglen = xferlen;
464
465 dev->d_sgt[nsegs].sg_addr =
466 htole32(dev->d_dmamap_xfer->dm_segs[i].ds_addr + skip);
467 dev->d_sgt[nsegs].sg_len = htole32(seglen);
468
469 xferlen -= seglen;
470 nsegs++;
471 skip = 0;
472 }
473 sc->sc_piobm_nsegs = nsegs;
474 /* end mark */
475 dev->d_sgt[nsegs - 1].sg_len |= htole32(NJATA32_SGT_ENDMARK);
476
477 #ifdef DIAGNOSTIC
478 if (xferlen)
479 panic("%s: njata32_piobm_start: xferlen residue %d\n",
480 NJATA32NAME(sc), xferlen);
481 #endif
482
483 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_sgt,
484 (char *)dev->d_sgt - (char *)sc->sc_sgtpg,
485 sizeof(struct njata32_sgtable) * nsegs,
486 BUS_DMASYNC_PREWRITE);
487
488 /* set timing for PIO */
489 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
490 NJATA32_REG_TIMING, sc->sc_timing_pio);
491
492 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_IOBM,
493 NJATA32_IOBM_DEFAULT);
494 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_AS,
495 NJATA32_AS_WAIT0);
496
497 /*
498 * interrupt configuration
499 */
500 if ((dev->d_flags & (NJATA32_DEV_DMA_READ | NJATA32_DEV_DMA_ATAPI)) ==
501 NJATA32_DEV_DMA_READ) {
502 /*
503 * ATA piobm read is executed while device interrupt is active,
504 * so disable device interrupt here
505 */
506 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
507 NJATA32_REG_IRQ_SELECT, NJATA32_IRQ_XFER);
508 }
509
510 /* enable scatter/gather busmaster transfer */
511 bmreg = NJATA32_BM_EN | NJATA32_BM_SG | NJATA32_BM_WAIT0 |
512 ((dev->d_flags & NJATA32_DEV_DMA_READ) ? NJATA32_BM_RD : 0);
513 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_BM,
514 bmreg);
515
516 /* load scatter/gather table */
517 bus_space_write_4(NJATA32_REGT(sc), NJATA32_REGH(sc),
518 NJATA32_REG_DMAADDR, dev->d_sgt_dma);
519 bus_space_write_4(NJATA32_REGT(sc), NJATA32_REGH(sc),
520 NJATA32_REG_DMALENGTH, sizeof(struct njata32_sgtable) * nsegs);
521
522 /* start transfer */
523 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_BM,
524 (bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
525 NJATA32_REG_BM)
526 & ~(NJATA32_BM_RD|NJATA32_BM_SG|NJATA32_BM_WAIT_MASK)) |
527 bmreg | NJATA32_BM_GO);
528
529 sc->sc_devflags = dev->d_flags;
530 if (flags & WDC_PIOBM_XFER_IRQ)
531 sc->sc_devflags |= NJATA32_DEV_XFER_INTR;
532 #ifdef DIAGNOSTIC
533 dev->d_flags |= NJATA32_DEV_DMA_STARTED;
534 #endif
535 }
536
537 /*
538 * end of DMA
539 */
540 int
541 njata32_dma_finish(void *v, int channel, int drive,
542 int force)
543 {
544 struct njata32_softc *sc = v;
545 struct njata32_device *dev = &sc->sc_dev[drive];
546 int bm;
547 int error = 0;
548
549 DPRINTF(("%s: njata32_dma_finish: bm = %#x\n", NJATA32NAME(sc),
550 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
551 NJATA32_REG_BM)));
552
553 KASSERT(channel == 0);
554 KASSERT(dev->d_flags & NJATA32_DEV_DMA_MAPPED);
555 KASSERT(dev->d_flags & NJATA32_DEV_DMA_STARTED);
556
557 bm = bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
558 NJATA32_REG_BM);
559
560 #ifdef NJATA32_DEBUG
561 printf("%s: irq %#x, bm %#x, 18 %#x, 1c %#x\n", NJATA32NAME(sc),
562 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
563 NJATA32_REG_IRQ_STAT),
564 bm,
565 bus_space_read_4(NJATA32_REGT(sc), NJATA32_REGH(sc), 0x18),
566 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 0x1c));
567 #endif
568
569 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_sgt,
570 (char *)dev->d_sgt - (char *)sc->sc_sgtpg,
571 sizeof(struct njata32_sgtable) * sc->sc_piobm_nsegs,
572 BUS_DMASYNC_POSTWRITE);
573
574 /* check if DMA is active */
575 if (bm & NJATA32_BM_GO) {
576 error = WDC_DMAST_NOIRQ;
577
578 switch (force) {
579 case WDC_DMAEND_END:
580 return error;
581
582 case WDC_DMAEND_ABRT:
583 printf("%s: aborting DMA\n", NJATA32NAME(sc));
584 break;
585 }
586 }
587
588 /*
589 * ???
590 * For unknown reason, PIOBM transfer sometimes fails in the middle,
591 * in which case the bit #7 of BM register becomes 0.
592 * Increasing the wait value seems to improve the situation.
593 *
594 * XXX
595 * PIO transfer may also fail, but it seems it can't be detected.
596 */
597 if ((bm & NJATA32_BM_DONE) == 0) {
598 error |= WDC_DMAST_ERR;
599 printf("%s: busmaster error", NJATA32NAME(sc));
600 if (sc->sc_atawait < 0x11) {
601 if ((sc->sc_atawait & 0xf) == 0)
602 sc->sc_atawait++;
603 else
604 sc->sc_atawait += 0x10;
605 printf(", new ATA wait = %#x", sc->sc_atawait);
606 njata32_setup_channel(&sc->sc_ch[0].ch_ata_channel);
607 }
608 printf("\n");
609 }
610
611 /* stop command */
612 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_AS,
613 NJATA32_AS_WAIT0);
614 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_BM,
615 NJATA32_BM_WAIT0);
616
617 /* set timing for PIO */
618 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
619 NJATA32_REG_TIMING, sc->sc_timing_pio);
620
621 /*
622 * reenable device interrupt in case it was disabled for
623 * this transfer
624 */
625 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
626 NJATA32_REG_IRQ_SELECT, NJATA32_IRQ_XFER | NJATA32_IRQ_DEV);
627
628 #if 1 /* should be? */
629 if ((sc->sc_devflags & NJATA32_DEV_GOT_XFER_INTR) == 0)
630 error |= WDC_DMAST_ERR;
631 #endif
632 sc->sc_devflags = 0;
633
634 #ifdef DIAGNOSTIC
635 dev->d_flags &= ~NJATA32_DEV_DMA_STARTED;
636 #endif
637
638 return error;
639 }
640
641 /*
642 * unmap DMA buffer
643 */
644 void
645 njata32_piobm_done(void *v, int channel, int drive)
646 {
647 struct njata32_softc *sc = v;
648 struct njata32_device *dev = &sc->sc_dev[drive];
649
650 DPRINTF(("%s: njata32_piobm_done: ch%d dv%d\n",
651 NJATA32NAME(sc), channel, drive));
652
653 KASSERT(channel == 0);
654 KASSERT(dev->d_flags & NJATA32_DEV_DMA_MAPPED);
655 KASSERT((dev->d_flags & NJATA32_DEV_DMA_STARTED) == 0);
656
657 /* unload dma map */
658 bus_dmamap_sync(sc->sc_dmat, dev->d_dmamap_xfer,
659 0, dev->d_dmamap_xfer->dm_mapsize,
660 (dev->d_flags & NJATA32_DEV_DMA_READ) ?
661 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
662
663 bus_dmamap_unload(sc->sc_dmat, dev->d_dmamap_xfer);
664 dev->d_flags &= ~NJATA32_DEV_DMA_MAPPED;
665 }
666
667 int
668 njata32_intr(arg)
669 void *arg;
670 {
671 struct njata32_softc *sc = arg;
672 struct ata_channel *chp;
673 int irq;
674
675 irq = bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
676 NJATA32_REG_IRQ_STAT);
677 if ((irq & (NJATA32_IRQ_XFER | NJATA32_IRQ_DEV)) == 0)
678 return 0; /* not mine */
679
680 DPRINTF(("%s: njata32_intr: irq = %#x, altstatus = %#x\n",
681 NJATA32NAME(sc), irq,
682 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
683 NJATA32_REG_WD_ALTSTATUS)));
684
685 chp = &sc->sc_ch[0].ch_ata_channel;
686
687 if (irq & NJATA32_IRQ_XFER)
688 sc->sc_devflags |= NJATA32_DEV_GOT_XFER_INTR;
689
690 if ((irq & (NJATA32_IRQ_XFER | NJATA32_IRQ_DEV)) == NJATA32_IRQ_XFER &&
691 (sc->sc_devflags & NJATA32_DEV_XFER_INTR) == 0) {
692 /*
693 * transfer done, wait for device interrupt
694 */
695 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
696 NJATA32_REG_BM, NJATA32_BM_WAIT0);
697 return 1;
698 }
699
700 /*
701 * If both transfer done interrupt and device interrupt are
702 * active for ATAPI transfer, call wdcintr() twice.
703 */
704 if ((sc->sc_devflags & NJATA32_DEV_DMA_ATAPI) &&
705 (irq & (NJATA32_IRQ_XFER | NJATA32_IRQ_DEV)) ==
706 (NJATA32_IRQ_XFER | NJATA32_IRQ_DEV) &&
707 (sc->sc_devflags & NJATA32_DEV_XFER_INTR)) {
708 if (wdcintr(chp) == 0) {
709 njata32_clearirq(&sc->sc_ch[0].ch_ata_channel, irq);
710 }
711 }
712
713 if (wdcintr(chp) == 0) {
714 njata32_clearirq(&sc->sc_ch[0].ch_ata_channel, irq);
715 }
716
717 return 1;
718 }
Cache object: c5086d11084c901d04d5c930ccbc3bbc
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