1 /* $NetBSD: ninjascsi32.c,v 1.8.2.1 2007/11/25 08:48:28 xtraeme Exp $ */
2
3 /*-
4 * Copyright (c) 2004, 2006, 2007 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by ITOH Yasufumi.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 #include <sys/cdefs.h>
40 __KERNEL_RCSID(0, "$NetBSD: ninjascsi32.c,v 1.8.2.1 2007/11/25 08:48:28 xtraeme Exp $");
41
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/callout.h>
45 #include <sys/device.h>
46 #include <sys/kernel.h>
47 #include <sys/buf.h>
48 #include <sys/scsiio.h>
49
50 #include <machine/bus.h>
51 #include <machine/intr.h>
52
53 #include <uvm/uvm_extern.h>
54
55 #include <dev/scsipi/scsi_all.h>
56 #include <dev/scsipi/scsipi_all.h>
57 #include <dev/scsipi/scsiconf.h>
58 #include <dev/scsipi/scsi_message.h>
59
60 /*
61 * DualEdge transfer support
62 */
63 /* #define NJSC32_DUALEDGE */ /* XXX untested */
64
65 /*
66 * Auto param loading does not work properly (it partially works (works on
67 * start, doesn't on restart) on rev 0x54, it doesn't work at all on rev 0x51),
68 * and it doesn't improve the performance so much,
69 * forget about it.
70 */
71 #undef NJSC32_AUTOPARAM
72
73 #include <dev/ic/ninjascsi32reg.h>
74 #include <dev/ic/ninjascsi32var.h>
75
76 /* #define NJSC32_DEBUG */
77 /* #define NJSC32_TRACE */
78
79 #ifdef NJSC32_DEBUG
80 #define DPRINTF(x) printf x
81 #define DPRINTC(cmd, x) PRINTC(cmd, x)
82 #else
83 #define DPRINTF(x)
84 #define DPRINTC(cmd, x)
85 #endif
86 #ifdef NJSC32_TRACE
87 #define TPRINTF(x) printf x
88 #define TPRINTC(cmd, x) PRINTC(cmd, x)
89 #else
90 #define TPRINTF(x)
91 #define TPRINTC(cmd, x)
92 #endif
93
94 #define PRINTC(cmd, x) do { \
95 scsi_print_addr((cmd)->c_xs->xs_periph); \
96 printf x; \
97 } while (/* CONSTCOND */ 0)
98
99 static void njsc32_scsipi_request(struct scsipi_channel *,
100 scsipi_adapter_req_t, void *);
101 static void njsc32_scsipi_minphys(struct buf *);
102 static int njsc32_scsipi_ioctl(struct scsipi_channel *, u_long, caddr_t,
103 int, struct proc *);
104
105 static void njsc32_init(struct njsc32_softc *, int nosleep);
106 static int njsc32_init_cmds(struct njsc32_softc *);
107 static void njsc32_target_async(struct njsc32_softc *,
108 struct njsc32_target *);
109 static void njsc32_init_targets(struct njsc32_softc *);
110 static void njsc32_add_msgout(struct njsc32_softc *, int);
111 static u_int32_t njsc32_get_auto_msgout(struct njsc32_softc *);
112 #ifdef NJSC32_DUALEDGE
113 static void njsc32_msgout_wdtr(struct njsc32_softc *, int);
114 #endif
115 static void njsc32_msgout_sdtr(struct njsc32_softc *, int period,
116 int offset);
117 static void njsc32_negotiate_xfer(struct njsc32_softc *,
118 struct njsc32_target *);
119 static void njsc32_arbitration_failed(struct njsc32_softc *);
120 static void njsc32_start(struct njsc32_softc *);
121 static void njsc32_run_xfer(struct njsc32_softc *, struct scsipi_xfer *);
122 static void njsc32_end_cmd(struct njsc32_softc *, struct njsc32_cmd *,
123 scsipi_xfer_result_t);
124 static void njsc32_wait_reset_release(void *);
125 static void njsc32_reset_bus(struct njsc32_softc *);
126 static void njsc32_clear_cmds(struct njsc32_softc *,
127 scsipi_xfer_result_t);
128 static void njsc32_set_ptr(struct njsc32_softc *, struct njsc32_cmd *,
129 u_int32_t);
130 static void njsc32_assert_ack(struct njsc32_softc *);
131 static void njsc32_negate_ack(struct njsc32_softc *);
132 static void njsc32_wait_req_negate(struct njsc32_softc *);
133 static void njsc32_reconnect(struct njsc32_softc *, struct njsc32_cmd *);
134 enum njsc32_reselstat {
135 NJSC32_RESEL_ERROR, /* to be rejected */
136 NJSC32_RESEL_COMPLETE, /* reselection is just complete */
137 NJSC32_RESEL_THROUGH /* this message is OK (no reply) */
138 };
139 static enum njsc32_reselstat njsc32_resel_identify(struct njsc32_softc *,
140 int lun, struct njsc32_cmd **);
141 static enum njsc32_reselstat njsc32_resel_tag(struct njsc32_softc *,
142 int tag, struct njsc32_cmd **);
143 static void njsc32_cmd_reload(struct njsc32_softc *, struct njsc32_cmd *,
144 int);
145 static void njsc32_update_xfer_mode(struct njsc32_softc *,
146 struct njsc32_target *);
147 static void njsc32_msgin(struct njsc32_softc *);
148 static void njsc32_msgout(struct njsc32_softc *);
149 static void njsc32_cmdtimeout(void *);
150 static void njsc32_reseltimeout(void *);
151
152 static inline unsigned
153 njsc32_read_1(struct njsc32_softc *sc, int no)
154 {
155
156 return bus_space_read_1(sc->sc_regt, sc->sc_regh, no);
157 }
158
159 static inline unsigned
160 njsc32_read_2(struct njsc32_softc *sc, int no)
161 {
162
163 return bus_space_read_2(sc->sc_regt, sc->sc_regh, no);
164 }
165
166 static inline u_int32_t
167 njsc32_read_4(struct njsc32_softc *sc, int no)
168 {
169
170 return bus_space_read_4(sc->sc_regt, sc->sc_regh, no);
171 }
172
173 static inline void
174 njsc32_write_1(struct njsc32_softc *sc, int no, int val)
175 {
176
177 bus_space_write_1(sc->sc_regt, sc->sc_regh, no, val);
178 }
179
180 static inline void
181 njsc32_write_2(struct njsc32_softc *sc, int no, int val)
182 {
183
184 bus_space_write_2(sc->sc_regt, sc->sc_regh, no, val);
185 }
186
187 static inline void
188 njsc32_write_4(struct njsc32_softc *sc, int no, u_int32_t val)
189 {
190
191 bus_space_write_4(sc->sc_regt, sc->sc_regh, no, val);
192 }
193
194 static inline unsigned
195 njsc32_ireg_read_1(struct njsc32_softc *sc, int no)
196 {
197
198 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no);
199 return bus_space_read_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW);
200 }
201
202 static inline unsigned
203 njsc32_ireg_read_2(struct njsc32_softc *sc, int no)
204 {
205
206 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no);
207 return bus_space_read_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW);
208 }
209
210 static inline u_int32_t
211 njsc32_ireg_read_4(struct njsc32_softc *sc, int no)
212 {
213 u_int32_t val;
214
215 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no);
216 val = (u_int16_t)bus_space_read_2(sc->sc_regt, sc->sc_regh,
217 NJSC32_REG_DATA_LOW);
218 return val | (bus_space_read_2(sc->sc_regt, sc->sc_regh,
219 NJSC32_REG_DATA_HIGH) << 16);
220 }
221
222 static inline void
223 njsc32_ireg_write_1(struct njsc32_softc *sc, int no, int val)
224 {
225
226 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no);
227 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val);
228 }
229
230 static inline void
231 njsc32_ireg_write_2(struct njsc32_softc *sc, int no, int val)
232 {
233
234 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no);
235 bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val);
236 }
237
238 static inline void
239 njsc32_ireg_write_4(struct njsc32_softc *sc, int no, u_int32_t val)
240 {
241
242 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no);
243 bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val);
244 bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_HIGH,
245 val >> 16);
246 }
247
248 #define NS(ns) ((ns) / 4) /* nanosecond (>= 50) -> sync value */
249 #ifdef __STDC__
250 # define ACKW(n) NJSC32_ACK_WIDTH_ ## n ## CLK
251 # define SMPL(n) (NJSC32_SREQ_SAMPLING_ ## n ## CLK | \
252 NJSC32_SREQ_SAMPLING_ENABLE)
253 #else
254 # define ACKW(n) NJSC32_ACK_WIDTH_/**/n/**/CLK
255 # define SMPL(n) (NJSC32_SREQ_SAMPLING_/**/n/**/CLK | \
256 NJSC32_SREQ_SAMPLING_ENABLE)
257 #endif
258
259 #define NJSC32_NSYNCT_MAXSYNC 1
260 #define NJSC32_NSYNCT 16
261
262 /* 40MHz (25ns) */
263 static const struct njsc32_sync_param njsc32_synct_40M[NJSC32_NSYNCT] = {
264 { 0, 0, 0 }, /* dummy for async */
265 { NS( 50), ACKW(1), 0 }, /* 20.0 : 50ns, 25ns */
266 { NS( 75), ACKW(1), SMPL(1) }, /* 13.3 : 75ns, 25ns */
267 { NS(100), ACKW(2), SMPL(1) }, /* 10.0 : 100ns, 50ns */
268 { NS(125), ACKW(2), SMPL(2) }, /* 8.0 : 125ns, 50ns */
269 { NS(150), ACKW(3), SMPL(2) }, /* 6.7 : 150ns, 75ns */
270 { NS(175), ACKW(3), SMPL(2) }, /* 5.7 : 175ns, 75ns */
271 { NS(200), ACKW(4), SMPL(2) }, /* 5.0 : 200ns, 100ns */
272 { NS(225), ACKW(4), SMPL(4) }, /* 4.4 : 225ns, 100ns */
273 { NS(250), ACKW(4), SMPL(4) }, /* 4.0 : 250ns, 100ns */
274 { NS(275), ACKW(4), SMPL(4) }, /* 3.64: 275ns, 100ns */
275 { NS(300), ACKW(4), SMPL(4) }, /* 3.33: 300ns, 100ns */
276 { NS(325), ACKW(4), SMPL(4) }, /* 3.01: 325ns, 100ns */
277 { NS(350), ACKW(4), SMPL(4) }, /* 2.86: 350ns, 100ns */
278 { NS(375), ACKW(4), SMPL(4) }, /* 2.67: 375ns, 100ns */
279 { NS(400), ACKW(4), SMPL(4) } /* 2.50: 400ns, 100ns */
280 };
281
282 #ifdef NJSC32_SUPPORT_OTHER_CLOCKS
283 /* 20MHz (50ns) */
284 static const struct njsc32_sync_param njsc32_synct_20M[NJSC32_NSYNCT] = {
285 { 0, 0, 0 }, /* dummy for async */
286 { NS(100), ACKW(1), 0 }, /* 10.0 : 100ns, 50ns */
287 { NS(150), ACKW(1), SMPL(2) }, /* 6.7 : 150ns, 50ns */
288 { NS(200), ACKW(2), SMPL(2) }, /* 5.0 : 200ns, 100ns */
289 { NS(250), ACKW(2), SMPL(4) }, /* 4.0 : 250ns, 100ns */
290 { NS(300), ACKW(3), SMPL(4) }, /* 3.3 : 300ns, 150ns */
291 { NS(350), ACKW(3), SMPL(4) }, /* 2.8 : 350ns, 150ns */
292 { NS(400), ACKW(4), SMPL(4) }, /* 2.5 : 400ns, 200ns */
293 { NS(450), ACKW(4), SMPL(4) }, /* 2.2 : 450ns, 200ns */
294 { NS(500), ACKW(4), SMPL(4) }, /* 2.0 : 500ns, 200ns */
295 { NS(550), ACKW(4), SMPL(4) }, /* 1.82: 550ns, 200ns */
296 { NS(600), ACKW(4), SMPL(4) }, /* 1.67: 600ns, 200ns */
297 { NS(650), ACKW(4), SMPL(4) }, /* 1.54: 650ns, 200ns */
298 { NS(700), ACKW(4), SMPL(4) }, /* 1.43: 700ns, 200ns */
299 { NS(750), ACKW(4), SMPL(4) }, /* 1.33: 750ns, 200ns */
300 { NS(800), ACKW(4), SMPL(4) } /* 1.25: 800ns, 200ns */
301 };
302
303 /* 33.3MHz (30ns) */
304 static const struct njsc32_sync_param njsc32_synct_pci[NJSC32_NSYNCT] = {
305 { 0, 0, 0 }, /* dummy for async */
306 { NS( 60), ACKW(1), 0 }, /* 16.6 : 60ns, 30ns */
307 { NS( 90), ACKW(1), SMPL(1) }, /* 11.1 : 90ns, 30ns */
308 { NS(120), ACKW(2), SMPL(2) }, /* 8.3 : 120ns, 60ns */
309 { NS(150), ACKW(2), SMPL(2) }, /* 6.7 : 150ns, 60ns */
310 { NS(180), ACKW(3), SMPL(2) }, /* 5.6 : 180ns, 90ns */
311 { NS(210), ACKW(3), SMPL(4) }, /* 4.8 : 210ns, 90ns */
312 { NS(240), ACKW(4), SMPL(4) }, /* 4.2 : 240ns, 120ns */
313 { NS(270), ACKW(4), SMPL(4) }, /* 3.7 : 270ns, 120ns */
314 { NS(300), ACKW(4), SMPL(4) }, /* 3.3 : 300ns, 120ns */
315 { NS(330), ACKW(4), SMPL(4) }, /* 3.0 : 330ns, 120ns */
316 { NS(360), ACKW(4), SMPL(4) }, /* 2.8 : 360ns, 120ns */
317 { NS(390), ACKW(4), SMPL(4) }, /* 2.6 : 390ns, 120ns */
318 { NS(420), ACKW(4), SMPL(4) }, /* 2.4 : 420ns, 120ns */
319 { NS(450), ACKW(4), SMPL(4) }, /* 2.2 : 450ns, 120ns */
320 { NS(480), ACKW(4), SMPL(4) } /* 2.1 : 480ns, 120ns */
321 };
322 #endif /* NJSC32_SUPPORT_OTHER_CLOCKS */
323
324 #undef NS
325 #undef ACKW
326 #undef SMPL
327
328 /* initialize device */
329 static void
330 njsc32_init(struct njsc32_softc *sc, int nosleep)
331 {
332 u_int16_t intstat;
333 int i;
334
335 /* block all interrupts */
336 njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL);
337
338 /* clear transfer */
339 njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0);
340 njsc32_write_4(sc, NJSC32_REG_BM_CNT, 0);
341
342 /* make sure interrupts are cleared */
343 for (i = 0; ((intstat = njsc32_read_2(sc, NJSC32_REG_IRQ))
344 & NJSC32_IRQ_INTR_PENDING) && i < 5 /* just not forever */; i++) {
345 DPRINTF(("%s: njsc32_init: intr pending: %#x\n",
346 sc->sc_dev.dv_xname, intstat));
347 }
348
349 /* FIFO threshold */
350 njsc32_ireg_write_1(sc, NJSC32_IREG_FIFO_THRESHOLD_FULL,
351 NJSC32_FIFO_FULL_BUSMASTER);
352 njsc32_ireg_write_1(sc, NJSC32_IREG_FIFO_THRESHOLD_EMPTY,
353 NJSC32_FIFO_EMPTY_BUSMASTER);
354
355 /* clock source */
356 njsc32_ireg_write_1(sc, NJSC32_IREG_CLOCK, sc->sc_clk);
357
358 /* memory read multiple */
359 njsc32_ireg_write_1(sc, NJSC32_IREG_BM,
360 NJSC32_BM_MEMRD_CMD1 | NJSC32_BM_SGT_AUTO_PARA_MEMRD_CMD);
361
362 /* clear parity error and enable parity detection */
363 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL,
364 NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR);
365
366 /* misc configuration */
367 njsc32_ireg_write_2(sc, NJSC32_IREG_MISC,
368 NJSC32_MISC_SCSI_DIRECTION_DETECTOR_SELECT |
369 NJSC32_MISC_DELAYED_BMSTART |
370 NJSC32_MISC_MASTER_TERMINATION_SELECT |
371 NJSC32_MISC_BMREQ_NEGATE_TIMING_SEL |
372 NJSC32_MISC_AUTOSEL_TIMING_SEL |
373 NJSC32_MISC_BMSTOP_CHANGE2_NONDATA_PHASE);
374
375 /*
376 * Check for termination power (32Bi and some versions of 32UDE).
377 */
378 if (!nosleep || cold) {
379 DPRINTF(("%s: njsc32_init: checking TERMPWR\n",
380 sc->sc_dev.dv_xname));
381
382 /* First, turn termination power off */
383 njsc32_ireg_write_1(sc, NJSC32_IREG_TERM_PWR, 0);
384
385 /* give 0.5s to settle */
386 if (nosleep)
387 delay(500000);
388 else
389 tsleep(sc, PWAIT, "njs_t1", hz / 2);
390 }
391
392 /* supply termination power if not supplied by other devices */
393 if ((njsc32_ireg_read_1(sc, NJSC32_IREG_TERM_PWR) &
394 NJSC32_TERMPWR_SENSE) == 0) {
395 /* termination power is not present on the bus */
396 if (sc->sc_flags & NJSC32_CANNOT_SUPPLY_TERMPWR) {
397 /*
398 * CardBus device must not supply termination power
399 * to avoid excessive power consumption.
400 */
401 printf("%s: no termination power present\n",
402 sc->sc_dev.dv_xname);
403 } else {
404 /* supply termination power */
405 njsc32_ireg_write_1(sc, NJSC32_IREG_TERM_PWR,
406 NJSC32_TERMPWR_BPWR);
407
408 DPRINTF(("%s: supplying termination power\n",
409 sc->sc_dev.dv_xname));
410
411 /* give 0.5s to settle */
412 if (!nosleep)
413 tsleep(sc, PWAIT, "njs_t2", hz / 2);
414 }
415 }
416
417 /* stop timer */
418 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP);
419 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP);
420
421 /* default transfer parameter */
422 njsc32_write_1(sc, NJSC32_REG_SYNC, 0);
423 njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, NJSC32_ACK_WIDTH_1CLK);
424 njsc32_write_2(sc, NJSC32_REG_SEL_TIMEOUT,
425 NJSC32_SEL_TIMEOUT_TIME);
426
427 /* select interrupt source */
428 njsc32_ireg_write_2(sc, NJSC32_IREG_IRQ_SELECT,
429 NJSC32_IRQSEL_RESELECT |
430 NJSC32_IRQSEL_PHASE_CHANGE |
431 NJSC32_IRQSEL_SCSIRESET |
432 NJSC32_IRQSEL_TIMER |
433 NJSC32_IRQSEL_FIFO_THRESHOLD |
434 NJSC32_IRQSEL_TARGET_ABORT |
435 NJSC32_IRQSEL_MASTER_ABORT |
436 /* XXX not yet
437 NJSC32_IRQSEL_SERR |
438 NJSC32_IRQSEL_PERR |
439 NJSC32_IRQSEL_BMCNTERR |
440 */
441 NJSC32_IRQSEL_AUTO_SCSI_SEQ);
442
443 /* interrupts will be unblocked later after bus reset */
444
445 /* turn LED off */
446 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT_DDR,
447 NJSC32_EXTPORT_LED_OFF);
448 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT,
449 NJSC32_EXTPORT_LED_OFF);
450
451 /* reset SCSI bus so the targets become known state */
452 njsc32_reset_bus(sc);
453 }
454
455 static int
456 njsc32_init_cmds(struct njsc32_softc *sc)
457 {
458 struct njsc32_cmd *cmd;
459 bus_addr_t dmaaddr;
460 int i, error;
461
462 /*
463 * allocate DMA area for command
464 */
465 if ((error = bus_dmamem_alloc(sc->sc_dmat,
466 sizeof(struct njsc32_dma_page), PAGE_SIZE, 0,
467 &sc->sc_cmdpg_seg, 1, &sc->sc_cmdpg_nsegs, BUS_DMA_NOWAIT)) != 0) {
468 printf("%s: unable to allocate cmd page, error = %d\n",
469 sc->sc_dev.dv_xname, error);
470 return 0;
471 }
472 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmdpg_seg,
473 sc->sc_cmdpg_nsegs, sizeof(struct njsc32_dma_page),
474 (caddr_t *)&sc->sc_cmdpg,
475 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
476 printf("%s: unable to map cmd page, error = %d\n",
477 sc->sc_dev.dv_xname, error);
478 goto fail1;
479 }
480 if ((error = bus_dmamap_create(sc->sc_dmat,
481 sizeof(struct njsc32_dma_page), 1,
482 sizeof(struct njsc32_dma_page), 0, BUS_DMA_NOWAIT,
483 &sc->sc_dmamap_cmdpg)) != 0) {
484 printf("%s: unable to create cmd DMA map, error = %d\n",
485 sc->sc_dev.dv_xname, error);
486 goto fail2;
487 }
488 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_cmdpg,
489 sc->sc_cmdpg, sizeof(struct njsc32_dma_page),
490 NULL, BUS_DMA_NOWAIT)) != 0) {
491 printf("%s: unable to load cmd DMA map, error = %d\n",
492 sc->sc_dev.dv_xname, error);
493 goto fail3;
494 }
495
496 memset(sc->sc_cmdpg, 0, sizeof(struct njsc32_dma_page));
497 dmaaddr = sc->sc_dmamap_cmdpg->dm_segs[0].ds_addr;
498
499 #ifdef NJSC32_AUTOPARAM
500 sc->sc_ap_dma = dmaaddr + offsetof(struct njsc32_dma_page, dp_ap);
501 #endif
502
503 for (i = 0; i < NJSC32_NUM_CMD; i++) {
504 cmd = &sc->sc_cmds[i];
505 cmd->c_sc = sc;
506 cmd->c_sgt = sc->sc_cmdpg->dp_sg[i];
507 cmd->c_sgt_dma = dmaaddr +
508 offsetof(struct njsc32_dma_page, dp_sg[i]);
509 cmd->c_flags = 0;
510
511 error = bus_dmamap_create(sc->sc_dmat,
512 NJSC32_MAX_XFER, /* max total map size */
513 NJSC32_NUM_SG, /* max number of segments */
514 NJSC32_SGT_MAXSEGLEN, /* max size of a segment */
515 0, /* boundary */
516 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &cmd->c_dmamap_xfer);
517 if (error) {
518 printf("%s: only %d cmd descs available (error = %d)\n",
519 sc->sc_dev.dv_xname, i, error);
520 break;
521 }
522 TAILQ_INSERT_TAIL(&sc->sc_freecmd, cmd, c_q);
523 }
524
525 if (i > 0)
526 return i;
527
528 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_cmdpg);
529 fail3: bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_cmdpg);
530 fail2: bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_cmdpg,
531 sizeof(struct njsc32_dma_page));
532 fail1: bus_dmamem_free(sc->sc_dmat, &sc->sc_cmdpg_seg, sc->sc_cmdpg_nsegs);
533
534 return 0;
535 }
536
537 static void
538 njsc32_target_async(struct njsc32_softc *sc, struct njsc32_target *target)
539 {
540
541 target->t_sync =
542 NJSC32_SYNC_VAL(sc->sc_sync_max, NJSC32_SYNCOFFSET_ASYNC);
543 target->t_ackwidth = NJSC32_ACK_WIDTH_1CLK;
544 target->t_sample = 0; /* disable */
545 target->t_syncoffset = NJSC32_SYNCOFFSET_ASYNC;
546 target->t_syncperiod = NJSC32_SYNCPERIOD_ASYNC;
547 }
548
549 static void
550 njsc32_init_targets(struct njsc32_softc *sc)
551 {
552 int id, lun;
553 struct njsc32_lu *lu;
554
555 for (id = 0; id <= NJSC32_MAX_TARGET_ID; id++) {
556 /* cancel negotiation status */
557 sc->sc_targets[id].t_state = NJSC32_TARST_INIT;
558
559 /* default to async mode */
560 njsc32_target_async(sc, &sc->sc_targets[id]);
561
562 #ifdef NJSC32_DUALEDGE
563 sc->sc_targets[id].t_xferctl = 0;
564 #endif
565
566 sc->sc_targets[id].t_targetid =
567 (1 << id) | (1 << NJSC32_INITIATOR_ID);
568
569 /* init logical units */
570 for (lun = 0; lun < NJSC32_NLU; lun++) {
571 lu = &sc->sc_targets[id].t_lus[lun];
572 lu->lu_cmd = NULL;
573 TAILQ_INIT(&lu->lu_q);
574 }
575 }
576 }
577
578 void
579 njsc32_attach(struct njsc32_softc *sc)
580 {
581 const char *str;
582 #if 1 /* test */
583 int reg;
584 njsc32_model_t detected_model;
585 #endif
586
587 /* init */
588 TAILQ_INIT(&sc->sc_freecmd);
589 TAILQ_INIT(&sc->sc_reqcmd);
590 callout_init(&sc->sc_callout);
591
592 #if 1 /* test */
593 /*
594 * try to distinguish 32Bi and 32UDE
595 */
596 /* try to set DualEdge bit (exists on 32UDE only) and read it back */
597 njsc32_write_2(sc, NJSC32_REG_TRANSFER, NJSC32_XFR_DUALEDGE_ENABLE);
598 if ((reg = njsc32_read_2(sc, NJSC32_REG_TRANSFER)) == 0xffff) {
599 /* device was removed? */
600 aprint_error("%s: attach failed\n", sc->sc_dev.dv_xname);
601 return;
602 } else if (reg & NJSC32_XFR_DUALEDGE_ENABLE) {
603 detected_model = NJSC32_MODEL_32UDE | NJSC32_FLAG_DUALEDGE;
604 } else {
605 detected_model = NJSC32_MODEL_32BI;
606 }
607 njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0); /* restore */
608
609 #if 1/*def DIAGNOSTIC*/
610 /* compare what is configured with what is detected */
611 if ((sc->sc_model & NJSC32_MODEL_MASK) !=
612 (detected_model & NJSC32_MODEL_MASK)) {
613 /*
614 * Please report this error if it happens.
615 */
616 aprint_error("%s: model mismatch: %#x vs %#x\n",
617 sc->sc_dev.dv_xname, sc->sc_model, detected_model);
618 return;
619 }
620 #endif
621 #endif
622
623 /* check model */
624 switch (sc->sc_model & NJSC32_MODEL_MASK) {
625 case NJSC32_MODEL_32BI:
626 str = "Bi";
627 /* 32Bi doesn't support DualEdge transfer */
628 KASSERT((sc->sc_model & NJSC32_FLAG_DUALEDGE) == 0);
629 break;
630 case NJSC32_MODEL_32UDE:
631 str = "UDE";
632 break;
633 default:
634 aprint_error("%s: unknown model!\n", sc->sc_dev.dv_xname);
635 return;
636 }
637 aprint_normal("%s: NJSC-32%s", sc->sc_dev.dv_xname, str);
638
639 switch (sc->sc_clk) {
640 default:
641 #ifdef DIAGNOSTIC
642 panic("njsc32_attach: unknown clk %d", sc->sc_clk);
643 #endif
644 case NJSC32_CLOCK_DIV_4:
645 sc->sc_synct = njsc32_synct_40M;
646 str = "40MHz";
647 break;
648 #ifdef NJSC32_SUPPORT_OTHER_CLOCKS
649 case NJSC32_CLOCK_DIV_2:
650 sc->sc_synct = njsc32_synct_20M;
651 str = "20MHz";
652 break;
653 case NJSC32_CLOCK_PCICLK:
654 sc->sc_synct = njsc32_synct_pci;
655 str = "PCI";
656 break;
657 #endif
658 }
659 aprint_normal(", G/A rev %#x, clk %s%s\n",
660 NJSC32_INDEX_GAREV(njsc32_read_2(sc, NJSC32_REG_INDEX)), str,
661 (sc->sc_model & NJSC32_FLAG_DUALEDGE) ?
662 #ifdef NJSC32_DUALEDGE
663 ", DualEdge"
664 #else
665 ", DualEdge (no driver support)"
666 #endif
667 : "");
668
669 /* allocate DMA resource */
670 if ((sc->sc_ncmd = njsc32_init_cmds(sc)) == 0) {
671 printf("%s: no usable DMA map\n", sc->sc_dev.dv_xname);
672 return;
673 }
674 sc->sc_flags |= NJSC32_CMDPG_MAPPED;
675
676 sc->sc_curcmd = NULL;
677 sc->sc_nusedcmds = 0;
678
679 sc->sc_sync_max = 1; /* XXX look up EEPROM configuration? */
680
681 /* initialize hardware and target structure */
682 njsc32_init(sc, cold);
683
684 /* setup adapter */
685 sc->sc_adapter.adapt_dev = &sc->sc_dev;
686 sc->sc_adapter.adapt_nchannels = 1;
687 sc->sc_adapter.adapt_request = njsc32_scsipi_request;
688 sc->sc_adapter.adapt_minphys = njsc32_scsipi_minphys;
689 sc->sc_adapter.adapt_ioctl = njsc32_scsipi_ioctl;
690
691 sc->sc_adapter.adapt_max_periph = sc->sc_adapter.adapt_openings =
692 sc->sc_ncmd;
693
694 /* setup channel */
695 sc->sc_channel.chan_adapter = &sc->sc_adapter;
696 sc->sc_channel.chan_bustype = &scsi_bustype;
697 sc->sc_channel.chan_channel = 0;
698 sc->sc_channel.chan_ntargets = NJSC32_NTARGET;
699 sc->sc_channel.chan_nluns = NJSC32_NLU;
700 sc->sc_channel.chan_id = NJSC32_INITIATOR_ID;
701
702 sc->sc_scsi = config_found(&sc->sc_dev, &sc->sc_channel, scsiprint);
703 }
704
705 int
706 njsc32_detach(struct njsc32_softc *sc, int flags)
707 {
708 int rv = 0;
709 int i, s;
710 struct njsc32_cmd *cmd;
711
712 callout_stop(&sc->sc_callout);
713
714 s = splbio();
715
716 /* clear running/disconnected commands */
717 njsc32_clear_cmds(sc, XS_DRIVER_STUFFUP);
718
719 sc->sc_stat = NJSC32_STAT_DETACH;
720
721 /* clear pending commands */
722 while ((cmd = TAILQ_FIRST(&sc->sc_reqcmd)) != NULL) {
723 TAILQ_REMOVE(&sc->sc_reqcmd, cmd, c_q);
724 njsc32_end_cmd(sc, cmd, XS_RESET);
725 }
726
727 if (sc->sc_scsi != NULL)
728 rv = config_detach(sc->sc_scsi, flags);
729
730 splx(s);
731
732 /* free DMA resource */
733 if (sc->sc_flags & NJSC32_CMDPG_MAPPED) {
734 for (i = 0; i < sc->sc_ncmd; i++) {
735 cmd = &sc->sc_cmds[i];
736 if (cmd->c_flags & NJSC32_CMD_DMA_MAPPED)
737 bus_dmamap_unload(sc->sc_dmat,
738 cmd->c_dmamap_xfer);
739 bus_dmamap_destroy(sc->sc_dmat, cmd->c_dmamap_xfer);
740 }
741
742 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_cmdpg);
743 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_cmdpg);
744 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_cmdpg,
745 sizeof(struct njsc32_dma_page));
746 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmdpg_seg,
747 sc->sc_cmdpg_nsegs);
748 }
749
750 return 0;
751 }
752
753 static inline void
754 njsc32_cmd_init(struct njsc32_cmd *cmd)
755 {
756
757 cmd->c_flags = 0;
758
759 /* scatter/gather table */
760 cmd->c_sgtdmaaddr = NJSC32_CMD_DMAADDR_SGT(cmd, 0);
761 cmd->c_sgoffset = 0;
762 cmd->c_sgfixcnt = 0;
763
764 /* data pointer */
765 cmd->c_dp_cur = cmd->c_dp_saved = cmd->c_dp_max = 0;
766 }
767
768 static inline void
769 njsc32_init_msgout(struct njsc32_softc *sc)
770 {
771
772 sc->sc_msgoutlen = 0;
773 sc->sc_msgoutidx = 0;
774 }
775
776 static void
777 njsc32_add_msgout(struct njsc32_softc *sc, int byte)
778 {
779
780 if (sc->sc_msgoutlen >= NJSC32_MSGOUT_LEN) {
781 printf("njsc32_add_msgout: too many\n");
782 return;
783 }
784 sc->sc_msgout[sc->sc_msgoutlen++] = byte;
785 }
786
787 static u_int32_t
788 njsc32_get_auto_msgout(struct njsc32_softc *sc)
789 {
790 u_int32_t val;
791 u_int8_t *p;
792
793 val = 0;
794 p = sc->sc_msgout;
795 switch (sc->sc_msgoutlen) {
796 /* 31-24 23-16 15-8 7 ... 1 0 */
797 case 3: /* MSG3 MSG2 MSG1 V --- cnt */
798 val |= *p++ << NJSC32_MSGOUT_MSG1_SHIFT;
799 /* FALLTHROUGH */
800
801 case 2: /* MSG2 MSG1 --- V --- cnt */
802 val |= *p++ << NJSC32_MSGOUT_MSG2_SHIFT;
803 /* FALLTHROUGH */
804
805 case 1: /* MSG1 --- --- V --- cnt */
806 val |= *p++ << NJSC32_MSGOUT_MSG3_SHIFT;
807 val |= NJSC32_MSGOUT_VALID | sc->sc_msgoutlen;
808 break;
809
810 default:
811 break;
812 }
813 return val;
814 }
815
816 #ifdef NJSC32_DUALEDGE
817 /* add Wide Data Transfer Request to the next Message Out */
818 static void
819 njsc32_msgout_wdtr(struct njsc32_softc *sc, int width)
820 {
821
822 njsc32_add_msgout(sc, MSG_EXTENDED);
823 njsc32_add_msgout(sc, MSG_EXT_WDTR_LEN);
824 njsc32_add_msgout(sc, MSG_EXT_WDTR);
825 njsc32_add_msgout(sc, width);
826 }
827 #endif
828
829 /* add Synchronous Data Transfer Request to the next Message Out */
830 static void
831 njsc32_msgout_sdtr(struct njsc32_softc *sc, int period, int offset)
832 {
833
834 njsc32_add_msgout(sc, MSG_EXTENDED);
835 njsc32_add_msgout(sc, MSG_EXT_SDTR_LEN);
836 njsc32_add_msgout(sc, MSG_EXT_SDTR);
837 njsc32_add_msgout(sc, period);
838 njsc32_add_msgout(sc, offset);
839 }
840
841 static void
842 njsc32_negotiate_xfer(struct njsc32_softc *sc, struct njsc32_target *target)
843 {
844
845 /* initial negotiation state */
846 if (target->t_state == NJSC32_TARST_INIT) {
847 #ifdef NJSC32_DUALEDGE
848 if (target->t_flags & NJSC32_TARF_DE)
849 target->t_state = NJSC32_TARST_DE;
850 else
851 #endif
852 if (target->t_flags & NJSC32_TARF_SYNC)
853 target->t_state = NJSC32_TARST_SDTR;
854 else
855 target->t_state = NJSC32_TARST_DONE;
856 }
857
858 switch (target->t_state) {
859 default:
860 case NJSC32_TARST_INIT:
861 #ifdef DIAGNOSTIC
862 panic("njsc32_negotiate_xfer");
863 /* NOTREACHED */
864 #endif
865 /* FALLTHROUGH */
866 case NJSC32_TARST_DONE:
867 /* no more work */
868 break;
869
870 #ifdef NJSC32_DUALEDGE
871 case NJSC32_TARST_DE:
872 njsc32_msgout_wdtr(sc, 0xde /* XXX? */);
873 break;
874
875 case NJSC32_TARST_WDTR:
876 njsc32_msgout_wdtr(sc, MSG_EXT_WDTR_BUS_8_BIT);
877 break;
878 #endif
879
880 case NJSC32_TARST_SDTR:
881 njsc32_msgout_sdtr(sc, sc->sc_synct[sc->sc_sync_max].sp_period,
882 NJSC32_SYNCOFFSET_MAX);
883 break;
884
885 case NJSC32_TARST_ASYNC:
886 njsc32_msgout_sdtr(sc, NJSC32_SYNCPERIOD_ASYNC,
887 NJSC32_SYNCOFFSET_ASYNC);
888 break;
889 }
890 }
891
892 /* turn LED on */
893 static inline void
894 njsc32_led_on(struct njsc32_softc *sc)
895 {
896
897 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, NJSC32_EXTPORT_LED_ON);
898 }
899
900 /* turn LED off */
901 static inline void
902 njsc32_led_off(struct njsc32_softc *sc)
903 {
904
905 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, NJSC32_EXTPORT_LED_OFF);
906 }
907
908 static void
909 njsc32_arbitration_failed(struct njsc32_softc *sc)
910 {
911 struct njsc32_cmd *cmd;
912
913 if ((cmd = sc->sc_curcmd) == NULL || sc->sc_stat != NJSC32_STAT_ARBIT)
914 return;
915
916 if ((cmd->c_xs->xs_control & XS_CTL_POLL) == 0)
917 callout_stop(&cmd->c_xs->xs_callout);
918
919 sc->sc_stat = NJSC32_STAT_IDLE;
920 sc->sc_curcmd = NULL;
921
922 /* the command is no longer active */
923 if (--sc->sc_nusedcmds == 0)
924 njsc32_led_off(sc);
925 }
926
927 static inline void
928 njsc32_cmd_load(struct njsc32_softc *sc, struct njsc32_cmd *cmd)
929 {
930 struct njsc32_target *target;
931 struct scsipi_xfer *xs;
932 int i, control, lun;
933 u_int32_t msgoutreg;
934 #ifdef NJSC32_AUTOPARAM
935 struct njsc32_autoparam *ap;
936 #endif
937
938 xs = cmd->c_xs;
939 #ifdef NJSC32_AUTOPARAM
940 ap = &sc->sc_cmdpg->dp_ap;
941 #else
942 /* reset CDB pointer */
943 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, NJSC32_CMD_CLEAR_CDB_FIFO_PTR);
944 #endif
945
946 /* CDB */
947 TPRINTC(cmd, ("njsc32_cmd_load: CDB"));
948 for (i = 0; i < xs->cmdlen; i++) {
949 #ifdef NJSC32_AUTOPARAM
950 ap->ap_cdb[i].cdb_data = ((u_int8_t *)xs->cmd)[i];
951 #else
952 njsc32_write_1(sc, NJSC32_REG_COMMAND_DATA,
953 ((u_int8_t *)xs->cmd)[i]);
954 #endif
955 TPRINTF((" %02x", ((u_int8_t *)cmd->c_xs->cmd)[i]));
956 }
957 #ifdef NJSC32_AUTOPARAM /* XXX needed? */
958 for ( ; i < NJSC32_AUTOPARAM_CDBLEN; i++)
959 ap->ap_cdb[i].cdb_data = 0;
960 #endif
961
962 control = xs->xs_control;
963
964 /*
965 * Message Out
966 */
967 njsc32_init_msgout(sc);
968
969 /* Identify */
970 lun = xs->xs_periph->periph_lun;
971 njsc32_add_msgout(sc, (control & XS_CTL_REQSENSE) ?
972 MSG_IDENTIFY(lun, 0) : MSG_IDENTIFY(lun, 1));
973
974 /* tagged queueing */
975 if (control & XS_CTL_TAGMASK) {
976 njsc32_add_msgout(sc, xs->xs_tag_type);
977 njsc32_add_msgout(sc, xs->xs_tag_id);
978 TPRINTF((" (tag %#x %#x)\n", xs->xs_tag_type, xs->xs_tag_id));
979 }
980 TPRINTF(("\n"));
981
982 target = cmd->c_target;
983
984 /* transfer negotiation */
985 if (control & XS_CTL_REQSENSE)
986 target->t_state = NJSC32_TARST_INIT;
987 njsc32_negotiate_xfer(sc, target);
988
989 msgoutreg = njsc32_get_auto_msgout(sc);
990
991 #ifdef NJSC32_AUTOPARAM
992 ap->ap_msgout = htole32(msgoutreg);
993
994 ap->ap_sync = target->t_sync;
995 ap->ap_ackwidth = target->t_ackwidth;
996 ap->ap_targetid = target->t_targetid;
997 ap->ap_sample = target->t_sample;
998
999 ap->ap_cmdctl = htole16(NJSC32_CMD_CLEAR_CDB_FIFO_PTR |
1000 NJSC32_CMD_AUTO_COMMAND_PHASE |
1001 NJSC32_CMD_AUTO_SCSI_START | NJSC32_CMD_AUTO_ATN |
1002 NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02);
1003 #ifdef NJSC32_DUALEDGE
1004 ap->ap_xferctl = htole16(cmd->c_xferctl | target->t_xferctl);
1005 #else
1006 ap->ap_xferctl = htole16(cmd->c_xferctl);
1007 #endif
1008 ap->ap_sgtdmaaddr = htole32(cmd->c_sgtdmaaddr);
1009
1010 /* sync njsc32_autoparam */
1011 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg,
1012 offsetof(struct njsc32_dma_page, dp_ap), /* offset */
1013 sizeof(struct njsc32_autoparam),
1014 BUS_DMASYNC_PREWRITE);
1015
1016 /* autoparam DMA address */
1017 njsc32_write_4(sc, NJSC32_REG_SGT_ADR, sc->sc_ap_dma);
1018
1019 /* start command (autoparam) */
1020 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL,
1021 NJSC32_CMD_CLEAR_CDB_FIFO_PTR | NJSC32_CMD_AUTO_PARAMETER);
1022
1023 #else /* not NJSC32_AUTOPARAM */
1024
1025 njsc32_write_4(sc, NJSC32_REG_SCSI_MSG_OUT, msgoutreg);
1026
1027 /* load parameters */
1028 njsc32_write_1(sc, NJSC32_REG_TARGET_ID, target->t_targetid);
1029 njsc32_write_1(sc, NJSC32_REG_SYNC, target->t_sync);
1030 njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, target->t_ackwidth);
1031 njsc32_write_1(sc, NJSC32_REG_SREQ_SAMPLING, target->t_sample);
1032 njsc32_write_4(sc, NJSC32_REG_SGT_ADR, cmd->c_sgtdmaaddr);
1033 #ifdef NJSC32_DUALEDGE
1034 njsc32_write_2(sc, NJSC32_REG_TRANSFER,
1035 cmd->c_xferctl | target->t_xferctl);
1036 #else
1037 njsc32_write_2(sc, NJSC32_REG_TRANSFER, cmd->c_xferctl);
1038 #endif
1039 /* start AutoSCSI */
1040 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL,
1041 NJSC32_CMD_CLEAR_CDB_FIFO_PTR | NJSC32_CMD_AUTO_COMMAND_PHASE |
1042 NJSC32_CMD_AUTO_SCSI_START | NJSC32_CMD_AUTO_ATN |
1043 NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02);
1044 #endif /* not NJSC32_AUTOPARAM */
1045 }
1046
1047 /* Note: must be called at splbio() */
1048 static void
1049 njsc32_start(struct njsc32_softc *sc)
1050 {
1051 struct njsc32_cmd *cmd;
1052
1053 /* get a command to issue */
1054 TAILQ_FOREACH(cmd, &sc->sc_reqcmd, c_q) {
1055 if (cmd->c_lu->lu_cmd == NULL &&
1056 ((cmd->c_flags & NJSC32_CMD_TAGGED) ||
1057 TAILQ_EMPTY(&cmd->c_lu->lu_q)))
1058 break; /* OK, the logical unit is free */
1059 }
1060 if (!cmd)
1061 goto out; /* no work to do */
1062
1063 /* request will always fail if not in bus free phase */
1064 if (njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) !=
1065 NJSC32_BUSMON_BUSFREE)
1066 goto busy;
1067
1068 /* clear parity error and enable parity detection */
1069 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL,
1070 NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR);
1071
1072 njsc32_cmd_load(sc, cmd);
1073
1074 if (sc->sc_nusedcmds++ == 0)
1075 njsc32_led_on(sc);
1076
1077 sc->sc_curcmd = cmd;
1078 sc->sc_stat = NJSC32_STAT_ARBIT;
1079
1080 if ((cmd->c_xs->xs_control & XS_CTL_POLL) == 0) {
1081 callout_reset(&cmd->c_xs->xs_callout,
1082 mstohz(cmd->c_xs->timeout),
1083 njsc32_cmdtimeout, cmd);
1084 }
1085
1086 return;
1087
1088 busy: /* XXX retry counter */
1089 TPRINTF(("%s: njsc32_start: busy\n", sc->sc_dev.dv_xname));
1090 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_ARBITRATION_RETRY_TIME);
1091 out: njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0);
1092 }
1093
1094 static void
1095 njsc32_run_xfer(struct njsc32_softc *sc, struct scsipi_xfer *xs)
1096 {
1097 struct scsipi_periph *periph;
1098 int control;
1099 int lun;
1100 struct njsc32_cmd *cmd;
1101 int s, i, error;
1102
1103 periph = xs->xs_periph;
1104 KASSERT((unsigned)periph->periph_target <= NJSC32_MAX_TARGET_ID);
1105
1106 control = xs->xs_control;
1107 lun = periph->periph_lun;
1108
1109 /*
1110 * get a free cmd
1111 * (scsipi layer knows the number of cmds, so this shall never fail)
1112 */
1113 s = splbio();
1114 cmd = TAILQ_FIRST(&sc->sc_freecmd);
1115 KASSERT(cmd);
1116 TAILQ_REMOVE(&sc->sc_freecmd, cmd, c_q);
1117 splx(s);
1118
1119 /*
1120 * build a request
1121 */
1122 njsc32_cmd_init(cmd);
1123 cmd->c_xs = xs;
1124 cmd->c_target = &sc->sc_targets[periph->periph_target];
1125 cmd->c_lu = &cmd->c_target->t_lus[lun];
1126
1127 /* tagged queueing */
1128 if (control & XS_CTL_TAGMASK) {
1129 cmd->c_flags |= NJSC32_CMD_TAGGED;
1130 if (control & XS_CTL_HEAD_TAG)
1131 cmd->c_flags |= NJSC32_CMD_TAGGED_HEAD;
1132 }
1133
1134 /* map DMA buffer */
1135 cmd->c_datacnt = xs->datalen;
1136 if (xs->datalen) {
1137 /* Is XS_CTL_DATA_UIO ever used anywhere? */
1138 KASSERT((control & XS_CTL_DATA_UIO) == 0);
1139
1140 error = bus_dmamap_load(sc->sc_dmat, cmd->c_dmamap_xfer,
1141 xs->data, xs->datalen, NULL,
1142 ((control & XS_CTL_NOSLEEP) ?
1143 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) |
1144 BUS_DMA_STREAMING |
1145 ((control & XS_CTL_DATA_IN) ?
1146 BUS_DMA_READ : BUS_DMA_WRITE));
1147
1148 switch (error) {
1149 case 0:
1150 break;
1151 case ENOMEM:
1152 case EAGAIN:
1153 xs->error = XS_RESOURCE_SHORTAGE;
1154 goto map_failed;
1155 default:
1156 xs->error = XS_DRIVER_STUFFUP;
1157 map_failed:
1158 printf("%s: njsc32_run_xfer: map failed, error %d\n",
1159 sc->sc_dev.dv_xname, error);
1160 /* put it back to free command list */
1161 s = splbio();
1162 TAILQ_INSERT_HEAD(&sc->sc_freecmd, cmd, c_q);
1163 splx(s);
1164 /* abort this transfer */
1165 scsipi_done(xs);
1166 return;
1167 }
1168
1169 bus_dmamap_sync(sc->sc_dmat, cmd->c_dmamap_xfer,
1170 0, cmd->c_dmamap_xfer->dm_mapsize,
1171 (control & XS_CTL_DATA_IN) ?
1172 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
1173
1174 for (i = 0; i < cmd->c_dmamap_xfer->dm_nsegs; i++) {
1175 cmd->c_sgt[i].sg_addr =
1176 htole32(cmd->c_dmamap_xfer->dm_segs[i].ds_addr);
1177 cmd->c_sgt[i].sg_len =
1178 htole32(cmd->c_dmamap_xfer->dm_segs[i].ds_len);
1179 }
1180 /* end mark */
1181 cmd->c_sgt[i - 1].sg_len |= htole32(NJSC32_SGT_ENDMARK);
1182
1183 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg,
1184 (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, /* offset */
1185 NJSC32_SIZE_SGT,
1186 BUS_DMASYNC_PREWRITE);
1187
1188 cmd->c_flags |= NJSC32_CMD_DMA_MAPPED;
1189
1190 /* enable transfer */
1191 cmd->c_xferctl =
1192 NJSC32_XFR_TRANSFER_GO | NJSC32_XFR_BM_START |
1193 NJSC32_XFR_ALL_COUNT_CLR;
1194
1195 /* XXX How can we specify the DMA direction? */
1196
1197 #if 0 /* faster write mode? (doesn't work) */
1198 if ((control & XS_CTL_DATA_IN) == 0)
1199 cmd->c_xferctl |= NJSC32_XFR_ADVANCED_BM_WRITE;
1200 #endif
1201 } else {
1202 /* no data transfer */
1203 cmd->c_xferctl = 0;
1204 }
1205
1206 /* queue request */
1207 s = splbio();
1208 TAILQ_INSERT_TAIL(&sc->sc_reqcmd, cmd, c_q);
1209
1210 /* start the controller if idle */
1211 if (sc->sc_stat == NJSC32_STAT_IDLE)
1212 njsc32_start(sc);
1213
1214 splx(s);
1215
1216 if (control & XS_CTL_POLL) {
1217 /* wait for completion */
1218 /* XXX should handle timeout? */
1219 while ((xs->xs_status & XS_STS_DONE) == 0) {
1220 delay(1000);
1221 njsc32_intr(sc);
1222 }
1223 }
1224 }
1225
1226 static void
1227 njsc32_end_cmd(struct njsc32_softc *sc, struct njsc32_cmd *cmd,
1228 scsipi_xfer_result_t result)
1229 {
1230 struct scsipi_xfer *xs;
1231 int s;
1232 #ifdef DIAGNOSTIC
1233 struct njsc32_cmd *c;
1234 #endif
1235
1236 KASSERT(cmd);
1237
1238 #ifdef DIAGNOSTIC
1239 s = splbio();
1240 TAILQ_FOREACH(c, &sc->sc_freecmd, c_q) {
1241 if (cmd == c)
1242 panic("njsc32_end_cmd: already in free list");
1243 }
1244 splx(s);
1245 #endif
1246 xs = cmd->c_xs;
1247
1248 if (cmd->c_flags & NJSC32_CMD_DMA_MAPPED) {
1249 if (cmd->c_datacnt) {
1250 bus_dmamap_sync(sc->sc_dmat, cmd->c_dmamap_xfer,
1251 0, cmd->c_dmamap_xfer->dm_mapsize,
1252 (xs->xs_control & XS_CTL_DATA_IN) ?
1253 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1254
1255 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg,
1256 (char *)cmd->c_sgt - (char *)sc->sc_cmdpg,
1257 NJSC32_SIZE_SGT, BUS_DMASYNC_POSTWRITE);
1258 }
1259
1260 bus_dmamap_unload(sc->sc_dmat, cmd->c_dmamap_xfer);
1261 cmd->c_flags &= ~NJSC32_CMD_DMA_MAPPED;
1262 }
1263
1264 s = splbio();
1265 if ((xs->xs_control & XS_CTL_POLL) == 0)
1266 callout_stop(&xs->xs_callout);
1267
1268 TAILQ_INSERT_HEAD(&sc->sc_freecmd, cmd, c_q);
1269 splx(s);
1270
1271 xs->error = result;
1272 scsipi_done(xs);
1273
1274 if (--sc->sc_nusedcmds == 0)
1275 njsc32_led_off(sc);
1276 }
1277
1278 /*
1279 * request from scsipi layer
1280 */
1281 static void
1282 njsc32_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req,
1283 void *arg)
1284 {
1285 struct njsc32_softc *sc;
1286 struct scsipi_xfer_mode *xm;
1287 struct njsc32_target *target;
1288
1289 sc = (void *)chan->chan_adapter->adapt_dev;
1290
1291 switch (req) {
1292 case ADAPTER_REQ_RUN_XFER:
1293 njsc32_run_xfer(sc, arg);
1294 break;
1295
1296 case ADAPTER_REQ_GROW_RESOURCES:
1297 /* not supported */
1298 break;
1299
1300 case ADAPTER_REQ_SET_XFER_MODE:
1301 xm = arg;
1302 target = &sc->sc_targets[xm->xm_target];
1303
1304 target->t_flags = 0;
1305 if (xm->xm_mode & PERIPH_CAP_TQING)
1306 target->t_flags |= NJSC32_TARF_TAG;
1307 if (xm->xm_mode & PERIPH_CAP_SYNC) {
1308 target->t_flags |= NJSC32_TARF_SYNC;
1309 #ifdef NJSC32_DUALEDGE
1310 if (sc->sc_model & NJSC32_FLAG_DUALEDGE)
1311 target->t_flags |= NJSC32_TARF_DE;
1312 #endif
1313 }
1314 #ifdef NJSC32_DUALEDGE
1315 target->t_xferctl = 0;
1316 #endif
1317 target->t_state = NJSC32_TARST_INIT;
1318 njsc32_target_async(sc, target);
1319
1320 break;
1321 default:
1322 break;
1323 }
1324 }
1325
1326 static void
1327 njsc32_scsipi_minphys(struct buf *bp)
1328 {
1329
1330 if (bp->b_bcount > NJSC32_MAX_XFER)
1331 bp->b_bcount = NJSC32_MAX_XFER;
1332 minphys(bp);
1333 }
1334
1335 /*
1336 * On some versions of 32UDE (probably the earlier ones), the controller
1337 * detects continuous bus reset when the termination power is absent.
1338 * Make sure the system won't hang on such situation.
1339 */
1340 static void
1341 njsc32_wait_reset_release(void *arg)
1342 {
1343 struct njsc32_softc *sc = arg;
1344 struct njsc32_cmd *cmd;
1345
1346 /* clear pending commands */
1347 while ((cmd = TAILQ_FIRST(&sc->sc_reqcmd)) != NULL) {
1348 TAILQ_REMOVE(&sc->sc_reqcmd, cmd, c_q);
1349 njsc32_end_cmd(sc, cmd, XS_RESET);
1350 }
1351
1352 /* If Bus Reset is not released yet, schedule recheck. */
1353 if (njsc32_read_2(sc, NJSC32_REG_IRQ) & NJSC32_IRQ_SCSIRESET) {
1354 switch (sc->sc_stat) {
1355 case NJSC32_STAT_RESET:
1356 sc->sc_stat = NJSC32_STAT_RESET1;
1357 break;
1358 case NJSC32_STAT_RESET1:
1359 /* print message if Bus Reset is detected twice */
1360 sc->sc_stat = NJSC32_STAT_RESET2;
1361 printf("%s: detected excessive bus reset --- missing termination power?\n",
1362 sc->sc_dev.dv_xname);
1363 break;
1364 default:
1365 break;
1366 }
1367 callout_reset(&sc->sc_callout,
1368 hz * 2 /* poll every 2s */,
1369 njsc32_wait_reset_release, sc);
1370 return;
1371 }
1372
1373 if (sc->sc_stat == NJSC32_STAT_RESET2)
1374 printf("%s: bus reset is released\n", sc->sc_dev.dv_xname);
1375
1376 /* unblock interrupts */
1377 njsc32_write_2(sc, NJSC32_REG_IRQ, 0);
1378
1379 sc->sc_stat = NJSC32_STAT_IDLE;
1380 }
1381
1382 static void
1383 njsc32_reset_bus(struct njsc32_softc *sc)
1384 {
1385 int s;
1386
1387 DPRINTF(("%s: njsc32_reset_bus:\n", sc->sc_dev.dv_xname));
1388
1389 /* block interrupts */
1390 njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL);
1391
1392 sc->sc_stat = NJSC32_STAT_RESET;
1393
1394 /* hold SCSI bus reset */
1395 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, NJSC32_SBCTL_RST);
1396 delay(NJSC32_RESET_HOLD_TIME);
1397
1398 /* clear transfer */
1399 njsc32_clear_cmds(sc, XS_RESET);
1400
1401 /* initialize target structure */
1402 njsc32_init_targets(sc);
1403
1404 s = splbio();
1405 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_RESET, NULL);
1406 splx(s);
1407
1408 /* release SCSI bus reset */
1409 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, 0);
1410
1411 njsc32_wait_reset_release(sc);
1412 }
1413
1414 /*
1415 * clear running/disconnected commands
1416 */
1417 static void
1418 njsc32_clear_cmds(struct njsc32_softc *sc, scsipi_xfer_result_t cmdresult)
1419 {
1420 struct njsc32_cmd *cmd;
1421 int id, lun;
1422 struct njsc32_lu *lu;
1423
1424 njsc32_arbitration_failed(sc);
1425
1426 /* clear current transfer */
1427 if ((cmd = sc->sc_curcmd) != NULL) {
1428 sc->sc_curcmd = NULL;
1429 njsc32_end_cmd(sc, cmd, cmdresult);
1430 }
1431
1432 /* clear disconnected transfers */
1433 for (id = 0; id <= NJSC32_MAX_TARGET_ID; id++) {
1434 for (lun = 0; lun < NJSC32_NLU; lun++) {
1435 lu = &sc->sc_targets[id].t_lus[lun];
1436
1437 if ((cmd = lu->lu_cmd) != NULL) {
1438 lu->lu_cmd = NULL;
1439 njsc32_end_cmd(sc, cmd, cmdresult);
1440 }
1441 while ((cmd = TAILQ_FIRST(&lu->lu_q)) != NULL) {
1442 TAILQ_REMOVE(&lu->lu_q, cmd, c_q);
1443 njsc32_end_cmd(sc, cmd, cmdresult);
1444 }
1445 }
1446 }
1447 }
1448
1449 static int
1450 njsc32_scsipi_ioctl(struct scsipi_channel *chan, u_long cmd,
1451 caddr_t addr, int flag, struct proc *p)
1452 {
1453 struct njsc32_softc *sc = (void *)chan->chan_adapter->adapt_dev;
1454
1455 switch (cmd) {
1456 case SCBUSIORESET:
1457 njsc32_init(sc, 0);
1458 return 0;
1459 default:
1460 break;
1461 }
1462
1463 return ENOTTY;
1464 }
1465
1466 /*
1467 * set current data pointer
1468 */
1469 static inline void
1470 njsc32_set_cur_ptr(struct njsc32_cmd *cmd, u_int32_t pos)
1471 {
1472
1473 /* new current data pointer */
1474 cmd->c_dp_cur = pos;
1475
1476 /* update number of bytes transferred */
1477 if (pos > cmd->c_dp_max)
1478 cmd->c_dp_max = pos;
1479 }
1480
1481 /*
1482 * set data pointer for the next transfer
1483 */
1484 static void
1485 njsc32_set_ptr(struct njsc32_softc *sc, struct njsc32_cmd *cmd, u_int32_t pos)
1486 {
1487 struct njsc32_sgtable *sg;
1488 unsigned sgte;
1489 u_int32_t len;
1490
1491 /* set current pointer */
1492 njsc32_set_cur_ptr(cmd, pos);
1493
1494 /* undo previous fix if any */
1495 if (cmd->c_sgfixcnt != 0) {
1496 sg = &cmd->c_sgt[cmd->c_sgoffset];
1497 sg->sg_addr = htole32(le32toh(sg->sg_addr) - cmd->c_sgfixcnt);
1498 sg->sg_len = htole32(le32toh(sg->sg_len) + cmd->c_sgfixcnt);
1499 cmd->c_sgfixcnt = 0;
1500 }
1501
1502 if (pos >= cmd->c_datacnt) {
1503 /* transfer done */
1504 #if 1 /*def DIAGNOSTIC*/
1505 if (pos > cmd->c_datacnt)
1506 printf("%s: pos %u too large\n",
1507 sc->sc_dev.dv_xname, pos - cmd->c_datacnt);
1508 #endif
1509 cmd->c_xferctl = 0; /* XXX correct? */
1510
1511 return;
1512 }
1513
1514 for (sgte = 0, sg = cmd->c_sgt;
1515 sgte < NJSC32_NUM_SG && pos > 0; sgte++, sg++) {
1516 len = le32toh(sg->sg_len) & ~NJSC32_SGT_ENDMARK;
1517 if (pos < len) {
1518 sg->sg_addr = htole32(le32toh(sg->sg_addr) + pos);
1519 sg->sg_len = htole32(le32toh(sg->sg_len) - pos);
1520 cmd->c_sgfixcnt = pos;
1521 break;
1522 }
1523 pos -= len;
1524 #ifdef DIAGNOSTIC
1525 if (sg->sg_len & htole32(NJSC32_SGT_ENDMARK)) {
1526 panic("njsc32_set_ptr: bad pos");
1527 }
1528 #endif
1529 }
1530 #ifdef DIAGNOSTIC
1531 if (sgte >= NJSC32_NUM_SG)
1532 panic("njsc32_set_ptr: bad sg");
1533 #endif
1534 if (cmd->c_sgoffset != sgte) {
1535 cmd->c_sgoffset = sgte;
1536 cmd->c_sgtdmaaddr = NJSC32_CMD_DMAADDR_SGT(cmd, sgte);
1537 }
1538
1539 /* XXX overkill */
1540 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg,
1541 (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, /* offset */
1542 NJSC32_SIZE_SGT,
1543 BUS_DMASYNC_PREWRITE);
1544 }
1545
1546 /*
1547 * save data pointer
1548 */
1549 static inline void
1550 njsc32_save_ptr(struct njsc32_cmd *cmd)
1551 {
1552
1553 cmd->c_dp_saved = cmd->c_dp_cur;
1554 }
1555
1556 static void
1557 njsc32_assert_ack(struct njsc32_softc *sc)
1558 {
1559 u_int8_t reg;
1560
1561 reg = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_CONTROL);
1562 reg |= NJSC32_SBCTL_ACK | NJSC32_SBCTL_ACK_ENABLE;
1563 #if 0 /* needed? */
1564 reg |= NJSC32_SBCTL_AUTODIRECTION;
1565 #endif
1566 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, reg);
1567 }
1568
1569 static void
1570 njsc32_negate_ack(struct njsc32_softc *sc)
1571 {
1572 u_int8_t reg;
1573
1574 reg = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_CONTROL);
1575 #if 0 /* needed? */
1576 reg |= NJSC32_SBCTL_ACK_ENABLE;
1577 reg |= NJSC32_SBCTL_AUTODIRECTION;
1578 #endif
1579 reg &= ~NJSC32_SBCTL_ACK;
1580 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, reg);
1581 }
1582
1583 static void
1584 njsc32_wait_req_negate(struct njsc32_softc *sc)
1585 {
1586 int cnt;
1587
1588 for (cnt = 0; cnt < NJSC32_REQ_TIMEOUT; cnt++) {
1589 if ((njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) &
1590 NJSC32_BUSMON_REQ) == 0)
1591 return;
1592 delay(1);
1593 }
1594 printf("%s: njsc32_wait_req_negate: timed out\n", sc->sc_dev.dv_xname);
1595 }
1596
1597 static void
1598 njsc32_reconnect(struct njsc32_softc *sc, struct njsc32_cmd *cmd)
1599 {
1600 struct scsipi_xfer *xs;
1601
1602 xs = cmd->c_xs;
1603 if ((xs->xs_control & XS_CTL_POLL) == 0) {
1604 callout_stop(&xs->xs_callout);
1605 callout_reset(&xs->xs_callout,
1606 mstohz(xs->timeout),
1607 njsc32_cmdtimeout, cmd);
1608 }
1609
1610 /* Reconnection implies Restore Pointers */
1611 njsc32_set_ptr(sc, cmd, cmd->c_dp_saved);
1612 }
1613
1614 static enum njsc32_reselstat
1615 njsc32_resel_identify(struct njsc32_softc *sc, int lun,
1616 struct njsc32_cmd **pcmd)
1617 {
1618 int targetid;
1619 struct njsc32_lu *plu;
1620 struct njsc32_cmd *cmd;
1621
1622 switch (sc->sc_stat) {
1623 case NJSC32_STAT_RESEL:
1624 break; /* OK */
1625
1626 case NJSC32_STAT_RESEL_LUN:
1627 case NJSC32_STAT_RECONNECT:
1628 /*
1629 * accept and ignore if the LUN is the same as the current one,
1630 * reject otherwise.
1631 */
1632 return sc->sc_resellun == lun ?
1633 NJSC32_RESEL_THROUGH : NJSC32_RESEL_ERROR;
1634
1635 default:
1636 printf("%s: njsc32_resel_identify: not in reselection\n",
1637 sc->sc_dev.dv_xname);
1638 return NJSC32_RESEL_ERROR;
1639 }
1640
1641 targetid = sc->sc_reselid;
1642 TPRINTF(("%s: njsc32_resel_identify: reselection lun %d\n",
1643 sc->sc_dev.dv_xname, lun));
1644
1645 if (targetid > NJSC32_MAX_TARGET_ID || lun >= NJSC32_NLU)
1646 return NJSC32_RESEL_ERROR;
1647
1648 sc->sc_resellun = lun;
1649 plu = &sc->sc_targets[targetid].t_lus[lun];
1650
1651 if ((cmd = plu->lu_cmd) != NULL) {
1652 sc->sc_stat = NJSC32_STAT_RECONNECT;
1653 plu->lu_cmd = NULL;
1654 *pcmd = cmd;
1655 TPRINTC(cmd, ("njsc32_resel_identify: I_T_L nexus\n"));
1656 njsc32_reconnect(sc, cmd);
1657 return NJSC32_RESEL_COMPLETE;
1658 } else if (!TAILQ_EMPTY(&plu->lu_q)) {
1659 /* wait for tag */
1660 sc->sc_stat = NJSC32_STAT_RESEL_LUN;
1661 return NJSC32_RESEL_THROUGH;
1662 }
1663
1664 /* no disconnected commands */
1665 return NJSC32_RESEL_ERROR;
1666 }
1667
1668 static enum njsc32_reselstat
1669 njsc32_resel_tag(struct njsc32_softc *sc, int tag, struct njsc32_cmd **pcmd)
1670 {
1671 struct njsc32_cmd_head *head;
1672 struct njsc32_cmd *cmd;
1673
1674 TPRINTF(("%s: njsc32_resel_tag: reselection tag %d\n",
1675 sc->sc_dev.dv_xname, tag));
1676 if (sc->sc_stat != NJSC32_STAT_RESEL_LUN)
1677 return NJSC32_RESEL_ERROR;
1678
1679 head = &sc->sc_targets[sc->sc_reselid].t_lus[sc->sc_resellun].lu_q;
1680
1681 /* XXX slow? */
1682 /* search for the command of the tag */
1683 TAILQ_FOREACH(cmd, head, c_q) {
1684 if (cmd->c_xs->xs_tag_id == tag) {
1685 sc->sc_stat = NJSC32_STAT_RECONNECT;
1686 TAILQ_REMOVE(head, cmd, c_q);
1687 *pcmd = cmd;
1688 TPRINTC(cmd, ("njsc32_resel_tag: I_T_L_Q nexus\n"));
1689 njsc32_reconnect(sc, cmd);
1690 return NJSC32_RESEL_COMPLETE;
1691 }
1692 }
1693
1694 /* no disconnected commands */
1695 return NJSC32_RESEL_ERROR;
1696 }
1697
1698 /*
1699 * Reload parameters and restart AutoSCSI.
1700 *
1701 * XXX autoparam doesn't work as expected and we can't use it here.
1702 */
1703 static void
1704 njsc32_cmd_reload(struct njsc32_softc *sc, struct njsc32_cmd *cmd, int cctl)
1705 {
1706 struct njsc32_target *target;
1707
1708 target = cmd->c_target;
1709
1710 /* clear parity error and enable parity detection */
1711 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL,
1712 NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR);
1713
1714 /* load parameters */
1715 njsc32_write_1(sc, NJSC32_REG_SYNC, target->t_sync);
1716 njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, target->t_ackwidth);
1717 njsc32_write_1(sc, NJSC32_REG_SREQ_SAMPLING, target->t_sample);
1718 njsc32_write_4(sc, NJSC32_REG_SGT_ADR, cmd->c_sgtdmaaddr);
1719 #ifdef NJSC32_DUALEDGE
1720 njsc32_write_2(sc, NJSC32_REG_TRANSFER,
1721 cmd->c_xferctl | target->t_xferctl);
1722 #else
1723 njsc32_write_2(sc, NJSC32_REG_TRANSFER, cmd->c_xferctl);
1724 #endif
1725 /* start AutoSCSI */
1726 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl);
1727
1728 sc->sc_curcmd = cmd;
1729 }
1730
1731 static void
1732 njsc32_update_xfer_mode(struct njsc32_softc *sc, struct njsc32_target *target)
1733 {
1734 struct scsipi_xfer_mode xm;
1735
1736 xm.xm_target = target - sc->sc_targets; /* target ID */
1737 xm.xm_mode = 0;
1738 xm.xm_period = target->t_syncperiod;
1739 xm.xm_offset = target->t_syncoffset;
1740 if (xm.xm_offset != 0)
1741 xm.xm_mode |= PERIPH_CAP_SYNC;
1742 if (target->t_flags & NJSC32_TARF_TAG)
1743 xm.xm_mode |= PERIPH_CAP_TQING;
1744
1745 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm);
1746 }
1747
1748 static void
1749 njsc32_msgin(struct njsc32_softc *sc)
1750 {
1751 u_int8_t msg0, msg;
1752 int msgcnt;
1753 struct njsc32_cmd *cmd;
1754 enum njsc32_reselstat rstat;
1755 int cctl = 0;
1756 u_int32_t ptr; /* unsigned type ensures 2-complement calculation */
1757 u_int32_t msgout = 0;
1758 boolean_t reload_params = FALSE;
1759 struct njsc32_target *target;
1760 int idx, period, offset;
1761
1762 /*
1763 * we are in Message In, so the previous Message Out should have
1764 * been done.
1765 */
1766 njsc32_init_msgout(sc);
1767
1768 /* get a byte of Message In */
1769 msg = njsc32_read_1(sc, NJSC32_REG_DATA_IN);
1770 TPRINTF(("%s: njsc32_msgin: got %#x\n", sc->sc_dev.dv_xname, msg));
1771 if ((msgcnt = sc->sc_msgincnt) < NJSC32_MSGIN_LEN)
1772 sc->sc_msginbuf[sc->sc_msgincnt] = msg;
1773
1774 njsc32_assert_ack(sc);
1775
1776 msg0 = sc->sc_msginbuf[0];
1777 cmd = sc->sc_curcmd;
1778
1779 /* check for parity error */
1780 if (njsc32_read_1(sc, NJSC32_REG_PARITY_STATUS) &
1781 NJSC32_PARITYSTATUS_ERROR_LSB) {
1782
1783 printf("%s: msgin: parity error\n", sc->sc_dev.dv_xname);
1784
1785 /* clear parity error */
1786 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL,
1787 NJSC32_PARITYCTL_CHECK_ENABLE |
1788 NJSC32_PARITYCTL_CLEAR_ERROR);
1789
1790 /* respond as Message Parity Error */
1791 njsc32_add_msgout(sc, MSG_PARITY_ERROR);
1792
1793 /* clear Message In */
1794 sc->sc_msgincnt = 0;
1795 goto reply;
1796 }
1797
1798 #define WAITNEXTMSG do { sc->sc_msgincnt++; goto restart; } while (0)
1799 #define MSGCOMPLETE do { sc->sc_msgincnt = 0; goto restart; } while (0)
1800 if (MSG_ISIDENTIFY(msg0)) {
1801 /*
1802 * Got Identify message from target.
1803 */
1804 if ((msg0 & ~MSG_IDENTIFY_LUNMASK) != MSG_IDENTIFYFLAG ||
1805 (rstat = njsc32_resel_identify(sc, msg0 &
1806 MSG_IDENTIFY_LUNMASK, &cmd)) == NJSC32_RESEL_ERROR) {
1807 /*
1808 * invalid Identify -> Reject
1809 */
1810 goto reject;
1811 }
1812 if (rstat == NJSC32_RESEL_COMPLETE)
1813 reload_params = TRUE;
1814 MSGCOMPLETE;
1815 }
1816
1817 if (msg0 == MSG_SIMPLE_Q_TAG) {
1818 if (msgcnt == 0)
1819 WAITNEXTMSG;
1820
1821 /* got whole message */
1822 sc->sc_msgincnt = 0;
1823
1824 if ((rstat = njsc32_resel_tag(sc, sc->sc_msginbuf[1], &cmd))
1825 == NJSC32_RESEL_ERROR) {
1826 /*
1827 * invalid Simple Queue Tag -> Abort Tag
1828 */
1829 printf("%s: msgin: invalid tag\n", sc->sc_dev.dv_xname);
1830 njsc32_add_msgout(sc, MSG_ABORT_TAG);
1831 goto reply;
1832 }
1833 if (rstat == NJSC32_RESEL_COMPLETE)
1834 reload_params = TRUE;
1835 MSGCOMPLETE;
1836 }
1837
1838 /* I_T_L or I_T_L_Q nexus should be established now */
1839 if (cmd == NULL) {
1840 printf("%s: msgin %#x without nexus -- sending abort\n",
1841 sc->sc_dev.dv_xname, msg0);
1842 njsc32_add_msgout(sc, MSG_ABORT);
1843 goto reply;
1844 }
1845
1846 /*
1847 * extended message
1848 * 0x01 <length (0 stands for 256)> <length bytes>
1849 * (<code> [<parameter> ...])
1850 */
1851 #define EXTLENOFF 1
1852 #define EXTCODEOFF 2
1853 if (msg0 == MSG_EXTENDED) {
1854 if (msgcnt < EXTLENOFF ||
1855 msgcnt < EXTLENOFF + 1 +
1856 (u_int8_t)(sc->sc_msginbuf[EXTLENOFF] - 1))
1857 WAITNEXTMSG;
1858
1859 /* got whole message */
1860 sc->sc_msgincnt = 0;
1861
1862 switch (sc->sc_msginbuf[EXTCODEOFF]) {
1863 case 0: /* Modify Data Pointer */
1864 if (msgcnt != 5 + EXTCODEOFF - 1)
1865 break;
1866 /*
1867 * parameter is 32bit big-endian signed (2-complement)
1868 * value
1869 */
1870 ptr = (sc->sc_msginbuf[EXTCODEOFF + 1] << 24) |
1871 (sc->sc_msginbuf[EXTCODEOFF + 2] << 16) |
1872 (sc->sc_msginbuf[EXTCODEOFF + 3] << 8) |
1873 sc->sc_msginbuf[EXTCODEOFF + 4];
1874
1875 /* new pointer */
1876 ptr += cmd->c_dp_cur; /* ignore overflow */
1877
1878 /* reject if ptr is not in data buffer */
1879 if (ptr > cmd->c_datacnt)
1880 break;
1881
1882 njsc32_set_ptr(sc, cmd, ptr);
1883 goto restart;
1884
1885 case MSG_EXT_SDTR: /* Synchronous Data Transfer Request */
1886 DPRINTC(cmd, ("SDTR %#x %#x\n",
1887 sc->sc_msginbuf[EXTCODEOFF + 1],
1888 sc->sc_msginbuf[EXTCODEOFF + 2]));
1889 if (msgcnt != MSG_EXT_SDTR_LEN + EXTCODEOFF-1)
1890 break; /* reject */
1891
1892 target = cmd->c_target;
1893
1894 /* lookup sync period parameters */
1895 period = sc->sc_msginbuf[EXTCODEOFF + 1];
1896 for (idx = sc->sc_sync_max; idx < NJSC32_NSYNCT; idx++)
1897 if (sc->sc_synct[idx].sp_period >= period) {
1898 period = sc->sc_synct[idx].sp_period;
1899 break;
1900 }
1901 if (idx >= NJSC32_NSYNCT) {
1902 /*
1903 * We can't meet the timing condition that
1904 * the target requests -- use async.
1905 */
1906 njsc32_target_async(sc, target);
1907 njsc32_update_xfer_mode(sc, target);
1908 if (target->t_state == NJSC32_TARST_SDTR) {
1909 /*
1910 * We started SDTR exchange -- start
1911 * negotiation again and request async.
1912 */
1913 target->t_state = NJSC32_TARST_ASYNC;
1914 njsc32_negotiate_xfer(sc, target);
1915 goto reply;
1916 } else {
1917 /*
1918 * The target started SDTR exchange
1919 * -- just reject and fallback
1920 * to async.
1921 */
1922 goto reject;
1923 }
1924 }
1925
1926 /* check sync offset */
1927 offset = sc->sc_msginbuf[EXTCODEOFF + 2];
1928 if (offset > NJSC32_SYNCOFFSET_MAX) {
1929 if (target->t_state == NJSC32_TARST_SDTR) {
1930 printf("%s: wrong sync offset: %d\n",
1931 cmd->c_xs->xs_periph->periph_dev->dv_xname,
1932 offset);
1933 /* XXX what to do? */
1934 }
1935 offset = NJSC32_SYNCOFFSET_MAX;
1936 }
1937
1938 target->t_ackwidth = sc->sc_synct[idx].sp_ackw;
1939 target->t_sample = sc->sc_synct[idx].sp_sample;
1940 target->t_syncperiod = period;
1941 target->t_syncoffset = offset;
1942 target->t_sync = NJSC32_SYNC_VAL(idx, offset);
1943 njsc32_update_xfer_mode(sc, target);
1944
1945 if (target->t_state == NJSC32_TARST_SDTR) {
1946 target->t_state = NJSC32_TARST_DONE;
1947 } else {
1948 njsc32_msgout_sdtr(sc, period, offset);
1949 goto reply;
1950 }
1951 goto restart;
1952
1953 case MSG_EXT_WDTR: /* Wide Data Transfer Request */
1954 DPRINTC(cmd,
1955 ("WDTR %#x\n", sc->sc_msginbuf[EXTCODEOFF + 1]));
1956 #ifdef NJSC32_DUALEDGE
1957 if (msgcnt != MSG_EXT_WDTR_LEN + EXTCODEOFF-1)
1958 break; /* reject */
1959
1960 /*
1961 * T->I of this message is not used for
1962 * DualEdge negotiation, so the device
1963 * must not be a DualEdge device.
1964 *
1965 * XXX correct?
1966 */
1967 target = cmd->c_target;
1968 target->t_xferctl = 0;
1969
1970 switch (target->t_state) {
1971 case NJSC32_TARST_DE:
1972 if (sc->sc_msginbuf[EXTCODEOFF + 1] !=
1973 MSG_EXT_WDTR_BUS_8_BIT) {
1974 /*
1975 * Oops, we got unexpected WDTR.
1976 * Negotiate for 8bit.
1977 */
1978 target->t_state = NJSC32_TARST_WDTR;
1979 } else {
1980 target->t_state = NJSC32_TARST_SDTR;
1981 }
1982 njsc32_negotiate_xfer(sc, target);
1983 goto reply;
1984
1985 case NJSC32_TARST_WDTR:
1986 if (sc->sc_msginbuf[EXTCODEOFF + 1] !=
1987 MSG_EXT_WDTR_BUS_8_BIT) {
1988 printf("%s: unexpected transfer width: %#x\n",
1989 cmd->c_xs->xs_periph->periph_dev->dv_xname,
1990 sc->sc_msginbuf[EXTCODEOFF + 1]);
1991 /* XXX what to do? */
1992 }
1993 target->t_state = NJSC32_TARST_SDTR;
1994 njsc32_negotiate_xfer(sc, target);
1995 goto reply;
1996
1997 default:
1998 /* the target started WDTR exchange */
1999 DPRINTC(cmd, ("WDTR from target\n"));
2000
2001 target->t_state = NJSC32_TARST_SDTR;
2002 njsc32_target_async(sc, target);
2003
2004 break; /* reject the WDTR (8bit transfer) */
2005 }
2006 #endif /* NJSC32_DUALEDGE */
2007 break; /* reject */
2008 }
2009 DPRINTC(cmd, ("njsc32_msgin: reject ext msg %#x msgincnt %d\n",
2010 sc->sc_msginbuf[EXTCODEOFF], msgcnt));
2011 goto reject;
2012 }
2013
2014 /* 2byte messages */
2015 if (MSG_IS2BYTE(msg0)) {
2016 if (msgcnt == 0)
2017 WAITNEXTMSG;
2018
2019 /* got whole message */
2020 sc->sc_msgincnt = 0;
2021 }
2022
2023 switch (msg0) {
2024 case MSG_CMDCOMPLETE: /* 0x00 */
2025 case MSG_SAVEDATAPOINTER: /* 0x02 */
2026 case MSG_DISCONNECT: /* 0x04 */
2027 /* handled by AutoSCSI */
2028 PRINTC(cmd, ("msgin: unexpected msg: %#x\n", msg0));
2029 break;
2030
2031 case MSG_RESTOREPOINTERS: /* 0x03 */
2032 /* restore data pointer to what was saved */
2033 DPRINTC(cmd, ("njsc32_msgin: Restore Pointers\n"));
2034 njsc32_set_ptr(sc, cmd, cmd->c_dp_saved);
2035 reload_params = TRUE;
2036 MSGCOMPLETE;
2037 /* NOTREACHED */
2038 break;
2039
2040 #if 0 /* handled above */
2041 case MSG_EXTENDED: /* 0x01 */
2042 #endif
2043 case MSG_MESSAGE_REJECT: /* 0x07 */
2044 target = cmd->c_target;
2045 DPRINTC(cmd, ("Reject tarst %d\n", target->t_state));
2046 switch (target->t_state) {
2047 #ifdef NJSC32_DUALEDGE
2048 case NJSC32_TARST_WDTR:
2049 case NJSC32_TARST_DE:
2050 target->t_xferctl = 0;
2051 target->t_state = NJSC32_TARST_SDTR;
2052 njsc32_negotiate_xfer(sc, target);
2053 goto reply;
2054 #endif
2055 case NJSC32_TARST_SDTR:
2056 case NJSC32_TARST_ASYNC:
2057 njsc32_target_async(sc, target);
2058 target->t_state = NJSC32_TARST_DONE;
2059 njsc32_update_xfer_mode(sc, target);
2060 break;
2061 default:
2062 break;
2063 }
2064 goto restart;
2065
2066 case MSG_NOOP: /* 0x08 */
2067 #ifdef NJSC32_DUALEDGE
2068 target = cmd->c_target;
2069 if (target->t_state == NJSC32_TARST_DE) {
2070 aprint_normal("%s: DualEdge transfer\n",
2071 cmd->c_xs->xs_periph->periph_dev->dv_xname);
2072 target->t_xferctl = NJSC32_XFR_DUALEDGE_ENABLE;
2073 /* go to next negotiation */
2074 target->t_state = NJSC32_TARST_SDTR;
2075 njsc32_negotiate_xfer(sc, target);
2076 goto reply;
2077 }
2078 #endif
2079 goto restart;
2080
2081 case MSG_INITIATOR_DET_ERR: /* 0x05 I->T only */
2082 case MSG_ABORT: /* 0x06 I->T only */
2083 case MSG_PARITY_ERROR: /* 0x09 I->T only */
2084 case MSG_LINK_CMD_COMPLETE: /* 0x0a */
2085 case MSG_LINK_CMD_COMPLETEF: /* 0x0b */
2086 case MSG_BUS_DEV_RESET: /* 0x0c I->T only */
2087 case MSG_ABORT_TAG: /* 0x0d I->T only */
2088 case MSG_CLEAR_QUEUE: /* 0x0e I->T only */
2089
2090 #if 0 /* handled above */
2091 case MSG_SIMPLE_Q_TAG: /* 0x20 */
2092 #endif
2093 case MSG_HEAD_OF_Q_TAG: /* 0x21 I->T only */
2094 case MSG_ORDERED_Q_TAG: /* 0x22 I->T only */
2095 case MSG_IGN_WIDE_RESIDUE: /* 0x23 */
2096
2097 default:
2098 #ifdef NJSC32_DEBUG
2099 PRINTC(cmd, ("msgin: unsupported msg: %#x", msg0));
2100 if (MSG_IS2BYTE(msg0))
2101 printf(" %#x", msg);
2102 printf("\n");
2103 #endif
2104 break;
2105 }
2106
2107 reject:
2108 njsc32_add_msgout(sc, MSG_MESSAGE_REJECT);
2109
2110 reply:
2111 msgout = njsc32_get_auto_msgout(sc);
2112
2113 restart:
2114 cctl = NJSC32_CMD_CLEAR_CDB_FIFO_PTR |
2115 NJSC32_CMD_AUTO_COMMAND_PHASE |
2116 NJSC32_CMD_AUTO_SCSI_RESTART;
2117
2118 /*
2119 * Be careful the second and latter bytes of Message In
2120 * shall not be absorbed by AutoSCSI.
2121 */
2122 if (sc->sc_msgincnt == 0)
2123 cctl |= NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02;
2124
2125 if (sc->sc_msgoutlen != 0)
2126 cctl |= NJSC32_CMD_AUTO_ATN;
2127
2128 njsc32_write_4(sc, NJSC32_REG_SCSI_MSG_OUT, msgout);
2129
2130 /* (re)start AutoSCSI (may assert ATN) */
2131 if (reload_params) {
2132 njsc32_cmd_reload(sc, cmd, cctl);
2133 } else {
2134 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl);
2135 }
2136
2137 /* +ATN -> -REQ: need 90ns delay? */
2138
2139 njsc32_wait_req_negate(sc); /* wait for REQ negation */
2140
2141 njsc32_negate_ack(sc);
2142
2143 return;
2144 }
2145
2146 static void
2147 njsc32_msgout(struct njsc32_softc *sc)
2148 {
2149 int cctl;
2150 u_int8_t bus;
2151 unsigned n;
2152
2153 if (sc->sc_msgoutlen == 0) {
2154 /* target entered to Message Out on unexpected timing */
2155 njsc32_add_msgout(sc, MSG_NOOP);
2156 }
2157
2158 cctl = NJSC32_CMD_CLEAR_CDB_FIFO_PTR |
2159 NJSC32_CMD_AUTO_COMMAND_PHASE | NJSC32_CMD_AUTO_SCSI_RESTART |
2160 NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02;
2161
2162 /* make sure target is in Message Out phase */
2163 bus = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR);
2164 if ((bus & NJSC32_BUSMON_PHASE_MASK) != NJSC32_PHASE_MESSAGE_OUT) {
2165 /*
2166 * Message Out is aborted by target.
2167 */
2168 printf("%s: njsc32_msgout: phase change %#x\n",
2169 sc->sc_dev.dv_xname, bus);
2170
2171 /* XXX what to do? */
2172
2173 /* restart AutoSCSI (negate ATN) */
2174 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl);
2175
2176 sc->sc_msgoutidx = 0;
2177 return;
2178 }
2179
2180 n = sc->sc_msgoutidx;
2181 if (n == sc->sc_msgoutlen - 1) {
2182 /*
2183 * negate ATN before sending ACK
2184 */
2185 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 0);
2186
2187 sc->sc_msgoutidx = 0; /* target may retry Message Out */
2188 } else {
2189 cctl |= NJSC32_CMD_AUTO_ATN;
2190 sc->sc_msgoutidx++;
2191 }
2192
2193 /* Send Message Out */
2194 njsc32_write_1(sc, NJSC32_REG_SCSI_OUT_LATCH, sc->sc_msgout[n]);
2195
2196 /* DBn -> +ACK: need 55ns delay? */
2197
2198 njsc32_assert_ack(sc);
2199 njsc32_wait_req_negate(sc); /* wait for REQ negation */
2200
2201 /* restart AutoSCSI */
2202 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl);
2203
2204 njsc32_negate_ack(sc);
2205
2206 /*
2207 * do not reset sc->sc_msgoutlen so the target
2208 * can retry Message Out phase
2209 */
2210 }
2211
2212 static void
2213 njsc32_cmdtimeout(void *arg)
2214 {
2215 struct njsc32_cmd *cmd = arg;
2216 struct njsc32_softc *sc;
2217 int s;
2218
2219 PRINTC(cmd, ("command timeout\n"));
2220
2221 sc = cmd->c_sc;
2222
2223 s = splbio();
2224
2225 if (sc->sc_stat == NJSC32_STAT_ARBIT)
2226 njsc32_arbitration_failed(sc);
2227 else {
2228 sc->sc_curcmd = NULL;
2229 sc->sc_stat = NJSC32_STAT_IDLE;
2230 njsc32_end_cmd(sc, cmd, XS_TIMEOUT);
2231 }
2232
2233 /* XXX? */
2234 njsc32_init(sc, 1); /* bus reset */
2235
2236 splx(s);
2237 }
2238
2239 static void
2240 njsc32_reseltimeout(void *arg)
2241 {
2242 struct njsc32_cmd *cmd = arg;
2243 struct njsc32_softc *sc;
2244 int s;
2245
2246 PRINTC(cmd, ("reselection timeout\n"));
2247
2248 sc = cmd->c_sc;
2249
2250 s = splbio();
2251
2252 /* remove from disconnected list */
2253 if (cmd->c_flags & NJSC32_CMD_TAGGED) {
2254 /* I_T_L_Q */
2255 KASSERT(cmd->c_lu->lu_cmd == NULL);
2256 TAILQ_REMOVE(&cmd->c_lu->lu_q, cmd, c_q);
2257 } else {
2258 /* I_T_L */
2259 KASSERT(cmd->c_lu->lu_cmd == cmd);
2260 cmd->c_lu->lu_cmd = NULL;
2261 }
2262
2263 njsc32_end_cmd(sc, cmd, XS_TIMEOUT);
2264
2265 /* XXX? */
2266 njsc32_init(sc, 1); /* bus reset */
2267
2268 splx(s);
2269 }
2270
2271 static inline void
2272 njsc32_end_auto(struct njsc32_softc *sc, struct njsc32_cmd *cmd, int auto_phase)
2273 {
2274 struct scsipi_xfer *xs;
2275
2276 if (auto_phase & NJSC32_XPHASE_MSGIN_02) {
2277 /* Message In: 0x02 Save Data Pointer */
2278
2279 /*
2280 * Adjust saved data pointer
2281 * if the command is not completed yet.
2282 */
2283 if ((auto_phase & NJSC32_XPHASE_MSGIN_00) == 0 &&
2284 (auto_phase &
2285 (NJSC32_XPHASE_DATA_IN | NJSC32_XPHASE_DATA_OUT)) != 0) {
2286 njsc32_save_ptr(cmd);
2287 }
2288 TPRINTF(("BM %u, SGT %u, SACK %u, SAVED_ACK %u\n",
2289 njsc32_read_4(sc, NJSC32_REG_BM_CNT),
2290 njsc32_read_4(sc, NJSC32_REG_SGT_ADR),
2291 njsc32_read_4(sc, NJSC32_REG_SACK_CNT),
2292 njsc32_read_4(sc, NJSC32_REG_SAVED_ACK_CNT)));
2293 }
2294
2295 xs = cmd->c_xs;
2296
2297 if (auto_phase & NJSC32_XPHASE_MSGIN_00) {
2298 /* Command Complete */
2299 TPRINTC(cmd, ("njsc32_intr: Command Complete\n"));
2300 switch (xs->status) {
2301 case SCSI_CHECK: case SCSI_QUEUE_FULL: case SCSI_BUSY:
2302 /*
2303 * scsipi layer will automatically handle the error
2304 */
2305 njsc32_end_cmd(sc, cmd, XS_BUSY);
2306 break;
2307 default:
2308 xs->resid -= cmd->c_dp_max;
2309 njsc32_end_cmd(sc, cmd, XS_NOERROR);
2310 break;
2311 }
2312 } else if (auto_phase & NJSC32_XPHASE_MSGIN_04) {
2313 /* Disconnect */
2314 TPRINTC(cmd, ("njsc32_intr: Disconnect\n"));
2315
2316 /* for ill-designed devices */
2317 if ((xs->xs_periph->periph_quirks & PQUIRK_AUTOSAVE) != 0)
2318 njsc32_save_ptr(cmd);
2319
2320 /*
2321 * move current cmd to disconnected list
2322 */
2323 if (cmd->c_flags & NJSC32_CMD_TAGGED) {
2324 /* I_T_L_Q */
2325 if (cmd->c_flags & NJSC32_CMD_TAGGED_HEAD)
2326 TAILQ_INSERT_HEAD(&cmd->c_lu->lu_q, cmd, c_q);
2327 else
2328 TAILQ_INSERT_TAIL(&cmd->c_lu->lu_q, cmd, c_q);
2329 } else {
2330 /* I_T_L */
2331 cmd->c_lu->lu_cmd = cmd;
2332 }
2333
2334 /*
2335 * schedule timeout -- avoid being
2336 * disconnected forever
2337 */
2338 if ((xs->xs_control & XS_CTL_POLL) == 0) {
2339 callout_stop(&xs->xs_callout);
2340 callout_reset(&xs->xs_callout, mstohz(xs->timeout),
2341 njsc32_reseltimeout, cmd);
2342 }
2343
2344 } else {
2345 /*
2346 * target has come to Bus Free phase
2347 * probably to notify an error
2348 */
2349 PRINTC(cmd, ("njsc32_intr: unexpected bus free\n"));
2350 /* try Request Sense */
2351 xs->status = SCSI_CHECK;
2352 njsc32_end_cmd(sc, cmd, XS_BUSY);
2353 }
2354 }
2355
2356 int
2357 njsc32_intr(void *arg)
2358 {
2359 struct njsc32_softc *sc = arg;
2360 u_int16_t intr;
2361 u_int8_t arbstat, bus_phase;
2362 int auto_phase;
2363 int idbit;
2364 struct njsc32_cmd *cmd;
2365
2366 intr = njsc32_read_2(sc, NJSC32_REG_IRQ);
2367 if ((intr & NJSC32_IRQ_INTR_PENDING) == 0)
2368 return 0; /* not mine */
2369
2370 TPRINTF(("%s: njsc32_intr: %#x\n", sc->sc_dev.dv_xname, intr));
2371
2372 #if 0 /* I don't think this is required */
2373 /* mask interrupts */
2374 njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL);
2375 #endif
2376
2377 /* we got an interrupt, so stop the timer */
2378 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP);
2379
2380 if (intr & NJSC32_IRQ_SCSIRESET) {
2381 printf("%s: detected bus reset\n", sc->sc_dev.dv_xname);
2382 /* make sure all devices on the bus are certainly reset */
2383 njsc32_reset_bus(sc);
2384 goto out;
2385 }
2386
2387 if (sc->sc_stat == NJSC32_STAT_ARBIT) {
2388 cmd = sc->sc_curcmd;
2389 KASSERT(cmd);
2390 arbstat = njsc32_read_1(sc, NJSC32_REG_ARBITRATION_STAT);
2391 if (arbstat & (NJSC32_ARBSTAT_WIN | NJSC32_ARBSTAT_FAIL)) {
2392 /*
2393 * arbitration done
2394 */
2395 /* clear arbitration status */
2396 njsc32_write_1(sc, NJSC32_REG_SET_ARBITRATION,
2397 NJSC32_SETARB_CLEAR);
2398
2399 if (arbstat & NJSC32_ARBSTAT_WIN) {
2400 TPRINTC(cmd,
2401 ("njsc32_intr: arbitration won\n"));
2402
2403 TAILQ_REMOVE(&sc->sc_reqcmd, cmd, c_q);
2404
2405 sc->sc_stat = NJSC32_STAT_CONNECT;
2406 } else {
2407 TPRINTC(cmd,
2408 ("njsc32_intr: arbitration failed\n"));
2409
2410 njsc32_arbitration_failed(sc);
2411
2412 /* XXX delay */
2413 /* XXX retry counter */
2414 }
2415 }
2416 }
2417
2418 if (intr & NJSC32_IRQ_TIMER) {
2419 TPRINTF(("%s: njsc32_intr: timer interrupt\n",
2420 sc->sc_dev.dv_xname));
2421 }
2422
2423 if (intr & NJSC32_IRQ_RESELECT) {
2424 /* Reselection from a target */
2425 njsc32_arbitration_failed(sc); /* just in case */
2426 if ((cmd = sc->sc_curcmd) != NULL) {
2427 /* ? */
2428 printf("%s: unexpected reselection\n",
2429 sc->sc_dev.dv_xname);
2430 sc->sc_curcmd = NULL;
2431 sc->sc_stat = NJSC32_STAT_IDLE;
2432 njsc32_end_cmd(sc, cmd, XS_DRIVER_STUFFUP);
2433 }
2434
2435 idbit = njsc32_read_1(sc, NJSC32_REG_RESELECT_ID);
2436 if ((idbit & (1 << NJSC32_INITIATOR_ID)) == 0 ||
2437 (sc->sc_reselid =
2438 ffs(idbit & ~(1 << NJSC32_INITIATOR_ID)) - 1) < 0) {
2439 printf("%s: invalid reselection (id: %#x)\n",
2440 sc->sc_dev.dv_xname, idbit);
2441 sc->sc_stat = NJSC32_STAT_IDLE; /* XXX ? */
2442 } else {
2443 sc->sc_stat = NJSC32_STAT_RESEL;
2444 TPRINTF(("%s: njsc32_intr: reselection from %d\n",
2445 sc->sc_dev.dv_xname, sc->sc_reselid));
2446 }
2447 }
2448
2449 if (intr & NJSC32_IRQ_PHASE_CHANGE) {
2450 #if 1 /* XXX probably not needed */
2451 if (sc->sc_stat == NJSC32_STAT_ARBIT)
2452 PRINTC(sc->sc_curcmd,
2453 ("njsc32_intr: cancel arbitration phase\n"));
2454 njsc32_arbitration_failed(sc);
2455 #endif
2456 /* current bus phase */
2457 bus_phase = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) &
2458 NJSC32_BUSMON_PHASE_MASK;
2459
2460 switch (bus_phase) {
2461 case NJSC32_PHASE_MESSAGE_IN:
2462 njsc32_msgin(sc);
2463 break;
2464
2465 /*
2466 * target may suddenly become Status / Bus Free phase
2467 * to notify an error condition
2468 */
2469 case NJSC32_PHASE_STATUS:
2470 printf("%s: unexpected bus phase: Status\n",
2471 sc->sc_dev.dv_xname);
2472 if ((cmd = sc->sc_curcmd) != NULL) {
2473 cmd->c_xs->status =
2474 njsc32_read_1(sc, NJSC32_REG_SCSI_CSB_IN);
2475 TPRINTC(cmd, ("njsc32_intr: Status %d\n",
2476 cmd->c_xs->status));
2477 }
2478 break;
2479 case NJSC32_PHASE_BUSFREE:
2480 printf("%s: unexpected bus phase: Bus Free\n",
2481 sc->sc_dev.dv_xname);
2482 if ((cmd = sc->sc_curcmd) != NULL) {
2483 sc->sc_curcmd = NULL;
2484 sc->sc_stat = NJSC32_STAT_IDLE;
2485 if (cmd->c_xs->status != SCSI_QUEUE_FULL &&
2486 cmd->c_xs->status != SCSI_BUSY)
2487 cmd->c_xs->status = SCSI_CHECK;/* XXX */
2488 njsc32_end_cmd(sc, cmd, XS_BUSY);
2489 }
2490 goto out;
2491 default:
2492 #ifdef NJSC32_DEBUG
2493 printf("%s: unexpected bus phase: ",
2494 sc->sc_dev.dv_xname);
2495 switch (bus_phase) {
2496 case NJSC32_PHASE_COMMAND:
2497 printf("Command\n"); break;
2498 case NJSC32_PHASE_MESSAGE_OUT:
2499 printf("Message Out\n");break;
2500 case NJSC32_PHASE_DATA_IN:
2501 printf("Data In\n"); break;
2502 case NJSC32_PHASE_DATA_OUT:
2503 printf("Data Out\n"); break;
2504 case NJSC32_PHASE_RESELECT:
2505 printf("Reselect\n");break;
2506 default: printf("%#x\n", bus_phase); break;
2507 }
2508 #else
2509 printf("%s: unexpected bus phase: %#x",
2510 sc->sc_dev.dv_xname, bus_phase);
2511 #endif
2512 break;
2513 }
2514 }
2515
2516 if (intr & NJSC32_IRQ_AUTOSCSI) {
2517 /*
2518 * AutoSCSI interrupt
2519 */
2520 auto_phase = njsc32_read_2(sc, NJSC32_REG_EXECUTE_PHASE);
2521 TPRINTF(("%s: njsc32_intr: AutoSCSI: %#x\n",
2522 sc->sc_dev.dv_xname, auto_phase));
2523 njsc32_write_2(sc, NJSC32_REG_EXECUTE_PHASE, 0);
2524
2525 if (auto_phase & NJSC32_XPHASE_SEL_TIMEOUT) {
2526 cmd = sc->sc_curcmd;
2527 if (cmd == NULL) {
2528 printf("%s: sel no cmd\n",
2529 sc->sc_dev.dv_xname);
2530 goto out;
2531 }
2532 DPRINTC(cmd, ("njsc32_intr: selection timeout\n"));
2533
2534 sc->sc_curcmd = NULL;
2535 sc->sc_stat = NJSC32_STAT_IDLE;
2536 njsc32_end_cmd(sc, cmd, XS_SELTIMEOUT);
2537
2538 goto out;
2539 }
2540
2541 #ifdef NJSC32_TRACE
2542 if (auto_phase & NJSC32_XPHASE_COMMAND) {
2543 /* Command phase has been automatically processed */
2544 TPRINTF(("%s: njsc32_intr: Command\n",
2545 sc->sc_dev.dv_xname));
2546 }
2547 #endif
2548 #ifdef NJSC32_DEBUG
2549 if (auto_phase & NJSC32_XPHASE_ILLEGAL) {
2550 printf("%s: njsc32_intr: Illegal phase\n",
2551 sc->sc_dev.dv_xname);
2552 }
2553 #endif
2554
2555 if (auto_phase & NJSC32_XPHASE_PAUSED_MSG_IN) {
2556 TPRINTF(("%s: njsc32_intr: Process Message In\n",
2557 sc->sc_dev.dv_xname));
2558 njsc32_msgin(sc);
2559 }
2560
2561 if (auto_phase & NJSC32_XPHASE_PAUSED_MSG_OUT) {
2562 TPRINTF(("%s: njsc32_intr: Process Message Out\n",
2563 sc->sc_dev.dv_xname));
2564 njsc32_msgout(sc);
2565 }
2566
2567 cmd = sc->sc_curcmd;
2568 if (cmd == NULL) {
2569 TPRINTF(("%s: njsc32_intr: no cmd\n",
2570 sc->sc_dev.dv_xname));
2571 goto out;
2572 }
2573
2574 if (auto_phase &
2575 (NJSC32_XPHASE_DATA_IN | NJSC32_XPHASE_DATA_OUT)) {
2576 u_int32_t sackcnt, cntoffset;
2577
2578 #ifdef NJSC32_TRACE
2579 if (auto_phase & NJSC32_XPHASE_DATA_IN)
2580 PRINTC(cmd, ("njsc32_intr: data in done\n"));
2581 if (auto_phase & NJSC32_XPHASE_DATA_OUT)
2582 PRINTC(cmd, ("njsc32_intr: data out done\n"));
2583 printf("BM %u, SGT %u, SACK %u, SAVED_ACK %u\n",
2584 njsc32_read_4(sc, NJSC32_REG_BM_CNT),
2585 njsc32_read_4(sc, NJSC32_REG_SGT_ADR),
2586 njsc32_read_4(sc, NJSC32_REG_SACK_CNT),
2587 njsc32_read_4(sc, NJSC32_REG_SAVED_ACK_CNT));
2588 #endif
2589
2590 /*
2591 * detected parity error on data transfer?
2592 */
2593 if (njsc32_read_1(sc, NJSC32_REG_PARITY_STATUS) &
2594 (NJSC32_PARITYSTATUS_ERROR_LSB|
2595 NJSC32_PARITYSTATUS_ERROR_MSB)) {
2596
2597 PRINTC(cmd, ("datain: parity error\n"));
2598
2599 /* clear parity error */
2600 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL,
2601 NJSC32_PARITYCTL_CHECK_ENABLE |
2602 NJSC32_PARITYCTL_CLEAR_ERROR);
2603
2604 if (auto_phase & NJSC32_XPHASE_BUS_FREE) {
2605 /*
2606 * XXX command has already finished
2607 * -- what can we do?
2608 *
2609 * It is not clear current command
2610 * caused the error -- reset everything.
2611 */
2612 njsc32_init(sc, 1); /* XXX */
2613 } else {
2614 /* XXX does this case occur? */
2615 #if 1
2616 printf("%s: datain: parity error\n",
2617 sc->sc_dev.dv_xname);
2618 #endif
2619 /*
2620 * Make attention condition and try
2621 * to send Initiator Detected Error
2622 * message.
2623 */
2624 njsc32_init_msgout(sc);
2625 njsc32_add_msgout(sc,
2626 MSG_INITIATOR_DET_ERR);
2627 njsc32_write_4(sc,
2628 NJSC32_REG_SCSI_MSG_OUT,
2629 njsc32_get_auto_msgout(sc));
2630 /* restart autoscsi with ATN */
2631 njsc32_write_2(sc,
2632 NJSC32_REG_COMMAND_CONTROL,
2633 NJSC32_CMD_CLEAR_CDB_FIFO_PTR |
2634 NJSC32_CMD_AUTO_COMMAND_PHASE |
2635 NJSC32_CMD_AUTO_SCSI_RESTART |
2636 NJSC32_CMD_AUTO_MSGIN_00_04 |
2637 NJSC32_CMD_AUTO_MSGIN_02 |
2638 NJSC32_CMD_AUTO_ATN);
2639 }
2640 goto out;
2641 }
2642
2643 /*
2644 * data has been transferred, and current pointer
2645 * is changed
2646 */
2647 sackcnt = njsc32_read_4(sc, NJSC32_REG_SACK_CNT);
2648
2649 /*
2650 * The controller returns extra ACK count
2651 * if the DMA buffer is not 4byte aligned.
2652 */
2653 cntoffset = le32toh(cmd->c_sgt[0].sg_addr) & 3;
2654 #ifdef NJSC32_DEBUG
2655 if (cntoffset != 0) {
2656 printf("sackcnt %u, cntoffset %u\n",
2657 sackcnt, cntoffset);
2658 }
2659 #endif
2660 /* advance SCSI pointer */
2661 njsc32_set_cur_ptr(cmd,
2662 cmd->c_dp_cur + sackcnt - cntoffset);
2663 }
2664
2665 if (auto_phase & NJSC32_XPHASE_MSGOUT) {
2666 /* Message Out phase has been automatically processed */
2667 TPRINTC(cmd, ("njsc32_intr: Message Out\n"));
2668 if ((auto_phase & NJSC32_XPHASE_PAUSED_MSG_IN) == 0 &&
2669 sc->sc_msgoutlen <= NJSC32_MSGOUT_MAX_AUTO) {
2670 njsc32_init_msgout(sc);
2671 }
2672 }
2673
2674 if (auto_phase & NJSC32_XPHASE_STATUS) {
2675 /* Status phase has been automatically processed */
2676 cmd->c_xs->status =
2677 njsc32_read_1(sc, NJSC32_REG_SCSI_CSB_IN);
2678 TPRINTC(cmd, ("njsc32_intr: Status %#x\n",
2679 cmd->c_xs->status));
2680 }
2681
2682 if (auto_phase & NJSC32_XPHASE_BUS_FREE) {
2683 /* AutoSCSI is finished */
2684
2685 TPRINTC(cmd, ("njsc32_intr: Bus Free\n"));
2686
2687 sc->sc_stat = NJSC32_STAT_IDLE;
2688 sc->sc_curcmd = NULL;
2689
2690 njsc32_end_auto(sc, cmd, auto_phase);
2691 }
2692 goto out;
2693 }
2694
2695 if (intr & NJSC32_IRQ_FIFO_THRESHOLD) {
2696 /* XXX We use DMA, and this shouldn't happen */
2697 printf("%s: njsc32_intr: FIFO\n", sc->sc_dev.dv_xname);
2698 njsc32_init(sc, 1);
2699 goto out;
2700 }
2701 if (intr & NJSC32_IRQ_PCI) {
2702 /* XXX? */
2703 printf("%s: njsc32_intr: PCI\n", sc->sc_dev.dv_xname);
2704 }
2705 if (intr & NJSC32_IRQ_BMCNTERR) {
2706 /* XXX? */
2707 printf("%s: njsc32_intr: BM\n", sc->sc_dev.dv_xname);
2708 }
2709
2710 out:
2711 /* go next command if controller is idle */
2712 if (sc->sc_stat == NJSC32_STAT_IDLE)
2713 njsc32_start(sc);
2714
2715 #if 0
2716 /* enable interrupts */
2717 njsc32_write_2(sc, NJSC32_REG_IRQ, 0);
2718 #endif
2719
2720 return 1; /* processed */
2721 }
Cache object: 6bf08cd4923724306f97d4f3db8afa63
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