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sys/dev/ic/ninjascsi32.c
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1 /* $NetBSD: ninjascsi32.c,v 1.18 2008/07/09 19:08:44 joerg Exp $ */ 2 3 /*- 4 * Copyright (c) 2004, 2006, 2007 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by ITOH Yasufumi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: ninjascsi32.c,v 1.18 2008/07/09 19:08:44 joerg Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/callout.h> 38 #include <sys/device.h> 39 #include <sys/kernel.h> 40 #include <sys/buf.h> 41 #include <sys/scsiio.h> 42 #include <sys/proc.h> 43 44 #include <sys/bus.h> 45 #include <sys/intr.h> 46 47 #include <uvm/uvm_extern.h> 48 49 #include <dev/scsipi/scsi_all.h> 50 #include <dev/scsipi/scsipi_all.h> 51 #include <dev/scsipi/scsiconf.h> 52 #include <dev/scsipi/scsi_message.h> 53 54 /* 55 * DualEdge transfer support 56 */ 57 /* #define NJSC32_DUALEDGE */ /* XXX untested */ 58 59 /* 60 * Auto param loading does not work properly (it partially works (works on 61 * start, doesn't on restart) on rev 0x54, it doesn't work at all on rev 0x51), 62 * and it doesn't improve the performance so much, 63 * forget about it. 64 */ 65 #undef NJSC32_AUTOPARAM 66 67 #include <dev/ic/ninjascsi32reg.h> 68 #include <dev/ic/ninjascsi32var.h> 69 70 /* #define NJSC32_DEBUG */ 71 /* #define NJSC32_TRACE */ 72 73 #ifdef NJSC32_DEBUG 74 #define DPRINTF(x) printf x 75 #define DPRINTC(cmd, x) PRINTC(cmd, x) 76 #else 77 #define DPRINTF(x) 78 #define DPRINTC(cmd, x) 79 #endif 80 #ifdef NJSC32_TRACE 81 #define TPRINTF(x) printf x 82 #define TPRINTC(cmd, x) PRINTC(cmd, x) 83 #else 84 #define TPRINTF(x) 85 #define TPRINTC(cmd, x) 86 #endif 87 88 #define PRINTC(cmd, x) do { \ 89 scsi_print_addr((cmd)->c_xs->xs_periph); \ 90 printf x; \ 91 } while (/* CONSTCOND */ 0) 92 93 static void njsc32_scsipi_request(struct scsipi_channel *, 94 scsipi_adapter_req_t, void *); 95 static void njsc32_scsipi_minphys(struct buf *); 96 static int njsc32_scsipi_ioctl(struct scsipi_channel *, u_long, void *, 97 int, struct proc *); 98 99 static void njsc32_init(struct njsc32_softc *, int nosleep); 100 static int njsc32_init_cmds(struct njsc32_softc *); 101 static void njsc32_target_async(struct njsc32_softc *, 102 struct njsc32_target *); 103 static void njsc32_init_targets(struct njsc32_softc *); 104 static void njsc32_add_msgout(struct njsc32_softc *, int); 105 static u_int32_t njsc32_get_auto_msgout(struct njsc32_softc *); 106 #ifdef NJSC32_DUALEDGE 107 static void njsc32_msgout_wdtr(struct njsc32_softc *, int); 108 #endif 109 static void njsc32_msgout_sdtr(struct njsc32_softc *, int period, 110 int offset); 111 static void njsc32_negotiate_xfer(struct njsc32_softc *, 112 struct njsc32_target *); 113 static void njsc32_arbitration_failed(struct njsc32_softc *); 114 static void njsc32_start(struct njsc32_softc *); 115 static void njsc32_run_xfer(struct njsc32_softc *, struct scsipi_xfer *); 116 static void njsc32_end_cmd(struct njsc32_softc *, struct njsc32_cmd *, 117 scsipi_xfer_result_t); 118 static void njsc32_wait_reset_release(void *); 119 static void njsc32_reset_bus(struct njsc32_softc *); 120 static void njsc32_clear_cmds(struct njsc32_softc *, 121 scsipi_xfer_result_t); 122 static void njsc32_set_ptr(struct njsc32_softc *, struct njsc32_cmd *, 123 u_int32_t); 124 static void njsc32_assert_ack(struct njsc32_softc *); 125 static void njsc32_negate_ack(struct njsc32_softc *); 126 static void njsc32_wait_req_negate(struct njsc32_softc *); 127 static void njsc32_reconnect(struct njsc32_softc *, struct njsc32_cmd *); 128 enum njsc32_reselstat { 129 NJSC32_RESEL_ERROR, /* to be rejected */ 130 NJSC32_RESEL_COMPLETE, /* reselection is just complete */ 131 NJSC32_RESEL_THROUGH /* this message is OK (no reply) */ 132 }; 133 static enum njsc32_reselstat njsc32_resel_identify(struct njsc32_softc *, 134 int lun, struct njsc32_cmd **); 135 static enum njsc32_reselstat njsc32_resel_tag(struct njsc32_softc *, 136 int tag, struct njsc32_cmd **); 137 static void njsc32_cmd_reload(struct njsc32_softc *, struct njsc32_cmd *, 138 int); 139 static void njsc32_update_xfer_mode(struct njsc32_softc *, 140 struct njsc32_target *); 141 static void njsc32_msgin(struct njsc32_softc *); 142 static void njsc32_msgout(struct njsc32_softc *); 143 static void njsc32_cmdtimeout(void *); 144 static void njsc32_reseltimeout(void *); 145 146 static inline unsigned 147 njsc32_read_1(struct njsc32_softc *sc, int no) 148 { 149 150 return bus_space_read_1(sc->sc_regt, sc->sc_regh, no); 151 } 152 153 static inline unsigned 154 njsc32_read_2(struct njsc32_softc *sc, int no) 155 { 156 157 return bus_space_read_2(sc->sc_regt, sc->sc_regh, no); 158 } 159 160 static inline u_int32_t 161 njsc32_read_4(struct njsc32_softc *sc, int no) 162 { 163 164 return bus_space_read_4(sc->sc_regt, sc->sc_regh, no); 165 } 166 167 static inline void 168 njsc32_write_1(struct njsc32_softc *sc, int no, int val) 169 { 170 171 bus_space_write_1(sc->sc_regt, sc->sc_regh, no, val); 172 } 173 174 static inline void 175 njsc32_write_2(struct njsc32_softc *sc, int no, int val) 176 { 177 178 bus_space_write_2(sc->sc_regt, sc->sc_regh, no, val); 179 } 180 181 static inline void 182 njsc32_write_4(struct njsc32_softc *sc, int no, u_int32_t val) 183 { 184 185 bus_space_write_4(sc->sc_regt, sc->sc_regh, no, val); 186 } 187 188 static inline unsigned 189 njsc32_ireg_read_1(struct njsc32_softc *sc, int no) 190 { 191 192 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 193 return bus_space_read_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW); 194 } 195 196 static inline unsigned 197 njsc32_ireg_read_2(struct njsc32_softc *sc, int no) 198 { 199 200 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 201 return bus_space_read_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW); 202 } 203 204 static inline u_int32_t 205 njsc32_ireg_read_4(struct njsc32_softc *sc, int no) 206 { 207 u_int32_t val; 208 209 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 210 val = (u_int16_t)bus_space_read_2(sc->sc_regt, sc->sc_regh, 211 NJSC32_REG_DATA_LOW); 212 return val | (bus_space_read_2(sc->sc_regt, sc->sc_regh, 213 NJSC32_REG_DATA_HIGH) << 16); 214 } 215 216 static inline void 217 njsc32_ireg_write_1(struct njsc32_softc *sc, int no, int val) 218 { 219 220 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 221 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val); 222 } 223 224 static inline void 225 njsc32_ireg_write_2(struct njsc32_softc *sc, int no, int val) 226 { 227 228 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 229 bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val); 230 } 231 232 static inline void 233 njsc32_ireg_write_4(struct njsc32_softc *sc, int no, u_int32_t val) 234 { 235 236 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no); 237 bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val); 238 bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_HIGH, 239 val >> 16); 240 } 241 242 #define NS(ns) ((ns) / 4) /* nanosecond (>= 50) -> sync value */ 243 #ifdef __STDC__ 244 # define ACKW(n) NJSC32_ACK_WIDTH_ ## n ## CLK 245 # define SMPL(n) (NJSC32_SREQ_SAMPLING_ ## n ## CLK | \ 246 NJSC32_SREQ_SAMPLING_ENABLE) 247 #else 248 # define ACKW(n) NJSC32_ACK_WIDTH_/**/n/**/CLK 249 # define SMPL(n) (NJSC32_SREQ_SAMPLING_/**/n/**/CLK | \ 250 NJSC32_SREQ_SAMPLING_ENABLE) 251 #endif 252 253 #define NJSC32_NSYNCT_MAXSYNC 1 254 #define NJSC32_NSYNCT 16 255 256 /* 40MHz (25ns) */ 257 static const struct njsc32_sync_param njsc32_synct_40M[NJSC32_NSYNCT] = { 258 { 0, 0, 0 }, /* dummy for async */ 259 { NS( 50), ACKW(1), 0 }, /* 20.0 : 50ns, 25ns */ 260 { NS( 75), ACKW(1), SMPL(1) }, /* 13.3 : 75ns, 25ns */ 261 { NS(100), ACKW(2), SMPL(1) }, /* 10.0 : 100ns, 50ns */ 262 { NS(125), ACKW(2), SMPL(2) }, /* 8.0 : 125ns, 50ns */ 263 { NS(150), ACKW(3), SMPL(2) }, /* 6.7 : 150ns, 75ns */ 264 { NS(175), ACKW(3), SMPL(2) }, /* 5.7 : 175ns, 75ns */ 265 { NS(200), ACKW(4), SMPL(2) }, /* 5.0 : 200ns, 100ns */ 266 { NS(225), ACKW(4), SMPL(4) }, /* 4.4 : 225ns, 100ns */ 267 { NS(250), ACKW(4), SMPL(4) }, /* 4.0 : 250ns, 100ns */ 268 { NS(275), ACKW(4), SMPL(4) }, /* 3.64: 275ns, 100ns */ 269 { NS(300), ACKW(4), SMPL(4) }, /* 3.33: 300ns, 100ns */ 270 { NS(325), ACKW(4), SMPL(4) }, /* 3.01: 325ns, 100ns */ 271 { NS(350), ACKW(4), SMPL(4) }, /* 2.86: 350ns, 100ns */ 272 { NS(375), ACKW(4), SMPL(4) }, /* 2.67: 375ns, 100ns */ 273 { NS(400), ACKW(4), SMPL(4) } /* 2.50: 400ns, 100ns */ 274 }; 275 276 #ifdef NJSC32_SUPPORT_OTHER_CLOCKS 277 /* 20MHz (50ns) */ 278 static const struct njsc32_sync_param njsc32_synct_20M[NJSC32_NSYNCT] = { 279 { 0, 0, 0 }, /* dummy for async */ 280 { NS(100), ACKW(1), 0 }, /* 10.0 : 100ns, 50ns */ 281 { NS(150), ACKW(1), SMPL(2) }, /* 6.7 : 150ns, 50ns */ 282 { NS(200), ACKW(2), SMPL(2) }, /* 5.0 : 200ns, 100ns */ 283 { NS(250), ACKW(2), SMPL(4) }, /* 4.0 : 250ns, 100ns */ 284 { NS(300), ACKW(3), SMPL(4) }, /* 3.3 : 300ns, 150ns */ 285 { NS(350), ACKW(3), SMPL(4) }, /* 2.8 : 350ns, 150ns */ 286 { NS(400), ACKW(4), SMPL(4) }, /* 2.5 : 400ns, 200ns */ 287 { NS(450), ACKW(4), SMPL(4) }, /* 2.2 : 450ns, 200ns */ 288 { NS(500), ACKW(4), SMPL(4) }, /* 2.0 : 500ns, 200ns */ 289 { NS(550), ACKW(4), SMPL(4) }, /* 1.82: 550ns, 200ns */ 290 { NS(600), ACKW(4), SMPL(4) }, /* 1.67: 600ns, 200ns */ 291 { NS(650), ACKW(4), SMPL(4) }, /* 1.54: 650ns, 200ns */ 292 { NS(700), ACKW(4), SMPL(4) }, /* 1.43: 700ns, 200ns */ 293 { NS(750), ACKW(4), SMPL(4) }, /* 1.33: 750ns, 200ns */ 294 { NS(800), ACKW(4), SMPL(4) } /* 1.25: 800ns, 200ns */ 295 }; 296 297 /* 33.3MHz (30ns) */ 298 static const struct njsc32_sync_param njsc32_synct_pci[NJSC32_NSYNCT] = { 299 { 0, 0, 0 }, /* dummy for async */ 300 { NS( 60), ACKW(1), 0 }, /* 16.6 : 60ns, 30ns */ 301 { NS( 90), ACKW(1), SMPL(1) }, /* 11.1 : 90ns, 30ns */ 302 { NS(120), ACKW(2), SMPL(2) }, /* 8.3 : 120ns, 60ns */ 303 { NS(150), ACKW(2), SMPL(2) }, /* 6.7 : 150ns, 60ns */ 304 { NS(180), ACKW(3), SMPL(2) }, /* 5.6 : 180ns, 90ns */ 305 { NS(210), ACKW(3), SMPL(4) }, /* 4.8 : 210ns, 90ns */ 306 { NS(240), ACKW(4), SMPL(4) }, /* 4.2 : 240ns, 120ns */ 307 { NS(270), ACKW(4), SMPL(4) }, /* 3.7 : 270ns, 120ns */ 308 { NS(300), ACKW(4), SMPL(4) }, /* 3.3 : 300ns, 120ns */ 309 { NS(330), ACKW(4), SMPL(4) }, /* 3.0 : 330ns, 120ns */ 310 { NS(360), ACKW(4), SMPL(4) }, /* 2.8 : 360ns, 120ns */ 311 { NS(390), ACKW(4), SMPL(4) }, /* 2.6 : 390ns, 120ns */ 312 { NS(420), ACKW(4), SMPL(4) }, /* 2.4 : 420ns, 120ns */ 313 { NS(450), ACKW(4), SMPL(4) }, /* 2.2 : 450ns, 120ns */ 314 { NS(480), ACKW(4), SMPL(4) } /* 2.1 : 480ns, 120ns */ 315 }; 316 #endif /* NJSC32_SUPPORT_OTHER_CLOCKS */ 317 318 #undef NS 319 #undef ACKW 320 #undef SMPL 321 322 /* initialize device */ 323 static void 324 njsc32_init(struct njsc32_softc *sc, int nosleep) 325 { 326 u_int16_t intstat; 327 int i; 328 329 /* block all interrupts */ 330 njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL); 331 332 /* clear transfer */ 333 njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0); 334 njsc32_write_4(sc, NJSC32_REG_BM_CNT, 0); 335 336 /* make sure interrupts are cleared */ 337 for (i = 0; ((intstat = njsc32_read_2(sc, NJSC32_REG_IRQ)) 338 & NJSC32_IRQ_INTR_PENDING) && i < 5 /* just not forever */; i++) { 339 DPRINTF(("%s: njsc32_init: intr pending: %#x\n", 340 device_xname(sc->sc_dev), intstat)); 341 } 342 343 /* FIFO threshold */ 344 njsc32_ireg_write_1(sc, NJSC32_IREG_FIFO_THRESHOLD_FULL, 345 NJSC32_FIFO_FULL_BUSMASTER); 346 njsc32_ireg_write_1(sc, NJSC32_IREG_FIFO_THRESHOLD_EMPTY, 347 NJSC32_FIFO_EMPTY_BUSMASTER); 348 349 /* clock source */ 350 njsc32_ireg_write_1(sc, NJSC32_IREG_CLOCK, sc->sc_clk); 351 352 /* memory read multiple */ 353 njsc32_ireg_write_1(sc, NJSC32_IREG_BM, 354 NJSC32_BM_MEMRD_CMD1 | NJSC32_BM_SGT_AUTO_PARA_MEMRD_CMD); 355 356 /* clear parity error and enable parity detection */ 357 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 358 NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR); 359 360 /* misc configuration */ 361 njsc32_ireg_write_2(sc, NJSC32_IREG_MISC, 362 NJSC32_MISC_SCSI_DIRECTION_DETECTOR_SELECT | 363 NJSC32_MISC_DELAYED_BMSTART | 364 NJSC32_MISC_MASTER_TERMINATION_SELECT | 365 NJSC32_MISC_BMREQ_NEGATE_TIMING_SEL | 366 NJSC32_MISC_AUTOSEL_TIMING_SEL | 367 NJSC32_MISC_BMSTOP_CHANGE2_NONDATA_PHASE); 368 369 /* 370 * Check for termination power (32Bi and some versions of 32UDE). 371 */ 372 if (!nosleep || cold) { 373 DPRINTF(("%s: njsc32_init: checking TERMPWR\n", 374 device_xname(sc->sc_dev))); 375 376 /* First, turn termination power off */ 377 njsc32_ireg_write_1(sc, NJSC32_IREG_TERM_PWR, 0); 378 379 /* give 0.5s to settle */ 380 if (nosleep) 381 delay(500000); 382 else 383 tsleep(sc, PWAIT, "njs_t1", hz / 2); 384 } 385 386 /* supply termination power if not supplied by other devices */ 387 if ((njsc32_ireg_read_1(sc, NJSC32_IREG_TERM_PWR) & 388 NJSC32_TERMPWR_SENSE) == 0) { 389 /* termination power is not present on the bus */ 390 if (sc->sc_flags & NJSC32_CANNOT_SUPPLY_TERMPWR) { 391 /* 392 * CardBus device must not supply termination power 393 * to avoid excessive power consumption. 394 */ 395 printf("%s: no termination power present\n", 396 device_xname(sc->sc_dev)); 397 } else { 398 /* supply termination power */ 399 njsc32_ireg_write_1(sc, NJSC32_IREG_TERM_PWR, 400 NJSC32_TERMPWR_BPWR); 401 402 DPRINTF(("%s: supplying termination power\n", 403 device_xname(sc->sc_dev))); 404 405 /* give 0.5s to settle */ 406 if (!nosleep) 407 tsleep(sc, PWAIT, "njs_t2", hz / 2); 408 } 409 } 410 411 /* stop timer */ 412 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP); 413 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP); 414 415 /* default transfer parameter */ 416 njsc32_write_1(sc, NJSC32_REG_SYNC, 0); 417 njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, NJSC32_ACK_WIDTH_1CLK); 418 njsc32_write_2(sc, NJSC32_REG_SEL_TIMEOUT, 419 NJSC32_SEL_TIMEOUT_TIME); 420 421 /* select interrupt source */ 422 njsc32_ireg_write_2(sc, NJSC32_IREG_IRQ_SELECT, 423 NJSC32_IRQSEL_RESELECT | 424 NJSC32_IRQSEL_PHASE_CHANGE | 425 NJSC32_IRQSEL_SCSIRESET | 426 NJSC32_IRQSEL_TIMER | 427 NJSC32_IRQSEL_FIFO_THRESHOLD | 428 NJSC32_IRQSEL_TARGET_ABORT | 429 NJSC32_IRQSEL_MASTER_ABORT | 430 /* XXX not yet 431 NJSC32_IRQSEL_SERR | 432 NJSC32_IRQSEL_PERR | 433 NJSC32_IRQSEL_BMCNTERR | 434 */ 435 NJSC32_IRQSEL_AUTO_SCSI_SEQ); 436 437 /* interrupts will be unblocked later after bus reset */ 438 439 /* turn LED off */ 440 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT_DDR, 441 NJSC32_EXTPORT_LED_OFF); 442 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, 443 NJSC32_EXTPORT_LED_OFF); 444 445 /* reset SCSI bus so the targets become known state */ 446 njsc32_reset_bus(sc); 447 } 448 449 static int 450 njsc32_init_cmds(struct njsc32_softc *sc) 451 { 452 struct njsc32_cmd *cmd; 453 bus_addr_t dmaaddr; 454 int i, error; 455 456 /* 457 * allocate DMA area for command 458 */ 459 if ((error = bus_dmamem_alloc(sc->sc_dmat, 460 sizeof(struct njsc32_dma_page), PAGE_SIZE, 0, 461 &sc->sc_cmdpg_seg, 1, &sc->sc_cmdpg_nsegs, BUS_DMA_NOWAIT)) != 0) { 462 aprint_error_dev(sc->sc_dev, "unable to allocate cmd page, error = %d\n", 463 error); 464 return 0; 465 } 466 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmdpg_seg, 467 sc->sc_cmdpg_nsegs, sizeof(struct njsc32_dma_page), 468 (void **)&sc->sc_cmdpg, 469 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 470 aprint_error_dev(sc->sc_dev, "unable to map cmd page, error = %d\n", 471 error); 472 goto fail1; 473 } 474 if ((error = bus_dmamap_create(sc->sc_dmat, 475 sizeof(struct njsc32_dma_page), 1, 476 sizeof(struct njsc32_dma_page), 0, BUS_DMA_NOWAIT, 477 &sc->sc_dmamap_cmdpg)) != 0) { 478 aprint_error_dev(sc->sc_dev, "unable to create cmd DMA map, error = %d\n", 479 error); 480 goto fail2; 481 } 482 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_cmdpg, 483 sc->sc_cmdpg, sizeof(struct njsc32_dma_page), 484 NULL, BUS_DMA_NOWAIT)) != 0) { 485 aprint_error_dev(sc->sc_dev, "unable to load cmd DMA map, error = %d\n", 486 error); 487 goto fail3; 488 } 489 490 memset(sc->sc_cmdpg, 0, sizeof(struct njsc32_dma_page)); 491 dmaaddr = sc->sc_dmamap_cmdpg->dm_segs[0].ds_addr; 492 493 #ifdef NJSC32_AUTOPARAM 494 sc->sc_ap_dma = dmaaddr + offsetof(struct njsc32_dma_page, dp_ap); 495 #endif 496 497 for (i = 0; i < NJSC32_NUM_CMD; i++) { 498 cmd = &sc->sc_cmds[i]; 499 cmd->c_sc = sc; 500 cmd->c_sgt = sc->sc_cmdpg->dp_sg[i]; 501 cmd->c_sgt_dma = dmaaddr + 502 offsetof(struct njsc32_dma_page, dp_sg[i]); 503 cmd->c_flags = 0; 504 505 error = bus_dmamap_create(sc->sc_dmat, 506 NJSC32_MAX_XFER, /* max total map size */ 507 NJSC32_NUM_SG, /* max number of segments */ 508 NJSC32_SGT_MAXSEGLEN, /* max size of a segment */ 509 0, /* boundary */ 510 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &cmd->c_dmamap_xfer); 511 if (error) { 512 aprint_error_dev(sc->sc_dev, "only %d cmd descs available (error = %d)\n", 513 i, error); 514 break; 515 } 516 TAILQ_INSERT_TAIL(&sc->sc_freecmd, cmd, c_q); 517 } 518 519 if (i > 0) 520 return i; 521 522 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_cmdpg); 523 fail3: bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_cmdpg); 524 fail2: bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_cmdpg, 525 sizeof(struct njsc32_dma_page)); 526 fail1: bus_dmamem_free(sc->sc_dmat, &sc->sc_cmdpg_seg, sc->sc_cmdpg_nsegs); 527 528 return 0; 529 } 530 531 static void 532 njsc32_target_async(struct njsc32_softc *sc, struct njsc32_target *target) 533 { 534 535 target->t_sync = 536 NJSC32_SYNC_VAL(sc->sc_sync_max, NJSC32_SYNCOFFSET_ASYNC); 537 target->t_ackwidth = NJSC32_ACK_WIDTH_1CLK; 538 target->t_sample = 0; /* disable */ 539 target->t_syncoffset = NJSC32_SYNCOFFSET_ASYNC; 540 target->t_syncperiod = NJSC32_SYNCPERIOD_ASYNC; 541 } 542 543 static void 544 njsc32_init_targets(struct njsc32_softc *sc) 545 { 546 int id, lun; 547 struct njsc32_lu *lu; 548 549 for (id = 0; id <= NJSC32_MAX_TARGET_ID; id++) { 550 /* cancel negotiation status */ 551 sc->sc_targets[id].t_state = NJSC32_TARST_INIT; 552 553 /* default to async mode */ 554 njsc32_target_async(sc, &sc->sc_targets[id]); 555 556 #ifdef NJSC32_DUALEDGE 557 sc->sc_targets[id].t_xferctl = 0; 558 #endif 559 560 sc->sc_targets[id].t_targetid = 561 (1 << id) | (1 << NJSC32_INITIATOR_ID); 562 563 /* init logical units */ 564 for (lun = 0; lun < NJSC32_NLU; lun++) { 565 lu = &sc->sc_targets[id].t_lus[lun]; 566 lu->lu_cmd = NULL; 567 TAILQ_INIT(&lu->lu_q); 568 } 569 } 570 } 571 572 void 573 njsc32_attach(struct njsc32_softc *sc) 574 { 575 const char *str; 576 #if 1 /* test */ 577 int reg; 578 njsc32_model_t detected_model; 579 #endif 580 581 /* init */ 582 TAILQ_INIT(&sc->sc_freecmd); 583 TAILQ_INIT(&sc->sc_reqcmd); 584 callout_init(&sc->sc_callout, 0); 585 586 #if 1 /* test */ 587 /* 588 * try to distinguish 32Bi and 32UDE 589 */ 590 /* try to set DualEdge bit (exists on 32UDE only) and read it back */ 591 njsc32_write_2(sc, NJSC32_REG_TRANSFER, NJSC32_XFR_DUALEDGE_ENABLE); 592 if ((reg = njsc32_read_2(sc, NJSC32_REG_TRANSFER)) == 0xffff) { 593 /* device was removed? */ 594 aprint_error_dev(sc->sc_dev, "attach failed\n"); 595 return; 596 } else if (reg & NJSC32_XFR_DUALEDGE_ENABLE) { 597 detected_model = NJSC32_MODEL_32UDE | NJSC32_FLAG_DUALEDGE; 598 } else { 599 detected_model = NJSC32_MODEL_32BI; 600 } 601 njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0); /* restore */ 602 603 #if 1/*def DIAGNOSTIC*/ 604 /* compare what is configured with what is detected */ 605 if ((sc->sc_model & NJSC32_MODEL_MASK) != 606 (detected_model & NJSC32_MODEL_MASK)) { 607 /* 608 * Please report this error if it happens. 609 */ 610 aprint_error_dev(sc->sc_dev, "model mismatch: %#x vs %#x\n", 611 sc->sc_model, detected_model); 612 return; 613 } 614 #endif 615 #endif 616 617 /* check model */ 618 switch (sc->sc_model & NJSC32_MODEL_MASK) { 619 case NJSC32_MODEL_32BI: 620 str = "Bi"; 621 /* 32Bi doesn't support DualEdge transfer */ 622 KASSERT((sc->sc_model & NJSC32_FLAG_DUALEDGE) == 0); 623 break; 624 case NJSC32_MODEL_32UDE: 625 str = "UDE"; 626 break; 627 default: 628 aprint_error_dev(sc->sc_dev, "unknown model!\n"); 629 return; 630 } 631 aprint_normal_dev(sc->sc_dev, "NJSC-32%s", str); 632 633 switch (sc->sc_clk) { 634 default: 635 #ifdef DIAGNOSTIC 636 panic("njsc32_attach: unknown clk %d", sc->sc_clk); 637 #endif 638 case NJSC32_CLOCK_DIV_4: 639 sc->sc_synct = njsc32_synct_40M; 640 str = "40MHz"; 641 break; 642 #ifdef NJSC32_SUPPORT_OTHER_CLOCKS 643 case NJSC32_CLOCK_DIV_2: 644 sc->sc_synct = njsc32_synct_20M; 645 str = "20MHz"; 646 break; 647 case NJSC32_CLOCK_PCICLK: 648 sc->sc_synct = njsc32_synct_pci; 649 str = "PCI"; 650 break; 651 #endif 652 } 653 aprint_normal(", G/A rev %#x, clk %s%s\n", 654 NJSC32_INDEX_GAREV(njsc32_read_2(sc, NJSC32_REG_INDEX)), str, 655 (sc->sc_model & NJSC32_FLAG_DUALEDGE) ? 656 #ifdef NJSC32_DUALEDGE 657 ", DualEdge" 658 #else 659 ", DualEdge (no driver support)" 660 #endif 661 : ""); 662 663 /* allocate DMA resource */ 664 if ((sc->sc_ncmd = njsc32_init_cmds(sc)) == 0) { 665 aprint_error_dev(sc->sc_dev, "no usable DMA map\n"); 666 return; 667 } 668 sc->sc_flags |= NJSC32_CMDPG_MAPPED; 669 670 sc->sc_curcmd = NULL; 671 sc->sc_nusedcmds = 0; 672 673 sc->sc_sync_max = 1; /* XXX look up EEPROM configuration? */ 674 675 /* initialize hardware and target structure */ 676 njsc32_init(sc, cold); 677 678 /* setup adapter */ 679 sc->sc_adapter.adapt_dev = sc->sc_dev; 680 sc->sc_adapter.adapt_nchannels = 1; 681 sc->sc_adapter.adapt_request = njsc32_scsipi_request; 682 sc->sc_adapter.adapt_minphys = njsc32_scsipi_minphys; 683 sc->sc_adapter.adapt_ioctl = njsc32_scsipi_ioctl; 684 685 sc->sc_adapter.adapt_max_periph = sc->sc_adapter.adapt_openings = 686 sc->sc_ncmd; 687 688 /* setup channel */ 689 sc->sc_channel.chan_adapter = &sc->sc_adapter; 690 sc->sc_channel.chan_bustype = &scsi_bustype; 691 sc->sc_channel.chan_channel = 0; 692 sc->sc_channel.chan_ntargets = NJSC32_NTARGET; 693 sc->sc_channel.chan_nluns = NJSC32_NLU; 694 sc->sc_channel.chan_id = NJSC32_INITIATOR_ID; 695 696 sc->sc_scsi = config_found(sc->sc_dev, &sc->sc_channel, scsiprint); 697 } 698 699 int 700 njsc32_detach(struct njsc32_softc *sc, int flags) 701 { 702 int rv = 0; 703 int i, s; 704 struct njsc32_cmd *cmd; 705 706 callout_stop(&sc->sc_callout); 707 708 s = splbio(); 709 710 /* clear running/disconnected commands */ 711 njsc32_clear_cmds(sc, XS_DRIVER_STUFFUP); 712 713 sc->sc_stat = NJSC32_STAT_DETACH; 714 715 /* clear pending commands */ 716 while ((cmd = TAILQ_FIRST(&sc->sc_reqcmd)) != NULL) { 717 TAILQ_REMOVE(&sc->sc_reqcmd, cmd, c_q); 718 njsc32_end_cmd(sc, cmd, XS_RESET); 719 } 720 721 if (sc->sc_scsi != NULL) 722 rv = config_detach(sc->sc_scsi, flags); 723 724 splx(s); 725 726 /* free DMA resource */ 727 if (sc->sc_flags & NJSC32_CMDPG_MAPPED) { 728 for (i = 0; i < sc->sc_ncmd; i++) { 729 cmd = &sc->sc_cmds[i]; 730 if (cmd->c_flags & NJSC32_CMD_DMA_MAPPED) 731 bus_dmamap_unload(sc->sc_dmat, 732 cmd->c_dmamap_xfer); 733 bus_dmamap_destroy(sc->sc_dmat, cmd->c_dmamap_xfer); 734 } 735 736 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_cmdpg); 737 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_cmdpg); 738 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_cmdpg, 739 sizeof(struct njsc32_dma_page)); 740 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmdpg_seg, 741 sc->sc_cmdpg_nsegs); 742 } 743 744 return 0; 745 } 746 747 static inline void 748 njsc32_cmd_init(struct njsc32_cmd *cmd) 749 { 750 751 cmd->c_flags = 0; 752 753 /* scatter/gather table */ 754 cmd->c_sgtdmaaddr = NJSC32_CMD_DMAADDR_SGT(cmd, 0); 755 cmd->c_sgoffset = 0; 756 cmd->c_sgfixcnt = 0; 757 758 /* data pointer */ 759 cmd->c_dp_cur = cmd->c_dp_saved = cmd->c_dp_max = 0; 760 } 761 762 static inline void 763 njsc32_init_msgout(struct njsc32_softc *sc) 764 { 765 766 sc->sc_msgoutlen = 0; 767 sc->sc_msgoutidx = 0; 768 } 769 770 static void 771 njsc32_add_msgout(struct njsc32_softc *sc, int byte) 772 { 773 774 if (sc->sc_msgoutlen >= NJSC32_MSGOUT_LEN) { 775 printf("njsc32_add_msgout: too many\n"); 776 return; 777 } 778 sc->sc_msgout[sc->sc_msgoutlen++] = byte; 779 } 780 781 static u_int32_t 782 njsc32_get_auto_msgout(struct njsc32_softc *sc) 783 { 784 u_int32_t val; 785 u_int8_t *p; 786 787 val = 0; 788 p = sc->sc_msgout; 789 switch (sc->sc_msgoutlen) { 790 /* 31-24 23-16 15-8 7 ... 1 0 */ 791 case 3: /* MSG3 MSG2 MSG1 V --- cnt */ 792 val |= *p++ << NJSC32_MSGOUT_MSG1_SHIFT; 793 /* FALLTHROUGH */ 794 795 case 2: /* MSG2 MSG1 --- V --- cnt */ 796 val |= *p++ << NJSC32_MSGOUT_MSG2_SHIFT; 797 /* FALLTHROUGH */ 798 799 case 1: /* MSG1 --- --- V --- cnt */ 800 val |= *p++ << NJSC32_MSGOUT_MSG3_SHIFT; 801 val |= NJSC32_MSGOUT_VALID | sc->sc_msgoutlen; 802 break; 803 804 default: 805 break; 806 } 807 return val; 808 } 809 810 #ifdef NJSC32_DUALEDGE 811 /* add Wide Data Transfer Request to the next Message Out */ 812 static void 813 njsc32_msgout_wdtr(struct njsc32_softc *sc, int width) 814 { 815 816 njsc32_add_msgout(sc, MSG_EXTENDED); 817 njsc32_add_msgout(sc, MSG_EXT_WDTR_LEN); 818 njsc32_add_msgout(sc, MSG_EXT_WDTR); 819 njsc32_add_msgout(sc, width); 820 } 821 #endif 822 823 /* add Synchronous Data Transfer Request to the next Message Out */ 824 static void 825 njsc32_msgout_sdtr(struct njsc32_softc *sc, int period, int offset) 826 { 827 828 njsc32_add_msgout(sc, MSG_EXTENDED); 829 njsc32_add_msgout(sc, MSG_EXT_SDTR_LEN); 830 njsc32_add_msgout(sc, MSG_EXT_SDTR); 831 njsc32_add_msgout(sc, period); 832 njsc32_add_msgout(sc, offset); 833 } 834 835 static void 836 njsc32_negotiate_xfer(struct njsc32_softc *sc, struct njsc32_target *target) 837 { 838 839 /* initial negotiation state */ 840 if (target->t_state == NJSC32_TARST_INIT) { 841 #ifdef NJSC32_DUALEDGE 842 if (target->t_flags & NJSC32_TARF_DE) 843 target->t_state = NJSC32_TARST_DE; 844 else 845 #endif 846 if (target->t_flags & NJSC32_TARF_SYNC) 847 target->t_state = NJSC32_TARST_SDTR; 848 else 849 target->t_state = NJSC32_TARST_DONE; 850 } 851 852 switch (target->t_state) { 853 default: 854 case NJSC32_TARST_INIT: 855 #ifdef DIAGNOSTIC 856 panic("njsc32_negotiate_xfer"); 857 /* NOTREACHED */ 858 #endif 859 /* FALLTHROUGH */ 860 case NJSC32_TARST_DONE: 861 /* no more work */ 862 break; 863 864 #ifdef NJSC32_DUALEDGE 865 case NJSC32_TARST_DE: 866 njsc32_msgout_wdtr(sc, 0xde /* XXX? */); 867 break; 868 869 case NJSC32_TARST_WDTR: 870 njsc32_msgout_wdtr(sc, MSG_EXT_WDTR_BUS_8_BIT); 871 break; 872 #endif 873 874 case NJSC32_TARST_SDTR: 875 njsc32_msgout_sdtr(sc, sc->sc_synct[sc->sc_sync_max].sp_period, 876 NJSC32_SYNCOFFSET_MAX); 877 break; 878 879 case NJSC32_TARST_ASYNC: 880 njsc32_msgout_sdtr(sc, NJSC32_SYNCPERIOD_ASYNC, 881 NJSC32_SYNCOFFSET_ASYNC); 882 break; 883 } 884 } 885 886 /* turn LED on */ 887 static inline void 888 njsc32_led_on(struct njsc32_softc *sc) 889 { 890 891 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, NJSC32_EXTPORT_LED_ON); 892 } 893 894 /* turn LED off */ 895 static inline void 896 njsc32_led_off(struct njsc32_softc *sc) 897 { 898 899 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, NJSC32_EXTPORT_LED_OFF); 900 } 901 902 static void 903 njsc32_arbitration_failed(struct njsc32_softc *sc) 904 { 905 struct njsc32_cmd *cmd; 906 907 if ((cmd = sc->sc_curcmd) == NULL || sc->sc_stat != NJSC32_STAT_ARBIT) 908 return; 909 910 if ((cmd->c_xs->xs_control & XS_CTL_POLL) == 0) 911 callout_stop(&cmd->c_xs->xs_callout); 912 913 sc->sc_stat = NJSC32_STAT_IDLE; 914 sc->sc_curcmd = NULL; 915 916 /* the command is no longer active */ 917 if (--sc->sc_nusedcmds == 0) 918 njsc32_led_off(sc); 919 } 920 921 static inline void 922 njsc32_cmd_load(struct njsc32_softc *sc, struct njsc32_cmd *cmd) 923 { 924 struct njsc32_target *target; 925 struct scsipi_xfer *xs; 926 int i, control, lun; 927 u_int32_t msgoutreg; 928 #ifdef NJSC32_AUTOPARAM 929 struct njsc32_autoparam *ap; 930 #endif 931 932 xs = cmd->c_xs; 933 #ifdef NJSC32_AUTOPARAM 934 ap = &sc->sc_cmdpg->dp_ap; 935 #else 936 /* reset CDB pointer */ 937 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, NJSC32_CMD_CLEAR_CDB_FIFO_PTR); 938 #endif 939 940 /* CDB */ 941 TPRINTC(cmd, ("njsc32_cmd_load: CDB")); 942 for (i = 0; i < xs->cmdlen; i++) { 943 #ifdef NJSC32_AUTOPARAM 944 ap->ap_cdb[i].cdb_data = ((u_int8_t *)xs->cmd)[i]; 945 #else 946 njsc32_write_1(sc, NJSC32_REG_COMMAND_DATA, 947 ((u_int8_t *)xs->cmd)[i]); 948 #endif 949 TPRINTF((" %02x", ((u_int8_t *)cmd->c_xs->cmd)[i])); 950 } 951 #ifdef NJSC32_AUTOPARAM /* XXX needed? */ 952 for ( ; i < NJSC32_AUTOPARAM_CDBLEN; i++) 953 ap->ap_cdb[i].cdb_data = 0; 954 #endif 955 956 control = xs->xs_control; 957 958 /* 959 * Message Out 960 */ 961 njsc32_init_msgout(sc); 962 963 /* Identify */ 964 lun = xs->xs_periph->periph_lun; 965 njsc32_add_msgout(sc, (control & XS_CTL_REQSENSE) ? 966 MSG_IDENTIFY(lun, 0) : MSG_IDENTIFY(lun, 1)); 967 968 /* tagged queueing */ 969 if (control & XS_CTL_TAGMASK) { 970 njsc32_add_msgout(sc, xs->xs_tag_type); 971 njsc32_add_msgout(sc, xs->xs_tag_id); 972 TPRINTF((" (tag %#x %#x)\n", xs->xs_tag_type, xs->xs_tag_id)); 973 } 974 TPRINTF(("\n")); 975 976 target = cmd->c_target; 977 978 /* transfer negotiation */ 979 if (control & XS_CTL_REQSENSE) 980 target->t_state = NJSC32_TARST_INIT; 981 njsc32_negotiate_xfer(sc, target); 982 983 msgoutreg = njsc32_get_auto_msgout(sc); 984 985 #ifdef NJSC32_AUTOPARAM 986 ap->ap_msgout = htole32(msgoutreg); 987 988 ap->ap_sync = target->t_sync; 989 ap->ap_ackwidth = target->t_ackwidth; 990 ap->ap_targetid = target->t_targetid; 991 ap->ap_sample = target->t_sample; 992 993 ap->ap_cmdctl = htole16(NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 994 NJSC32_CMD_AUTO_COMMAND_PHASE | 995 NJSC32_CMD_AUTO_SCSI_START | NJSC32_CMD_AUTO_ATN | 996 NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02); 997 #ifdef NJSC32_DUALEDGE 998 ap->ap_xferctl = htole16(cmd->c_xferctl | target->t_xferctl); 999 #else 1000 ap->ap_xferctl = htole16(cmd->c_xferctl); 1001 #endif 1002 ap->ap_sgtdmaaddr = htole32(cmd->c_sgtdmaaddr); 1003 1004 /* sync njsc32_autoparam */ 1005 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1006 offsetof(struct njsc32_dma_page, dp_ap), /* offset */ 1007 sizeof(struct njsc32_autoparam), 1008 BUS_DMASYNC_PREWRITE); 1009 1010 /* autoparam DMA address */ 1011 njsc32_write_4(sc, NJSC32_REG_SGT_ADR, sc->sc_ap_dma); 1012 1013 /* start command (autoparam) */ 1014 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 1015 NJSC32_CMD_CLEAR_CDB_FIFO_PTR | NJSC32_CMD_AUTO_PARAMETER); 1016 1017 #else /* not NJSC32_AUTOPARAM */ 1018 1019 njsc32_write_4(sc, NJSC32_REG_SCSI_MSG_OUT, msgoutreg); 1020 1021 /* load parameters */ 1022 njsc32_write_1(sc, NJSC32_REG_TARGET_ID, target->t_targetid); 1023 njsc32_write_1(sc, NJSC32_REG_SYNC, target->t_sync); 1024 njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, target->t_ackwidth); 1025 njsc32_write_1(sc, NJSC32_REG_SREQ_SAMPLING, target->t_sample); 1026 njsc32_write_4(sc, NJSC32_REG_SGT_ADR, cmd->c_sgtdmaaddr); 1027 #ifdef NJSC32_DUALEDGE 1028 njsc32_write_2(sc, NJSC32_REG_TRANSFER, 1029 cmd->c_xferctl | target->t_xferctl); 1030 #else 1031 njsc32_write_2(sc, NJSC32_REG_TRANSFER, cmd->c_xferctl); 1032 #endif 1033 /* start AutoSCSI */ 1034 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 1035 NJSC32_CMD_CLEAR_CDB_FIFO_PTR | NJSC32_CMD_AUTO_COMMAND_PHASE | 1036 NJSC32_CMD_AUTO_SCSI_START | NJSC32_CMD_AUTO_ATN | 1037 NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02); 1038 #endif /* not NJSC32_AUTOPARAM */ 1039 } 1040 1041 /* Note: must be called at splbio() */ 1042 static void 1043 njsc32_start(struct njsc32_softc *sc) 1044 { 1045 struct njsc32_cmd *cmd; 1046 1047 /* get a command to issue */ 1048 TAILQ_FOREACH(cmd, &sc->sc_reqcmd, c_q) { 1049 if (cmd->c_lu->lu_cmd == NULL && 1050 ((cmd->c_flags & NJSC32_CMD_TAGGED) || 1051 TAILQ_EMPTY(&cmd->c_lu->lu_q))) 1052 break; /* OK, the logical unit is free */ 1053 } 1054 if (!cmd) 1055 goto out; /* no work to do */ 1056 1057 /* request will always fail if not in bus free phase */ 1058 if (njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) != 1059 NJSC32_BUSMON_BUSFREE) 1060 goto busy; 1061 1062 /* clear parity error and enable parity detection */ 1063 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 1064 NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR); 1065 1066 njsc32_cmd_load(sc, cmd); 1067 1068 if (sc->sc_nusedcmds++ == 0) 1069 njsc32_led_on(sc); 1070 1071 sc->sc_curcmd = cmd; 1072 sc->sc_stat = NJSC32_STAT_ARBIT; 1073 1074 if ((cmd->c_xs->xs_control & XS_CTL_POLL) == 0) { 1075 callout_reset(&cmd->c_xs->xs_callout, 1076 mstohz(cmd->c_xs->timeout), 1077 njsc32_cmdtimeout, cmd); 1078 } 1079 1080 return; 1081 1082 busy: /* XXX retry counter */ 1083 TPRINTF(("%s: njsc32_start: busy\n", device_xname(sc->sc_dev))); 1084 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_ARBITRATION_RETRY_TIME); 1085 out: njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0); 1086 } 1087 1088 static void 1089 njsc32_run_xfer(struct njsc32_softc *sc, struct scsipi_xfer *xs) 1090 { 1091 struct scsipi_periph *periph; 1092 int control; 1093 int lun; 1094 struct njsc32_cmd *cmd; 1095 int s, i, error; 1096 1097 periph = xs->xs_periph; 1098 KASSERT((unsigned)periph->periph_target <= NJSC32_MAX_TARGET_ID); 1099 1100 control = xs->xs_control; 1101 lun = periph->periph_lun; 1102 1103 /* 1104 * get a free cmd 1105 * (scsipi layer knows the number of cmds, so this shall never fail) 1106 */ 1107 s = splbio(); 1108 cmd = TAILQ_FIRST(&sc->sc_freecmd); 1109 KASSERT(cmd); 1110 TAILQ_REMOVE(&sc->sc_freecmd, cmd, c_q); 1111 splx(s); 1112 1113 /* 1114 * build a request 1115 */ 1116 njsc32_cmd_init(cmd); 1117 cmd->c_xs = xs; 1118 cmd->c_target = &sc->sc_targets[periph->periph_target]; 1119 cmd->c_lu = &cmd->c_target->t_lus[lun]; 1120 1121 /* tagged queueing */ 1122 if (control & XS_CTL_TAGMASK) { 1123 cmd->c_flags |= NJSC32_CMD_TAGGED; 1124 if (control & XS_CTL_HEAD_TAG) 1125 cmd->c_flags |= NJSC32_CMD_TAGGED_HEAD; 1126 } 1127 1128 /* map DMA buffer */ 1129 cmd->c_datacnt = xs->datalen; 1130 if (xs->datalen) { 1131 /* Is XS_CTL_DATA_UIO ever used anywhere? */ 1132 KASSERT((control & XS_CTL_DATA_UIO) == 0); 1133 1134 error = bus_dmamap_load(sc->sc_dmat, cmd->c_dmamap_xfer, 1135 xs->data, xs->datalen, NULL, 1136 ((control & XS_CTL_NOSLEEP) ? 1137 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 1138 BUS_DMA_STREAMING | 1139 ((control & XS_CTL_DATA_IN) ? 1140 BUS_DMA_READ : BUS_DMA_WRITE)); 1141 1142 switch (error) { 1143 case 0: 1144 break; 1145 case ENOMEM: 1146 case EAGAIN: 1147 xs->error = XS_RESOURCE_SHORTAGE; 1148 goto map_failed; 1149 default: 1150 xs->error = XS_DRIVER_STUFFUP; 1151 map_failed: 1152 aprint_error_dev(sc->sc_dev, "njsc32_run_xfer: map failed, error %d\n", 1153 error); 1154 /* put it back to free command list */ 1155 s = splbio(); 1156 TAILQ_INSERT_HEAD(&sc->sc_freecmd, cmd, c_q); 1157 splx(s); 1158 /* abort this transfer */ 1159 scsipi_done(xs); 1160 return; 1161 } 1162 1163 bus_dmamap_sync(sc->sc_dmat, cmd->c_dmamap_xfer, 1164 0, cmd->c_dmamap_xfer->dm_mapsize, 1165 (control & XS_CTL_DATA_IN) ? 1166 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1167 1168 for (i = 0; i < cmd->c_dmamap_xfer->dm_nsegs; i++) { 1169 cmd->c_sgt[i].sg_addr = 1170 htole32(cmd->c_dmamap_xfer->dm_segs[i].ds_addr); 1171 cmd->c_sgt[i].sg_len = 1172 htole32(cmd->c_dmamap_xfer->dm_segs[i].ds_len); 1173 } 1174 /* end mark */ 1175 cmd->c_sgt[i - 1].sg_len |= htole32(NJSC32_SGT_ENDMARK); 1176 1177 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1178 (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, /* offset */ 1179 NJSC32_SIZE_SGT, 1180 BUS_DMASYNC_PREWRITE); 1181 1182 cmd->c_flags |= NJSC32_CMD_DMA_MAPPED; 1183 1184 /* enable transfer */ 1185 cmd->c_xferctl = 1186 NJSC32_XFR_TRANSFER_GO | NJSC32_XFR_BM_START | 1187 NJSC32_XFR_ALL_COUNT_CLR; 1188 1189 /* XXX How can we specify the DMA direction? */ 1190 1191 #if 0 /* faster write mode? (doesn't work) */ 1192 if ((control & XS_CTL_DATA_IN) == 0) 1193 cmd->c_xferctl |= NJSC32_XFR_ADVANCED_BM_WRITE; 1194 #endif 1195 } else { 1196 /* no data transfer */ 1197 cmd->c_xferctl = 0; 1198 } 1199 1200 /* queue request */ 1201 s = splbio(); 1202 TAILQ_INSERT_TAIL(&sc->sc_reqcmd, cmd, c_q); 1203 1204 /* start the controller if idle */ 1205 if (sc->sc_stat == NJSC32_STAT_IDLE) 1206 njsc32_start(sc); 1207 1208 splx(s); 1209 1210 if (control & XS_CTL_POLL) { 1211 /* wait for completion */ 1212 /* XXX should handle timeout? */ 1213 while ((xs->xs_status & XS_STS_DONE) == 0) { 1214 delay(1000); 1215 njsc32_intr(sc); 1216 } 1217 } 1218 } 1219 1220 static void 1221 njsc32_end_cmd(struct njsc32_softc *sc, struct njsc32_cmd *cmd, 1222 scsipi_xfer_result_t result) 1223 { 1224 struct scsipi_xfer *xs; 1225 int s; 1226 #ifdef DIAGNOSTIC 1227 struct njsc32_cmd *c; 1228 #endif 1229 1230 KASSERT(cmd); 1231 1232 #ifdef DIAGNOSTIC 1233 s = splbio(); 1234 TAILQ_FOREACH(c, &sc->sc_freecmd, c_q) { 1235 if (cmd == c) 1236 panic("njsc32_end_cmd: already in free list"); 1237 } 1238 splx(s); 1239 #endif 1240 xs = cmd->c_xs; 1241 1242 if (cmd->c_flags & NJSC32_CMD_DMA_MAPPED) { 1243 if (cmd->c_datacnt) { 1244 bus_dmamap_sync(sc->sc_dmat, cmd->c_dmamap_xfer, 1245 0, cmd->c_dmamap_xfer->dm_mapsize, 1246 (xs->xs_control & XS_CTL_DATA_IN) ? 1247 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1248 1249 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1250 (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, 1251 NJSC32_SIZE_SGT, BUS_DMASYNC_POSTWRITE); 1252 } 1253 1254 bus_dmamap_unload(sc->sc_dmat, cmd->c_dmamap_xfer); 1255 cmd->c_flags &= ~NJSC32_CMD_DMA_MAPPED; 1256 } 1257 1258 s = splbio(); 1259 if ((xs->xs_control & XS_CTL_POLL) == 0) 1260 callout_stop(&xs->xs_callout); 1261 1262 TAILQ_INSERT_HEAD(&sc->sc_freecmd, cmd, c_q); 1263 splx(s); 1264 1265 xs->error = result; 1266 scsipi_done(xs); 1267 1268 if (--sc->sc_nusedcmds == 0) 1269 njsc32_led_off(sc); 1270 } 1271 1272 /* 1273 * request from scsipi layer 1274 */ 1275 static void 1276 njsc32_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 1277 void *arg) 1278 { 1279 struct njsc32_softc *sc; 1280 struct scsipi_xfer_mode *xm; 1281 struct njsc32_target *target; 1282 1283 sc = (void *)chan->chan_adapter->adapt_dev; 1284 1285 switch (req) { 1286 case ADAPTER_REQ_RUN_XFER: 1287 njsc32_run_xfer(sc, arg); 1288 break; 1289 1290 case ADAPTER_REQ_GROW_RESOURCES: 1291 /* not supported */ 1292 break; 1293 1294 case ADAPTER_REQ_SET_XFER_MODE: 1295 xm = arg; 1296 target = &sc->sc_targets[xm->xm_target]; 1297 1298 target->t_flags = 0; 1299 if (xm->xm_mode & PERIPH_CAP_TQING) 1300 target->t_flags |= NJSC32_TARF_TAG; 1301 if (xm->xm_mode & PERIPH_CAP_SYNC) { 1302 target->t_flags |= NJSC32_TARF_SYNC; 1303 #ifdef NJSC32_DUALEDGE 1304 if (sc->sc_model & NJSC32_FLAG_DUALEDGE) 1305 target->t_flags |= NJSC32_TARF_DE; 1306 #endif 1307 } 1308 #ifdef NJSC32_DUALEDGE 1309 target->t_xferctl = 0; 1310 #endif 1311 target->t_state = NJSC32_TARST_INIT; 1312 njsc32_target_async(sc, target); 1313 1314 break; 1315 default: 1316 break; 1317 } 1318 } 1319 1320 static void 1321 njsc32_scsipi_minphys(struct buf *bp) 1322 { 1323 1324 if (bp->b_bcount > NJSC32_MAX_XFER) 1325 bp->b_bcount = NJSC32_MAX_XFER; 1326 minphys(bp); 1327 } 1328 1329 /* 1330 * On some versions of 32UDE (probably the earlier ones), the controller 1331 * detects continuous bus reset when the termination power is absent. 1332 * Make sure the system won't hang on such situation. 1333 */ 1334 static void 1335 njsc32_wait_reset_release(void *arg) 1336 { 1337 struct njsc32_softc *sc = arg; 1338 struct njsc32_cmd *cmd; 1339 1340 /* clear pending commands */ 1341 while ((cmd = TAILQ_FIRST(&sc->sc_reqcmd)) != NULL) { 1342 TAILQ_REMOVE(&sc->sc_reqcmd, cmd, c_q); 1343 njsc32_end_cmd(sc, cmd, XS_RESET); 1344 } 1345 1346 /* If Bus Reset is not released yet, schedule recheck. */ 1347 if (njsc32_read_2(sc, NJSC32_REG_IRQ) & NJSC32_IRQ_SCSIRESET) { 1348 switch (sc->sc_stat) { 1349 case NJSC32_STAT_RESET: 1350 sc->sc_stat = NJSC32_STAT_RESET1; 1351 break; 1352 case NJSC32_STAT_RESET1: 1353 /* print message if Bus Reset is detected twice */ 1354 sc->sc_stat = NJSC32_STAT_RESET2; 1355 printf("%s: detected excessive bus reset --- missing termination power?\n", 1356 device_xname(sc->sc_dev)); 1357 break; 1358 default: 1359 break; 1360 } 1361 callout_reset(&sc->sc_callout, 1362 hz * 2 /* poll every 2s */, 1363 njsc32_wait_reset_release, sc); 1364 return; 1365 } 1366 1367 if (sc->sc_stat == NJSC32_STAT_RESET2) 1368 printf("%s: bus reset is released\n", device_xname(sc->sc_dev)); 1369 1370 /* unblock interrupts */ 1371 njsc32_write_2(sc, NJSC32_REG_IRQ, 0); 1372 1373 sc->sc_stat = NJSC32_STAT_IDLE; 1374 } 1375 1376 static void 1377 njsc32_reset_bus(struct njsc32_softc *sc) 1378 { 1379 int s; 1380 1381 DPRINTF(("%s: njsc32_reset_bus:\n", device_xname(sc->sc_dev))); 1382 1383 /* block interrupts */ 1384 njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL); 1385 1386 sc->sc_stat = NJSC32_STAT_RESET; 1387 1388 /* hold SCSI bus reset */ 1389 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, NJSC32_SBCTL_RST); 1390 delay(NJSC32_RESET_HOLD_TIME); 1391 1392 /* clear transfer */ 1393 njsc32_clear_cmds(sc, XS_RESET); 1394 1395 /* initialize target structure */ 1396 njsc32_init_targets(sc); 1397 1398 s = splbio(); 1399 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_RESET, NULL); 1400 splx(s); 1401 1402 /* release SCSI bus reset */ 1403 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, 0); 1404 1405 njsc32_wait_reset_release(sc); 1406 } 1407 1408 /* 1409 * clear running/disconnected commands 1410 */ 1411 static void 1412 njsc32_clear_cmds(struct njsc32_softc *sc, scsipi_xfer_result_t cmdresult) 1413 { 1414 struct njsc32_cmd *cmd; 1415 int id, lun; 1416 struct njsc32_lu *lu; 1417 1418 njsc32_arbitration_failed(sc); 1419 1420 /* clear current transfer */ 1421 if ((cmd = sc->sc_curcmd) != NULL) { 1422 sc->sc_curcmd = NULL; 1423 njsc32_end_cmd(sc, cmd, cmdresult); 1424 } 1425 1426 /* clear disconnected transfers */ 1427 for (id = 0; id <= NJSC32_MAX_TARGET_ID; id++) { 1428 for (lun = 0; lun < NJSC32_NLU; lun++) { 1429 lu = &sc->sc_targets[id].t_lus[lun]; 1430 1431 if ((cmd = lu->lu_cmd) != NULL) { 1432 lu->lu_cmd = NULL; 1433 njsc32_end_cmd(sc, cmd, cmdresult); 1434 } 1435 while ((cmd = TAILQ_FIRST(&lu->lu_q)) != NULL) { 1436 TAILQ_REMOVE(&lu->lu_q, cmd, c_q); 1437 njsc32_end_cmd(sc, cmd, cmdresult); 1438 } 1439 } 1440 } 1441 } 1442 1443 static int 1444 njsc32_scsipi_ioctl(struct scsipi_channel *chan, u_long cmd, 1445 void *addr, int flag, struct proc *p) 1446 { 1447 struct njsc32_softc *sc = (void *)chan->chan_adapter->adapt_dev; 1448 1449 switch (cmd) { 1450 case SCBUSIORESET: 1451 njsc32_init(sc, 0); 1452 return 0; 1453 default: 1454 break; 1455 } 1456 1457 return ENOTTY; 1458 } 1459 1460 /* 1461 * set current data pointer 1462 */ 1463 static inline void 1464 njsc32_set_cur_ptr(struct njsc32_cmd *cmd, u_int32_t pos) 1465 { 1466 1467 /* new current data pointer */ 1468 cmd->c_dp_cur = pos; 1469 1470 /* update number of bytes transferred */ 1471 if (pos > cmd->c_dp_max) 1472 cmd->c_dp_max = pos; 1473 } 1474 1475 /* 1476 * set data pointer for the next transfer 1477 */ 1478 static void 1479 njsc32_set_ptr(struct njsc32_softc *sc, struct njsc32_cmd *cmd, u_int32_t pos) 1480 { 1481 struct njsc32_sgtable *sg; 1482 unsigned sgte; 1483 u_int32_t len; 1484 1485 /* set current pointer */ 1486 njsc32_set_cur_ptr(cmd, pos); 1487 1488 /* undo previous fix if any */ 1489 if (cmd->c_sgfixcnt != 0) { 1490 sg = &cmd->c_sgt[cmd->c_sgoffset]; 1491 sg->sg_addr = htole32(le32toh(sg->sg_addr) - cmd->c_sgfixcnt); 1492 sg->sg_len = htole32(le32toh(sg->sg_len) + cmd->c_sgfixcnt); 1493 cmd->c_sgfixcnt = 0; 1494 } 1495 1496 if (pos >= cmd->c_datacnt) { 1497 /* transfer done */ 1498 #if 1 /*def DIAGNOSTIC*/ 1499 if (pos > cmd->c_datacnt) 1500 aprint_error_dev(sc->sc_dev, "pos %u too large\n", 1501 pos - cmd->c_datacnt); 1502 #endif 1503 cmd->c_xferctl = 0; /* XXX correct? */ 1504 1505 return; 1506 } 1507 1508 for (sgte = 0, sg = cmd->c_sgt; 1509 sgte < NJSC32_NUM_SG && pos > 0; sgte++, sg++) { 1510 len = le32toh(sg->sg_len) & ~NJSC32_SGT_ENDMARK; 1511 if (pos < len) { 1512 sg->sg_addr = htole32(le32toh(sg->sg_addr) + pos); 1513 sg->sg_len = htole32(le32toh(sg->sg_len) - pos); 1514 cmd->c_sgfixcnt = pos; 1515 break; 1516 } 1517 pos -= len; 1518 #ifdef DIAGNOSTIC 1519 if (sg->sg_len & htole32(NJSC32_SGT_ENDMARK)) { 1520 panic("njsc32_set_ptr: bad pos"); 1521 } 1522 #endif 1523 } 1524 #ifdef DIAGNOSTIC 1525 if (sgte >= NJSC32_NUM_SG) 1526 panic("njsc32_set_ptr: bad sg"); 1527 #endif 1528 if (cmd->c_sgoffset != sgte) { 1529 cmd->c_sgoffset = sgte; 1530 cmd->c_sgtdmaaddr = NJSC32_CMD_DMAADDR_SGT(cmd, sgte); 1531 } 1532 1533 /* XXX overkill */ 1534 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg, 1535 (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, /* offset */ 1536 NJSC32_SIZE_SGT, 1537 BUS_DMASYNC_PREWRITE); 1538 } 1539 1540 /* 1541 * save data pointer 1542 */ 1543 static inline void 1544 njsc32_save_ptr(struct njsc32_cmd *cmd) 1545 { 1546 1547 cmd->c_dp_saved = cmd->c_dp_cur; 1548 } 1549 1550 static void 1551 njsc32_assert_ack(struct njsc32_softc *sc) 1552 { 1553 u_int8_t reg; 1554 1555 reg = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_CONTROL); 1556 reg |= NJSC32_SBCTL_ACK | NJSC32_SBCTL_ACK_ENABLE; 1557 #if 0 /* needed? */ 1558 reg |= NJSC32_SBCTL_AUTODIRECTION; 1559 #endif 1560 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, reg); 1561 } 1562 1563 static void 1564 njsc32_negate_ack(struct njsc32_softc *sc) 1565 { 1566 u_int8_t reg; 1567 1568 reg = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_CONTROL); 1569 #if 0 /* needed? */ 1570 reg |= NJSC32_SBCTL_ACK_ENABLE; 1571 reg |= NJSC32_SBCTL_AUTODIRECTION; 1572 #endif 1573 reg &= ~NJSC32_SBCTL_ACK; 1574 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, reg); 1575 } 1576 1577 static void 1578 njsc32_wait_req_negate(struct njsc32_softc *sc) 1579 { 1580 int cnt; 1581 1582 for (cnt = 0; cnt < NJSC32_REQ_TIMEOUT; cnt++) { 1583 if ((njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) & 1584 NJSC32_BUSMON_REQ) == 0) 1585 return; 1586 delay(1); 1587 } 1588 printf("%s: njsc32_wait_req_negate: timed out\n", device_xname(sc->sc_dev)); 1589 } 1590 1591 static void 1592 njsc32_reconnect(struct njsc32_softc *sc, struct njsc32_cmd *cmd) 1593 { 1594 struct scsipi_xfer *xs; 1595 1596 xs = cmd->c_xs; 1597 if ((xs->xs_control & XS_CTL_POLL) == 0) { 1598 callout_stop(&xs->xs_callout); 1599 callout_reset(&xs->xs_callout, 1600 mstohz(xs->timeout), 1601 njsc32_cmdtimeout, cmd); 1602 } 1603 1604 /* Reconnection implies Restore Pointers */ 1605 njsc32_set_ptr(sc, cmd, cmd->c_dp_saved); 1606 } 1607 1608 static enum njsc32_reselstat 1609 njsc32_resel_identify(struct njsc32_softc *sc, int lun, 1610 struct njsc32_cmd **pcmd) 1611 { 1612 int targetid; 1613 struct njsc32_lu *plu; 1614 struct njsc32_cmd *cmd; 1615 1616 switch (sc->sc_stat) { 1617 case NJSC32_STAT_RESEL: 1618 break; /* OK */ 1619 1620 case NJSC32_STAT_RESEL_LUN: 1621 case NJSC32_STAT_RECONNECT: 1622 /* 1623 * accept and ignore if the LUN is the same as the current one, 1624 * reject otherwise. 1625 */ 1626 return sc->sc_resellun == lun ? 1627 NJSC32_RESEL_THROUGH : NJSC32_RESEL_ERROR; 1628 1629 default: 1630 aprint_error_dev(sc->sc_dev, "njsc32_resel_identify: not in reselection\n"); 1631 return NJSC32_RESEL_ERROR; 1632 } 1633 1634 targetid = sc->sc_reselid; 1635 TPRINTF(("%s: njsc32_resel_identify: reselection lun %d\n", 1636 device_xname(sc->sc_dev), lun)); 1637 1638 if (targetid > NJSC32_MAX_TARGET_ID || lun >= NJSC32_NLU) 1639 return NJSC32_RESEL_ERROR; 1640 1641 sc->sc_resellun = lun; 1642 plu = &sc->sc_targets[targetid].t_lus[lun]; 1643 1644 if ((cmd = plu->lu_cmd) != NULL) { 1645 sc->sc_stat = NJSC32_STAT_RECONNECT; 1646 plu->lu_cmd = NULL; 1647 *pcmd = cmd; 1648 TPRINTC(cmd, ("njsc32_resel_identify: I_T_L nexus\n")); 1649 njsc32_reconnect(sc, cmd); 1650 return NJSC32_RESEL_COMPLETE; 1651 } else if (!TAILQ_EMPTY(&plu->lu_q)) { 1652 /* wait for tag */ 1653 sc->sc_stat = NJSC32_STAT_RESEL_LUN; 1654 return NJSC32_RESEL_THROUGH; 1655 } 1656 1657 /* no disconnected commands */ 1658 return NJSC32_RESEL_ERROR; 1659 } 1660 1661 static enum njsc32_reselstat 1662 njsc32_resel_tag(struct njsc32_softc *sc, int tag, struct njsc32_cmd **pcmd) 1663 { 1664 struct njsc32_cmd_head *head; 1665 struct njsc32_cmd *cmd; 1666 1667 TPRINTF(("%s: njsc32_resel_tag: reselection tag %d\n", 1668 device_xname(sc->sc_dev), tag)); 1669 if (sc->sc_stat != NJSC32_STAT_RESEL_LUN) 1670 return NJSC32_RESEL_ERROR; 1671 1672 head = &sc->sc_targets[sc->sc_reselid].t_lus[sc->sc_resellun].lu_q; 1673 1674 /* XXX slow? */ 1675 /* search for the command of the tag */ 1676 TAILQ_FOREACH(cmd, head, c_q) { 1677 if (cmd->c_xs->xs_tag_id == tag) { 1678 sc->sc_stat = NJSC32_STAT_RECONNECT; 1679 TAILQ_REMOVE(head, cmd, c_q); 1680 *pcmd = cmd; 1681 TPRINTC(cmd, ("njsc32_resel_tag: I_T_L_Q nexus\n")); 1682 njsc32_reconnect(sc, cmd); 1683 return NJSC32_RESEL_COMPLETE; 1684 } 1685 } 1686 1687 /* no disconnected commands */ 1688 return NJSC32_RESEL_ERROR; 1689 } 1690 1691 /* 1692 * Reload parameters and restart AutoSCSI. 1693 * 1694 * XXX autoparam doesn't work as expected and we can't use it here. 1695 */ 1696 static void 1697 njsc32_cmd_reload(struct njsc32_softc *sc, struct njsc32_cmd *cmd, int cctl) 1698 { 1699 struct njsc32_target *target; 1700 1701 target = cmd->c_target; 1702 1703 /* clear parity error and enable parity detection */ 1704 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 1705 NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR); 1706 1707 /* load parameters */ 1708 njsc32_write_1(sc, NJSC32_REG_SYNC, target->t_sync); 1709 njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, target->t_ackwidth); 1710 njsc32_write_1(sc, NJSC32_REG_SREQ_SAMPLING, target->t_sample); 1711 njsc32_write_4(sc, NJSC32_REG_SGT_ADR, cmd->c_sgtdmaaddr); 1712 #ifdef NJSC32_DUALEDGE 1713 njsc32_write_2(sc, NJSC32_REG_TRANSFER, 1714 cmd->c_xferctl | target->t_xferctl); 1715 #else 1716 njsc32_write_2(sc, NJSC32_REG_TRANSFER, cmd->c_xferctl); 1717 #endif 1718 /* start AutoSCSI */ 1719 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 1720 1721 sc->sc_curcmd = cmd; 1722 } 1723 1724 static void 1725 njsc32_update_xfer_mode(struct njsc32_softc *sc, struct njsc32_target *target) 1726 { 1727 struct scsipi_xfer_mode xm; 1728 1729 xm.xm_target = target - sc->sc_targets; /* target ID */ 1730 xm.xm_mode = 0; 1731 xm.xm_period = target->t_syncperiod; 1732 xm.xm_offset = target->t_syncoffset; 1733 if (xm.xm_offset != 0) 1734 xm.xm_mode |= PERIPH_CAP_SYNC; 1735 if (target->t_flags & NJSC32_TARF_TAG) 1736 xm.xm_mode |= PERIPH_CAP_TQING; 1737 1738 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 1739 } 1740 1741 static void 1742 njsc32_msgin(struct njsc32_softc *sc) 1743 { 1744 u_int8_t msg0, msg; 1745 int msgcnt; 1746 struct njsc32_cmd *cmd; 1747 enum njsc32_reselstat rstat; 1748 int cctl = 0; 1749 u_int32_t ptr; /* unsigned type ensures 2-complement calculation */ 1750 u_int32_t msgout = 0; 1751 bool reload_params = FALSE; 1752 struct njsc32_target *target; 1753 int idx, period, offset; 1754 1755 /* 1756 * we are in Message In, so the previous Message Out should have 1757 * been done. 1758 */ 1759 njsc32_init_msgout(sc); 1760 1761 /* get a byte of Message In */ 1762 msg = njsc32_read_1(sc, NJSC32_REG_DATA_IN); 1763 TPRINTF(("%s: njsc32_msgin: got %#x\n", device_xname(sc->sc_dev), msg)); 1764 if ((msgcnt = sc->sc_msgincnt) < NJSC32_MSGIN_LEN) 1765 sc->sc_msginbuf[sc->sc_msgincnt] = msg; 1766 1767 njsc32_assert_ack(sc); 1768 1769 msg0 = sc->sc_msginbuf[0]; 1770 cmd = sc->sc_curcmd; 1771 1772 /* check for parity error */ 1773 if (njsc32_read_1(sc, NJSC32_REG_PARITY_STATUS) & 1774 NJSC32_PARITYSTATUS_ERROR_LSB) { 1775 1776 aprint_error_dev(sc->sc_dev, "msgin: parity error\n"); 1777 1778 /* clear parity error */ 1779 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 1780 NJSC32_PARITYCTL_CHECK_ENABLE | 1781 NJSC32_PARITYCTL_CLEAR_ERROR); 1782 1783 /* respond as Message Parity Error */ 1784 njsc32_add_msgout(sc, MSG_PARITY_ERROR); 1785 1786 /* clear Message In */ 1787 sc->sc_msgincnt = 0; 1788 goto reply; 1789 } 1790 1791 #define WAITNEXTMSG do { sc->sc_msgincnt++; goto restart; } while (0) 1792 #define MSGCOMPLETE do { sc->sc_msgincnt = 0; goto restart; } while (0) 1793 if (MSG_ISIDENTIFY(msg0)) { 1794 /* 1795 * Got Identify message from target. 1796 */ 1797 if ((msg0 & ~MSG_IDENTIFY_LUNMASK) != MSG_IDENTIFYFLAG || 1798 (rstat = njsc32_resel_identify(sc, msg0 & 1799 MSG_IDENTIFY_LUNMASK, &cmd)) == NJSC32_RESEL_ERROR) { 1800 /* 1801 * invalid Identify -> Reject 1802 */ 1803 goto reject; 1804 } 1805 if (rstat == NJSC32_RESEL_COMPLETE) 1806 reload_params = TRUE; 1807 MSGCOMPLETE; 1808 } 1809 1810 if (msg0 == MSG_SIMPLE_Q_TAG) { 1811 if (msgcnt == 0) 1812 WAITNEXTMSG; 1813 1814 /* got whole message */ 1815 sc->sc_msgincnt = 0; 1816 1817 if ((rstat = njsc32_resel_tag(sc, sc->sc_msginbuf[1], &cmd)) 1818 == NJSC32_RESEL_ERROR) { 1819 /* 1820 * invalid Simple Queue Tag -> Abort Tag 1821 */ 1822 printf("%s: msgin: invalid tag\n", device_xname(sc->sc_dev)); 1823 njsc32_add_msgout(sc, MSG_ABORT_TAG); 1824 goto reply; 1825 } 1826 if (rstat == NJSC32_RESEL_COMPLETE) 1827 reload_params = TRUE; 1828 MSGCOMPLETE; 1829 } 1830 1831 /* I_T_L or I_T_L_Q nexus should be established now */ 1832 if (cmd == NULL) { 1833 printf("%s: msgin %#x without nexus -- sending abort\n", 1834 device_xname(sc->sc_dev), msg0); 1835 njsc32_add_msgout(sc, MSG_ABORT); 1836 goto reply; 1837 } 1838 1839 /* 1840 * extended message 1841 * 0x01 <length (0 stands for 256)> <length bytes> 1842 * (<code> [<parameter> ...]) 1843 */ 1844 #define EXTLENOFF 1 1845 #define EXTCODEOFF 2 1846 if (msg0 == MSG_EXTENDED) { 1847 if (msgcnt < EXTLENOFF || 1848 msgcnt < EXTLENOFF + 1 + 1849 (u_int8_t)(sc->sc_msginbuf[EXTLENOFF] - 1)) 1850 WAITNEXTMSG; 1851 1852 /* got whole message */ 1853 sc->sc_msgincnt = 0; 1854 1855 switch (sc->sc_msginbuf[EXTCODEOFF]) { 1856 case 0: /* Modify Data Pointer */ 1857 if (msgcnt != 5 + EXTCODEOFF - 1) 1858 break; 1859 /* 1860 * parameter is 32bit big-endian signed (2-complement) 1861 * value 1862 */ 1863 ptr = (sc->sc_msginbuf[EXTCODEOFF + 1] << 24) | 1864 (sc->sc_msginbuf[EXTCODEOFF + 2] << 16) | 1865 (sc->sc_msginbuf[EXTCODEOFF + 3] << 8) | 1866 sc->sc_msginbuf[EXTCODEOFF + 4]; 1867 1868 /* new pointer */ 1869 ptr += cmd->c_dp_cur; /* ignore overflow */ 1870 1871 /* reject if ptr is not in data buffer */ 1872 if (ptr > cmd->c_datacnt) 1873 break; 1874 1875 njsc32_set_ptr(sc, cmd, ptr); 1876 goto restart; 1877 1878 case MSG_EXT_SDTR: /* Synchronous Data Transfer Request */ 1879 DPRINTC(cmd, ("SDTR %#x %#x\n", 1880 sc->sc_msginbuf[EXTCODEOFF + 1], 1881 sc->sc_msginbuf[EXTCODEOFF + 2])); 1882 if (msgcnt != MSG_EXT_SDTR_LEN + EXTCODEOFF-1) 1883 break; /* reject */ 1884 1885 target = cmd->c_target; 1886 1887 /* lookup sync period parameters */ 1888 period = sc->sc_msginbuf[EXTCODEOFF + 1]; 1889 for (idx = sc->sc_sync_max; idx < NJSC32_NSYNCT; idx++) 1890 if (sc->sc_synct[idx].sp_period >= period) { 1891 period = sc->sc_synct[idx].sp_period; 1892 break; 1893 } 1894 if (idx >= NJSC32_NSYNCT) { 1895 /* 1896 * We can't meet the timing condition that 1897 * the target requests -- use async. 1898 */ 1899 njsc32_target_async(sc, target); 1900 njsc32_update_xfer_mode(sc, target); 1901 if (target->t_state == NJSC32_TARST_SDTR) { 1902 /* 1903 * We started SDTR exchange -- start 1904 * negotiation again and request async. 1905 */ 1906 target->t_state = NJSC32_TARST_ASYNC; 1907 njsc32_negotiate_xfer(sc, target); 1908 goto reply; 1909 } else { 1910 /* 1911 * The target started SDTR exchange 1912 * -- just reject and fallback 1913 * to async. 1914 */ 1915 goto reject; 1916 } 1917 } 1918 1919 /* check sync offset */ 1920 offset = sc->sc_msginbuf[EXTCODEOFF + 2]; 1921 if (offset > NJSC32_SYNCOFFSET_MAX) { 1922 if (target->t_state == NJSC32_TARST_SDTR) { 1923 aprint_error_dev(cmd->c_xs->xs_periph->periph_dev, "wrong sync offset: %d\n", offset); 1924 /* XXX what to do? */ 1925 } 1926 offset = NJSC32_SYNCOFFSET_MAX; 1927 } 1928 1929 target->t_ackwidth = sc->sc_synct[idx].sp_ackw; 1930 target->t_sample = sc->sc_synct[idx].sp_sample; 1931 target->t_syncperiod = period; 1932 target->t_syncoffset = offset; 1933 target->t_sync = NJSC32_SYNC_VAL(idx, offset); 1934 njsc32_update_xfer_mode(sc, target); 1935 1936 if (target->t_state == NJSC32_TARST_SDTR) { 1937 target->t_state = NJSC32_TARST_DONE; 1938 } else { 1939 njsc32_msgout_sdtr(sc, period, offset); 1940 goto reply; 1941 } 1942 goto restart; 1943 1944 case MSG_EXT_WDTR: /* Wide Data Transfer Request */ 1945 DPRINTC(cmd, 1946 ("WDTR %#x\n", sc->sc_msginbuf[EXTCODEOFF + 1])); 1947 #ifdef NJSC32_DUALEDGE 1948 if (msgcnt != MSG_EXT_WDTR_LEN + EXTCODEOFF-1) 1949 break; /* reject */ 1950 1951 /* 1952 * T->I of this message is not used for 1953 * DualEdge negotiation, so the device 1954 * must not be a DualEdge device. 1955 * 1956 * XXX correct? 1957 */ 1958 target = cmd->c_target; 1959 target->t_xferctl = 0; 1960 1961 switch (target->t_state) { 1962 case NJSC32_TARST_DE: 1963 if (sc->sc_msginbuf[EXTCODEOFF + 1] != 1964 MSG_EXT_WDTR_BUS_8_BIT) { 1965 /* 1966 * Oops, we got unexpected WDTR. 1967 * Negotiate for 8bit. 1968 */ 1969 target->t_state = NJSC32_TARST_WDTR; 1970 } else { 1971 target->t_state = NJSC32_TARST_SDTR; 1972 } 1973 njsc32_negotiate_xfer(sc, target); 1974 goto reply; 1975 1976 case NJSC32_TARST_WDTR: 1977 if (sc->sc_msginbuf[EXTCODEOFF + 1] != 1978 MSG_EXT_WDTR_BUS_8_BIT) { 1979 aprint_error_dev(cmd->c_xs->xs_periph->periph_dev, "unexpected transfer width: %#x\n", 1980 sc->sc_msginbuf[EXTCODEOFF + 1]); 1981 /* XXX what to do? */ 1982 } 1983 target->t_state = NJSC32_TARST_SDTR; 1984 njsc32_negotiate_xfer(sc, target); 1985 goto reply; 1986 1987 default: 1988 /* the target started WDTR exchange */ 1989 DPRINTC(cmd, ("WDTR from target\n")); 1990 1991 target->t_state = NJSC32_TARST_SDTR; 1992 njsc32_target_async(sc, target); 1993 1994 break; /* reject the WDTR (8bit transfer) */ 1995 } 1996 #endif /* NJSC32_DUALEDGE */ 1997 break; /* reject */ 1998 } 1999 DPRINTC(cmd, ("njsc32_msgin: reject ext msg %#x msgincnt %d\n", 2000 sc->sc_msginbuf[EXTCODEOFF], msgcnt)); 2001 goto reject; 2002 } 2003 2004 /* 2byte messages */ 2005 if (MSG_IS2BYTE(msg0)) { 2006 if (msgcnt == 0) 2007 WAITNEXTMSG; 2008 2009 /* got whole message */ 2010 sc->sc_msgincnt = 0; 2011 } 2012 2013 switch (msg0) { 2014 case MSG_CMDCOMPLETE: /* 0x00 */ 2015 case MSG_SAVEDATAPOINTER: /* 0x02 */ 2016 case MSG_DISCONNECT: /* 0x04 */ 2017 /* handled by AutoSCSI */ 2018 PRINTC(cmd, ("msgin: unexpected msg: %#x\n", msg0)); 2019 break; 2020 2021 case MSG_RESTOREPOINTERS: /* 0x03 */ 2022 /* restore data pointer to what was saved */ 2023 DPRINTC(cmd, ("njsc32_msgin: Restore Pointers\n")); 2024 njsc32_set_ptr(sc, cmd, cmd->c_dp_saved); 2025 reload_params = TRUE; 2026 MSGCOMPLETE; 2027 /* NOTREACHED */ 2028 break; 2029 2030 #if 0 /* handled above */ 2031 case MSG_EXTENDED: /* 0x01 */ 2032 #endif 2033 case MSG_MESSAGE_REJECT: /* 0x07 */ 2034 target = cmd->c_target; 2035 DPRINTC(cmd, ("Reject tarst %d\n", target->t_state)); 2036 switch (target->t_state) { 2037 #ifdef NJSC32_DUALEDGE 2038 case NJSC32_TARST_WDTR: 2039 case NJSC32_TARST_DE: 2040 target->t_xferctl = 0; 2041 target->t_state = NJSC32_TARST_SDTR; 2042 njsc32_negotiate_xfer(sc, target); 2043 goto reply; 2044 #endif 2045 case NJSC32_TARST_SDTR: 2046 case NJSC32_TARST_ASYNC: 2047 njsc32_target_async(sc, target); 2048 target->t_state = NJSC32_TARST_DONE; 2049 njsc32_update_xfer_mode(sc, target); 2050 break; 2051 default: 2052 break; 2053 } 2054 goto restart; 2055 2056 case MSG_NOOP: /* 0x08 */ 2057 #ifdef NJSC32_DUALEDGE 2058 target = cmd->c_target; 2059 if (target->t_state == NJSC32_TARST_DE) { 2060 aprint_normal_dev(&cmd->c_xs->xs_periph->periph_dev, 2061 "%s: DualEdge transfer\n"); 2062 target->t_xferctl = NJSC32_XFR_DUALEDGE_ENABLE; 2063 /* go to next negotiation */ 2064 target->t_state = NJSC32_TARST_SDTR; 2065 njsc32_negotiate_xfer(sc, target); 2066 goto reply; 2067 } 2068 #endif 2069 goto restart; 2070 2071 case MSG_INITIATOR_DET_ERR: /* 0x05 I->T only */ 2072 case MSG_ABORT: /* 0x06 I->T only */ 2073 case MSG_PARITY_ERROR: /* 0x09 I->T only */ 2074 case MSG_LINK_CMD_COMPLETE: /* 0x0a */ 2075 case MSG_LINK_CMD_COMPLETEF: /* 0x0b */ 2076 case MSG_BUS_DEV_RESET: /* 0x0c I->T only */ 2077 case MSG_ABORT_TAG: /* 0x0d I->T only */ 2078 case MSG_CLEAR_QUEUE: /* 0x0e I->T only */ 2079 2080 #if 0 /* handled above */ 2081 case MSG_SIMPLE_Q_TAG: /* 0x20 */ 2082 #endif 2083 case MSG_HEAD_OF_Q_TAG: /* 0x21 I->T only */ 2084 case MSG_ORDERED_Q_TAG: /* 0x22 I->T only */ 2085 case MSG_IGN_WIDE_RESIDUE: /* 0x23 */ 2086 2087 default: 2088 #ifdef NJSC32_DEBUG 2089 PRINTC(cmd, ("msgin: unsupported msg: %#x", msg0)); 2090 if (MSG_IS2BYTE(msg0)) 2091 printf(" %#x", msg); 2092 printf("\n"); 2093 #endif 2094 break; 2095 } 2096 2097 reject: 2098 njsc32_add_msgout(sc, MSG_MESSAGE_REJECT); 2099 2100 reply: 2101 msgout = njsc32_get_auto_msgout(sc); 2102 2103 restart: 2104 cctl = NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 2105 NJSC32_CMD_AUTO_COMMAND_PHASE | 2106 NJSC32_CMD_AUTO_SCSI_RESTART; 2107 2108 /* 2109 * Be careful the second and latter bytes of Message In 2110 * shall not be absorbed by AutoSCSI. 2111 */ 2112 if (sc->sc_msgincnt == 0) 2113 cctl |= NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02; 2114 2115 if (sc->sc_msgoutlen != 0) 2116 cctl |= NJSC32_CMD_AUTO_ATN; 2117 2118 njsc32_write_4(sc, NJSC32_REG_SCSI_MSG_OUT, msgout); 2119 2120 /* (re)start AutoSCSI (may assert ATN) */ 2121 if (reload_params) { 2122 njsc32_cmd_reload(sc, cmd, cctl); 2123 } else { 2124 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 2125 } 2126 2127 /* +ATN -> -REQ: need 90ns delay? */ 2128 2129 njsc32_wait_req_negate(sc); /* wait for REQ negation */ 2130 2131 njsc32_negate_ack(sc); 2132 2133 return; 2134 } 2135 2136 static void 2137 njsc32_msgout(struct njsc32_softc *sc) 2138 { 2139 int cctl; 2140 u_int8_t bus; 2141 unsigned n; 2142 2143 if (sc->sc_msgoutlen == 0) { 2144 /* target entered to Message Out on unexpected timing */ 2145 njsc32_add_msgout(sc, MSG_NOOP); 2146 } 2147 2148 cctl = NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 2149 NJSC32_CMD_AUTO_COMMAND_PHASE | NJSC32_CMD_AUTO_SCSI_RESTART | 2150 NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02; 2151 2152 /* make sure target is in Message Out phase */ 2153 bus = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR); 2154 if ((bus & NJSC32_BUSMON_PHASE_MASK) != NJSC32_PHASE_MESSAGE_OUT) { 2155 /* 2156 * Message Out is aborted by target. 2157 */ 2158 printf("%s: njsc32_msgout: phase change %#x\n", 2159 device_xname(sc->sc_dev), bus); 2160 2161 /* XXX what to do? */ 2162 2163 /* restart AutoSCSI (negate ATN) */ 2164 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 2165 2166 sc->sc_msgoutidx = 0; 2167 return; 2168 } 2169 2170 n = sc->sc_msgoutidx; 2171 if (n == sc->sc_msgoutlen - 1) { 2172 /* 2173 * negate ATN before sending ACK 2174 */ 2175 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 0); 2176 2177 sc->sc_msgoutidx = 0; /* target may retry Message Out */ 2178 } else { 2179 cctl |= NJSC32_CMD_AUTO_ATN; 2180 sc->sc_msgoutidx++; 2181 } 2182 2183 /* Send Message Out */ 2184 njsc32_write_1(sc, NJSC32_REG_SCSI_OUT_LATCH, sc->sc_msgout[n]); 2185 2186 /* DBn -> +ACK: need 55ns delay? */ 2187 2188 njsc32_assert_ack(sc); 2189 njsc32_wait_req_negate(sc); /* wait for REQ negation */ 2190 2191 /* restart AutoSCSI */ 2192 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl); 2193 2194 njsc32_negate_ack(sc); 2195 2196 /* 2197 * do not reset sc->sc_msgoutlen so the target 2198 * can retry Message Out phase 2199 */ 2200 } 2201 2202 static void 2203 njsc32_cmdtimeout(void *arg) 2204 { 2205 struct njsc32_cmd *cmd = arg; 2206 struct njsc32_softc *sc; 2207 int s; 2208 2209 PRINTC(cmd, ("command timeout\n")); 2210 2211 sc = cmd->c_sc; 2212 2213 s = splbio(); 2214 2215 if (sc->sc_stat == NJSC32_STAT_ARBIT) 2216 njsc32_arbitration_failed(sc); 2217 else { 2218 sc->sc_curcmd = NULL; 2219 sc->sc_stat = NJSC32_STAT_IDLE; 2220 njsc32_end_cmd(sc, cmd, XS_TIMEOUT); 2221 } 2222 2223 /* XXX? */ 2224 njsc32_init(sc, 1); /* bus reset */ 2225 2226 splx(s); 2227 } 2228 2229 static void 2230 njsc32_reseltimeout(void *arg) 2231 { 2232 struct njsc32_cmd *cmd = arg; 2233 struct njsc32_softc *sc; 2234 int s; 2235 2236 PRINTC(cmd, ("reselection timeout\n")); 2237 2238 sc = cmd->c_sc; 2239 2240 s = splbio(); 2241 2242 /* remove from disconnected list */ 2243 if (cmd->c_flags & NJSC32_CMD_TAGGED) { 2244 /* I_T_L_Q */ 2245 KASSERT(cmd->c_lu->lu_cmd == NULL); 2246 TAILQ_REMOVE(&cmd->c_lu->lu_q, cmd, c_q); 2247 } else { 2248 /* I_T_L */ 2249 KASSERT(cmd->c_lu->lu_cmd == cmd); 2250 cmd->c_lu->lu_cmd = NULL; 2251 } 2252 2253 njsc32_end_cmd(sc, cmd, XS_TIMEOUT); 2254 2255 /* XXX? */ 2256 njsc32_init(sc, 1); /* bus reset */ 2257 2258 splx(s); 2259 } 2260 2261 static inline void 2262 njsc32_end_auto(struct njsc32_softc *sc, struct njsc32_cmd *cmd, int auto_phase) 2263 { 2264 struct scsipi_xfer *xs; 2265 2266 if (auto_phase & NJSC32_XPHASE_MSGIN_02) { 2267 /* Message In: 0x02 Save Data Pointer */ 2268 2269 /* 2270 * Adjust saved data pointer 2271 * if the command is not completed yet. 2272 */ 2273 if ((auto_phase & NJSC32_XPHASE_MSGIN_00) == 0 && 2274 (auto_phase & 2275 (NJSC32_XPHASE_DATA_IN | NJSC32_XPHASE_DATA_OUT)) != 0) { 2276 njsc32_save_ptr(cmd); 2277 } 2278 TPRINTF(("BM %u, SGT %u, SACK %u, SAVED_ACK %u\n", 2279 njsc32_read_4(sc, NJSC32_REG_BM_CNT), 2280 njsc32_read_4(sc, NJSC32_REG_SGT_ADR), 2281 njsc32_read_4(sc, NJSC32_REG_SACK_CNT), 2282 njsc32_read_4(sc, NJSC32_REG_SAVED_ACK_CNT))); 2283 } 2284 2285 xs = cmd->c_xs; 2286 2287 if (auto_phase & NJSC32_XPHASE_MSGIN_00) { 2288 /* Command Complete */ 2289 TPRINTC(cmd, ("njsc32_intr: Command Complete\n")); 2290 switch (xs->status) { 2291 case SCSI_CHECK: case SCSI_QUEUE_FULL: case SCSI_BUSY: 2292 /* 2293 * scsipi layer will automatically handle the error 2294 */ 2295 njsc32_end_cmd(sc, cmd, XS_BUSY); 2296 break; 2297 default: 2298 xs->resid -= cmd->c_dp_max; 2299 njsc32_end_cmd(sc, cmd, XS_NOERROR); 2300 break; 2301 } 2302 } else if (auto_phase & NJSC32_XPHASE_MSGIN_04) { 2303 /* Disconnect */ 2304 TPRINTC(cmd, ("njsc32_intr: Disconnect\n")); 2305 2306 /* for ill-designed devices */ 2307 if ((xs->xs_periph->periph_quirks & PQUIRK_AUTOSAVE) != 0) 2308 njsc32_save_ptr(cmd); 2309 2310 /* 2311 * move current cmd to disconnected list 2312 */ 2313 if (cmd->c_flags & NJSC32_CMD_TAGGED) { 2314 /* I_T_L_Q */ 2315 if (cmd->c_flags & NJSC32_CMD_TAGGED_HEAD) 2316 TAILQ_INSERT_HEAD(&cmd->c_lu->lu_q, cmd, c_q); 2317 else 2318 TAILQ_INSERT_TAIL(&cmd->c_lu->lu_q, cmd, c_q); 2319 } else { 2320 /* I_T_L */ 2321 cmd->c_lu->lu_cmd = cmd; 2322 } 2323 2324 /* 2325 * schedule timeout -- avoid being 2326 * disconnected forever 2327 */ 2328 if ((xs->xs_control & XS_CTL_POLL) == 0) { 2329 callout_stop(&xs->xs_callout); 2330 callout_reset(&xs->xs_callout, mstohz(xs->timeout), 2331 njsc32_reseltimeout, cmd); 2332 } 2333 2334 } else { 2335 /* 2336 * target has come to Bus Free phase 2337 * probably to notify an error 2338 */ 2339 PRINTC(cmd, ("njsc32_intr: unexpected bus free\n")); 2340 /* try Request Sense */ 2341 xs->status = SCSI_CHECK; 2342 njsc32_end_cmd(sc, cmd, XS_BUSY); 2343 } 2344 } 2345 2346 int 2347 njsc32_intr(void *arg) 2348 { 2349 struct njsc32_softc *sc = arg; 2350 u_int16_t intr; 2351 u_int8_t arbstat, bus_phase; 2352 int auto_phase; 2353 int idbit; 2354 struct njsc32_cmd *cmd; 2355 2356 intr = njsc32_read_2(sc, NJSC32_REG_IRQ); 2357 if ((intr & NJSC32_IRQ_INTR_PENDING) == 0) 2358 return 0; /* not mine */ 2359 2360 TPRINTF(("%s: njsc32_intr: %#x\n", device_xname(sc->sc_dev), intr)); 2361 2362 #if 0 /* I don't think this is required */ 2363 /* mask interrupts */ 2364 njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL); 2365 #endif 2366 2367 /* we got an interrupt, so stop the timer */ 2368 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP); 2369 2370 if (intr & NJSC32_IRQ_SCSIRESET) { 2371 printf("%s: detected bus reset\n", device_xname(sc->sc_dev)); 2372 /* make sure all devices on the bus are certainly reset */ 2373 njsc32_reset_bus(sc); 2374 goto out; 2375 } 2376 2377 if (sc->sc_stat == NJSC32_STAT_ARBIT) { 2378 cmd = sc->sc_curcmd; 2379 KASSERT(cmd); 2380 arbstat = njsc32_read_1(sc, NJSC32_REG_ARBITRATION_STAT); 2381 if (arbstat & (NJSC32_ARBSTAT_WIN | NJSC32_ARBSTAT_FAIL)) { 2382 /* 2383 * arbitration done 2384 */ 2385 /* clear arbitration status */ 2386 njsc32_write_1(sc, NJSC32_REG_SET_ARBITRATION, 2387 NJSC32_SETARB_CLEAR); 2388 2389 if (arbstat & NJSC32_ARBSTAT_WIN) { 2390 TPRINTC(cmd, 2391 ("njsc32_intr: arbitration won\n")); 2392 2393 TAILQ_REMOVE(&sc->sc_reqcmd, cmd, c_q); 2394 2395 sc->sc_stat = NJSC32_STAT_CONNECT; 2396 } else { 2397 TPRINTC(cmd, 2398 ("njsc32_intr: arbitration failed\n")); 2399 2400 njsc32_arbitration_failed(sc); 2401 2402 /* XXX delay */ 2403 /* XXX retry counter */ 2404 } 2405 } 2406 } 2407 2408 if (intr & NJSC32_IRQ_TIMER) { 2409 TPRINTF(("%s: njsc32_intr: timer interrupt\n", 2410 device_xname(sc->sc_dev))); 2411 } 2412 2413 if (intr & NJSC32_IRQ_RESELECT) { 2414 /* Reselection from a target */ 2415 njsc32_arbitration_failed(sc); /* just in case */ 2416 if ((cmd = sc->sc_curcmd) != NULL) { 2417 /* ? */ 2418 aprint_error_dev(sc->sc_dev, "unexpected reselection\n"); 2419 sc->sc_curcmd = NULL; 2420 sc->sc_stat = NJSC32_STAT_IDLE; 2421 njsc32_end_cmd(sc, cmd, XS_DRIVER_STUFFUP); 2422 } 2423 2424 idbit = njsc32_read_1(sc, NJSC32_REG_RESELECT_ID); 2425 if ((idbit & (1 << NJSC32_INITIATOR_ID)) == 0 || 2426 (sc->sc_reselid = 2427 ffs(idbit & ~(1 << NJSC32_INITIATOR_ID)) - 1) < 0) { 2428 aprint_error_dev(sc->sc_dev, "invalid reselection (id: %#x)\n", 2429 idbit); 2430 sc->sc_stat = NJSC32_STAT_IDLE; /* XXX ? */ 2431 } else { 2432 sc->sc_stat = NJSC32_STAT_RESEL; 2433 TPRINTF(("%s: njsc32_intr: reselection from %d\n", 2434 device_xname(sc->sc_dev), sc->sc_reselid)); 2435 } 2436 } 2437 2438 if (intr & NJSC32_IRQ_PHASE_CHANGE) { 2439 #if 1 /* XXX probably not needed */ 2440 if (sc->sc_stat == NJSC32_STAT_ARBIT) 2441 PRINTC(sc->sc_curcmd, 2442 ("njsc32_intr: cancel arbitration phase\n")); 2443 njsc32_arbitration_failed(sc); 2444 #endif 2445 /* current bus phase */ 2446 bus_phase = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) & 2447 NJSC32_BUSMON_PHASE_MASK; 2448 2449 switch (bus_phase) { 2450 case NJSC32_PHASE_MESSAGE_IN: 2451 njsc32_msgin(sc); 2452 break; 2453 2454 /* 2455 * target may suddenly become Status / Bus Free phase 2456 * to notify an error condition 2457 */ 2458 case NJSC32_PHASE_STATUS: 2459 printf("%s: unexpected bus phase: Status\n", 2460 device_xname(sc->sc_dev)); 2461 if ((cmd = sc->sc_curcmd) != NULL) { 2462 cmd->c_xs->status = 2463 njsc32_read_1(sc, NJSC32_REG_SCSI_CSB_IN); 2464 TPRINTC(cmd, ("njsc32_intr: Status %d\n", 2465 cmd->c_xs->status)); 2466 } 2467 break; 2468 case NJSC32_PHASE_BUSFREE: 2469 aprint_error_dev(sc->sc_dev, "unexpected bus phase: Bus Free\n"); 2470 if ((cmd = sc->sc_curcmd) != NULL) { 2471 sc->sc_curcmd = NULL; 2472 sc->sc_stat = NJSC32_STAT_IDLE; 2473 if (cmd->c_xs->status != SCSI_QUEUE_FULL && 2474 cmd->c_xs->status != SCSI_BUSY) 2475 cmd->c_xs->status = SCSI_CHECK;/* XXX */ 2476 njsc32_end_cmd(sc, cmd, XS_BUSY); 2477 } 2478 goto out; 2479 default: 2480 #ifdef NJSC32_DEBUG 2481 printf("%s: unexpected bus phase: ", 2482 device_xname(sc->sc_dev)); 2483 switch (bus_phase) { 2484 case NJSC32_PHASE_COMMAND: 2485 printf("Command\n"); break; 2486 case NJSC32_PHASE_MESSAGE_OUT: 2487 printf("Message Out\n");break; 2488 case NJSC32_PHASE_DATA_IN: 2489 printf("Data In\n"); break; 2490 case NJSC32_PHASE_DATA_OUT: 2491 printf("Data Out\n"); break; 2492 case NJSC32_PHASE_RESELECT: 2493 printf("Reselect\n");break; 2494 default: printf("%#x\n", bus_phase); break; 2495 } 2496 #else 2497 aprint_error_dev(sc->sc_dev, "unexpected bus phase: %#x", 2498 bus_phase); 2499 #endif 2500 break; 2501 } 2502 } 2503 2504 if (intr & NJSC32_IRQ_AUTOSCSI) { 2505 /* 2506 * AutoSCSI interrupt 2507 */ 2508 auto_phase = njsc32_read_2(sc, NJSC32_REG_EXECUTE_PHASE); 2509 TPRINTF(("%s: njsc32_intr: AutoSCSI: %#x\n", 2510 device_xname(sc->sc_dev), auto_phase)); 2511 njsc32_write_2(sc, NJSC32_REG_EXECUTE_PHASE, 0); 2512 2513 if (auto_phase & NJSC32_XPHASE_SEL_TIMEOUT) { 2514 cmd = sc->sc_curcmd; 2515 if (cmd == NULL) { 2516 aprint_error_dev(sc->sc_dev, "sel no cmd\n"); 2517 goto out; 2518 } 2519 DPRINTC(cmd, ("njsc32_intr: selection timeout\n")); 2520 2521 sc->sc_curcmd = NULL; 2522 sc->sc_stat = NJSC32_STAT_IDLE; 2523 njsc32_end_cmd(sc, cmd, XS_SELTIMEOUT); 2524 2525 goto out; 2526 } 2527 2528 #ifdef NJSC32_TRACE 2529 if (auto_phase & NJSC32_XPHASE_COMMAND) { 2530 /* Command phase has been automatically processed */ 2531 TPRINTF(("%s: njsc32_intr: Command\n", 2532 device_xname(sc->sc_dev))); 2533 } 2534 #endif 2535 #ifdef NJSC32_DEBUG 2536 if (auto_phase & NJSC32_XPHASE_ILLEGAL) { 2537 printf("%s: njsc32_intr: Illegal phase\n", 2538 device_xname(sc->sc_dev)); 2539 } 2540 #endif 2541 2542 if (auto_phase & NJSC32_XPHASE_PAUSED_MSG_IN) { 2543 TPRINTF(("%s: njsc32_intr: Process Message In\n", 2544 device_xname(sc->sc_dev))); 2545 njsc32_msgin(sc); 2546 } 2547 2548 if (auto_phase & NJSC32_XPHASE_PAUSED_MSG_OUT) { 2549 TPRINTF(("%s: njsc32_intr: Process Message Out\n", 2550 device_xname(sc->sc_dev))); 2551 njsc32_msgout(sc); 2552 } 2553 2554 cmd = sc->sc_curcmd; 2555 if (cmd == NULL) { 2556 TPRINTF(("%s: njsc32_intr: no cmd\n", 2557 device_xname(sc->sc_dev))); 2558 goto out; 2559 } 2560 2561 if (auto_phase & 2562 (NJSC32_XPHASE_DATA_IN | NJSC32_XPHASE_DATA_OUT)) { 2563 u_int32_t sackcnt, cntoffset; 2564 2565 #ifdef NJSC32_TRACE 2566 if (auto_phase & NJSC32_XPHASE_DATA_IN) 2567 PRINTC(cmd, ("njsc32_intr: data in done\n")); 2568 if (auto_phase & NJSC32_XPHASE_DATA_OUT) 2569 PRINTC(cmd, ("njsc32_intr: data out done\n")); 2570 printf("BM %u, SGT %u, SACK %u, SAVED_ACK %u\n", 2571 njsc32_read_4(sc, NJSC32_REG_BM_CNT), 2572 njsc32_read_4(sc, NJSC32_REG_SGT_ADR), 2573 njsc32_read_4(sc, NJSC32_REG_SACK_CNT), 2574 njsc32_read_4(sc, NJSC32_REG_SAVED_ACK_CNT)); 2575 #endif 2576 2577 /* 2578 * detected parity error on data transfer? 2579 */ 2580 if (njsc32_read_1(sc, NJSC32_REG_PARITY_STATUS) & 2581 (NJSC32_PARITYSTATUS_ERROR_LSB| 2582 NJSC32_PARITYSTATUS_ERROR_MSB)) { 2583 2584 PRINTC(cmd, ("datain: parity error\n")); 2585 2586 /* clear parity error */ 2587 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL, 2588 NJSC32_PARITYCTL_CHECK_ENABLE | 2589 NJSC32_PARITYCTL_CLEAR_ERROR); 2590 2591 if (auto_phase & NJSC32_XPHASE_BUS_FREE) { 2592 /* 2593 * XXX command has already finished 2594 * -- what can we do? 2595 * 2596 * It is not clear current command 2597 * caused the error -- reset everything. 2598 */ 2599 njsc32_init(sc, 1); /* XXX */ 2600 } else { 2601 /* XXX does this case occur? */ 2602 #if 1 2603 aprint_error_dev(sc->sc_dev, "datain: parity error\n"); 2604 #endif 2605 /* 2606 * Make attention condition and try 2607 * to send Initiator Detected Error 2608 * message. 2609 */ 2610 njsc32_init_msgout(sc); 2611 njsc32_add_msgout(sc, 2612 MSG_INITIATOR_DET_ERR); 2613 njsc32_write_4(sc, 2614 NJSC32_REG_SCSI_MSG_OUT, 2615 njsc32_get_auto_msgout(sc)); 2616 /* restart autoscsi with ATN */ 2617 njsc32_write_2(sc, 2618 NJSC32_REG_COMMAND_CONTROL, 2619 NJSC32_CMD_CLEAR_CDB_FIFO_PTR | 2620 NJSC32_CMD_AUTO_COMMAND_PHASE | 2621 NJSC32_CMD_AUTO_SCSI_RESTART | 2622 NJSC32_CMD_AUTO_MSGIN_00_04 | 2623 NJSC32_CMD_AUTO_MSGIN_02 | 2624 NJSC32_CMD_AUTO_ATN); 2625 } 2626 goto out; 2627 } 2628 2629 /* 2630 * data has been transferred, and current pointer 2631 * is changed 2632 */ 2633 sackcnt = njsc32_read_4(sc, NJSC32_REG_SACK_CNT); 2634 2635 /* 2636 * The controller returns extra ACK count 2637 * if the DMA buffer is not 4byte aligned. 2638 */ 2639 cntoffset = le32toh(cmd->c_sgt[0].sg_addr) & 3; 2640 #ifdef NJSC32_DEBUG 2641 if (cntoffset != 0) { 2642 printf("sackcnt %u, cntoffset %u\n", 2643 sackcnt, cntoffset); 2644 } 2645 #endif 2646 /* advance SCSI pointer */ 2647 njsc32_set_cur_ptr(cmd, 2648 cmd->c_dp_cur + sackcnt - cntoffset); 2649 } 2650 2651 if (auto_phase & NJSC32_XPHASE_MSGOUT) { 2652 /* Message Out phase has been automatically processed */ 2653 TPRINTC(cmd, ("njsc32_intr: Message Out\n")); 2654 if ((auto_phase & NJSC32_XPHASE_PAUSED_MSG_IN) == 0 && 2655 sc->sc_msgoutlen <= NJSC32_MSGOUT_MAX_AUTO) { 2656 njsc32_init_msgout(sc); 2657 } 2658 } 2659 2660 if (auto_phase & NJSC32_XPHASE_STATUS) { 2661 /* Status phase has been automatically processed */ 2662 cmd->c_xs->status = 2663 njsc32_read_1(sc, NJSC32_REG_SCSI_CSB_IN); 2664 TPRINTC(cmd, ("njsc32_intr: Status %#x\n", 2665 cmd->c_xs->status)); 2666 } 2667 2668 if (auto_phase & NJSC32_XPHASE_BUS_FREE) { 2669 /* AutoSCSI is finished */ 2670 2671 TPRINTC(cmd, ("njsc32_intr: Bus Free\n")); 2672 2673 sc->sc_stat = NJSC32_STAT_IDLE; 2674 sc->sc_curcmd = NULL; 2675 2676 njsc32_end_auto(sc, cmd, auto_phase); 2677 } 2678 goto out; 2679 } 2680 2681 if (intr & NJSC32_IRQ_FIFO_THRESHOLD) { 2682 /* XXX We use DMA, and this shouldn't happen */ 2683 printf("%s: njsc32_intr: FIFO\n", device_xname(sc->sc_dev)); 2684 njsc32_init(sc, 1); 2685 goto out; 2686 } 2687 if (intr & NJSC32_IRQ_PCI) { 2688 /* XXX? */ 2689 printf("%s: njsc32_intr: PCI\n", device_xname(sc->sc_dev)); 2690 } 2691 if (intr & NJSC32_IRQ_BMCNTERR) { 2692 /* XXX? */ 2693 printf("%s: njsc32_intr: BM\n", device_xname(sc->sc_dev)); 2694 } 2695 2696 out: 2697 /* go next command if controller is idle */ 2698 if (sc->sc_stat == NJSC32_STAT_IDLE) 2699 njsc32_start(sc); 2700 2701 #if 0 2702 /* enable interrupts */ 2703 njsc32_write_2(sc, NJSC32_REG_IRQ, 0); 2704 #endif 2705 2706 return 1; /* processed */ 2707 }
Cache object: dd9ea841bb6c7c5cc1d032c969314fb9
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