The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/ninjascsi32reg.h

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    1 /*      $NetBSD: ninjascsi32reg.h,v 1.2 2005/12/11 12:21:28 christos Exp $      */
    2 
    3 /*-
    4  * Copyright (c) 2004 The NetBSD Foundation, Inc.
    5  * All rights reserved.
    6  *
    7  * This code is derived from software contributed to The NetBSD Foundation
    8  * by ITOH Yasufumi.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  * 3. All advertising materials mentioning features or use of this software
   19  *    must display the following acknowledgement:
   20  *      This product includes software developed by the NetBSD
   21  *      Foundation, Inc. and its contributors.
   22  * 4. Neither the name of The NetBSD Foundation nor the names of its
   23  *    contributors may be used to endorse or promote products derived
   24  *    from this software without specific prior written permission.
   25  *
   26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   36  * POSSIBILITY OF SUCH DAMAGE.
   37  */
   38 
   39 #ifndef _NJSC32REG_H_
   40 #define _NJSC32REG_H_
   41 
   42 /*
   43  * Workbit NinjaSCSI (32bit versions), Ultra Narrow SCSI3 host adapters:
   44  *      NJSC-32Bi       PCMCIA/CardBus dual mode device ("DuoSCSI")
   45  *                      (CardBus mode only)
   46  *      NJSC-32UDE      PCI/CardBus device, DualEdge transfer support
   47  */
   48 
   49 #define NJSC32_REGSIZE          128     /* size of register set */
   50 #define NJSC32_MEMOFFSET_REG    0x800   /* offset of memory mapped register */
   51 
   52 /*
   53  * Direct registers
   54  */
   55 #define NJSC32_REG_IRQ                  0x00    /* len=2 R/W */
   56 # define NJSC32_IRQ_MSG                 0x0001
   57 # define NJSC32_IRQ_IO                  0x0002
   58 # define NJSC32_IRQ_CD                  0x0004
   59 # define NJSC32_IRQ_BUS_FREE            0x0008
   60 # define NJSC32_IRQ_RESELECT            0x0010
   61 # define NJSC32_IRQ_PHASE_CHANGE        0x0020
   62 # define NJSC32_IRQ_SCSIRESET           0x0040
   63 # define NJSC32_IRQ_TIMER               0x0080
   64 # define NJSC32_IRQ_FIFO_THRESHOLD      0x0100
   65 # define NJSC32_IRQ_PCI                 0x0200
   66 # define NJSC32_IRQ_BMCNTERR            0x0400
   67 # define NJSC32_IRQ_AUTOSCSI            0x0800
   68 # define NJSC32_IRQ_MASK_PCI            0x1000
   69 # define NJSC32_IRQ_MASK_TIMER          0x2000
   70 # define NJSC32_IRQ_MASK_FIFO           0x4000
   71 # define NJSC32_IRQ_MASK_SCSI           0x8000
   72 
   73 # define NJSC32_IRQ_MASK_ALL            0xf000
   74 # define NJSC32_IRQ_INTR_PENDING        0x0ff0
   75 
   76 #define NJSC32_REG_TRANSFER             0x02    /* len=2 R/W */
   77 # define NJSC32_XFR_CB_MMIO_MODE        0x0001
   78 # define NJSC32_XFR_CB_PIO_MODE         0x0002
   79 # define NJSC32_XFR_BM_TEST             0x0004
   80 # define NJSC32_XFR_BM_TEST_DIR         0x0008
   81 # define NJSC32_XFR_DUALEDGE_ENABLE     0x0010  /* (UDE) */
   82 # define NJSC32_XFR_NO_XFER_TO_HOST     0x0020  /* (UDE) */
   83                                         /* reserved */
   84 # define NJSC32_XFR_TRANSFER_GO         0x0080
   85 # define NJSC32_XFR_BLIND_MODE          0x0100
   86 # define NJSC32_XFR_BM_START            0x0200
   87 # define NJSC32_XFR_ADVANCED_BM_WRITE   0x0400
   88 # define NJSC32_XFR_BM_SINGLE_MODE      0x0800
   89 # define NJSC32_XFR_FIFO_FULL           0x1000  /* RO */
   90 # define NJSC32_XFR_FIFO_EMPTY          0x2000  /* RO */
   91 # define NJSC32_XFR_ALL_COUNT_CLR       0x4000
   92 # define NJSC32_XFR_FIFO_TEST           0x8000
   93 
   94 #define NJSC32_REG_INDEX                0x04    /* len=1 R/W, len=2 RO */
   95 # define NJSC32_INDEX_GAREV(x)          ((x) >> 8)
   96 # define NJSC32_INDEX_GAREV_MIN         0x51
   97 
   98 #define NJSC32_REG_TIMER                0x06    /* len=2 R/W */
   99 # define NJSC32_TIMER_CNT_MASK          0x00ff
  100 # define NJSC32_TIMER_STOP              0x0100
  101 
  102 #define NJSC32_REG_DATA_LOW             0x08    /* len=2 R/W */
  103 #define NJSC32_REG_DATA_HIGH            0x0a    /* len=2 R/W */
  104 
  105 #define NJSC32_REG_FIFO_REST_CNT        0x0c    /* len=2 R/W */
  106 # define NJSC32_FIFOCNT_MASK            0x01ff
  107 # define NJSC32_FIFOCNT_LOW_WATER       0x4000
  108 # define NJSC32_FIFOCNT_HIGH_WATER      0x8000
  109 
  110 #define NJSC32_REG_SREQ_SAMPLING        0x0f    /* len=1 R/W */
  111 # define NJSC32_SREQ_SAMPLING_RATE0     0x01
  112 # define NJSC32_SREQ_SAMPLING_RATE1     0x02
  113 # define NJSC32_SREQ_SAMPLING_ENABLE    0x04
  114 
  115 # define NJSC32_SREQ_SAMPLING_1CLK      0
  116 # define NJSC32_SREQ_SAMPLING_2CLK      NJSC32_SREQ_SAMPLING_RATE0
  117 # define NJSC32_SREQ_SAMPLING_4CLK      NJSC32_SREQ_SAMPLING_RATE1
  118 
  119 #define NJSC32_REG_SCSI_BUS_CONTROL     0x10    /* len=1 R/W */
  120 # define NJSC32_SBCTL_SEL               0x01
  121 # define NJSC32_SBCTL_RST               0x02
  122 # define NJSC32_SBCTL_DATAOUT_ENABLE    0x04
  123 # define NJSC32_SBCTL_ATN               0x08
  124 # define NJSC32_SBCTL_ACK               0x10
  125 # define NJSC32_SBCTL_BSY               0x20
  126 # define NJSC32_SBCTL_AUTODIRECTION     0x40
  127 # define NJSC32_SBCTL_ACK_ENABLE        0x80
  128 
  129 #define NJSC32_REG_CLR_COUNTER          0x12    /* len=1 WO */
  130 # define NJSC32_CLRCNT_ACK              0x01
  131 # define NJSC32_CLRCNT_REQ              0x02
  132 # define NJSC32_CLRCNT_FIFO_HOST_PTR    0x04
  133 # define NJSC32_CLRCNT_FIFO_REST        0x08
  134 # define NJSC32_CLRCNT_BM               0x10
  135 # define NJSC32_CLRCNT_SAVED_ACK        0x20
  136 
  137 # define NJSC32_CLCNT_ALL               0x3f
  138 
  139 #define NJSC32_REG_SCSI_BUS_MONITOR     0x12    /* len=1 RO */
  140 # define NJSC32_BUSMON_MSG              0x01
  141 # define NJSC32_BUSMON_IO               0x02
  142 # define NJSC32_BUSMON_CD               0x04
  143 # define NJSC32_BUSMON_BSY              0x08
  144 # define NJSC32_BUSMON_ACK              0x10
  145 # define NJSC32_BUSMON_REQ              0x20
  146 # define NJSC32_BUSMON_SEL              0x40
  147 # define NJSC32_BUSMON_ATN              0x80
  148 
  149 # define NJSC32_BUSMON_BUSFREE          0x00
  150 # define NJSC32_BUSMON_COMMAND          (NJSC32_BUSMON_CD | \
  151         NJSC32_BUSMON_BSY | NJSC32_BUSMON_REQ)
  152 # define NJSC32_BUSMON_MESSAGE_IN       (NJSC32_BUSMON_MSG | \
  153         NJSC32_BUSMON_BSY | NJSC32_BUSMON_IO | NJSC32_BUSMON_CD | \
  154         NJSC32_BUSMON_REQ)
  155 # define NJSC32_BUSMON_MESSAGE_OUT      (NJSC32_BUSMON_MSG | \
  156         NJSC32_BUSMON_BSY | NJSC32_BUSMON_CD | NJSC32_BUSMON_REQ)
  157 # define NJSC32_BUSMON_DATA_IN          (NJSC32_BUSMON_IO | \
  158         NJSC32_BUSMON_BSY | NJSC32_BUSMON_REQ)
  159 # define NJSC32_BUSMON_DATA_OUT (NJSC32_BUSMON_BSY | \
  160         NJSC32_BUSMON_REQ)
  161 # define NJSC32_BUSMON_STATUS           (NJSC32_BUSMON_IO | \
  162         NJSC32_BUSMON_CD | NJSC32_BUSMON_BSY | NJSC32_BUSMON_REQ)
  163 # define NJSC32_BUSMON_RESELECT (NJSC32_BUSMON_IO | NJSC32_BUSMON_SEL)
  164 
  165 # define NJSC32_BUSMON_PHASE_MASK       (NJSC32_BUSMON_MSG | \
  166         NJSC32_BUSMON_IO | NJSC32_BUSMON_BSY | NJSC32_BUSMON_CD | \
  167         NJSC32_BUSMON_SEL)
  168 
  169 # define NJSC32_PHASE_BUSFREE           \
  170         (NJSC32_BUSMON_BUSFREE & NJSC32_BUSMON_PHASE_MASK)
  171 # define NJSC32_PHASE_COMMAND           \
  172         (NJSC32_BUSMON_COMMAND & NJSC32_BUSMON_PHASE_MASK)
  173 # define NJSC32_PHASE_MESSAGE_IN        \
  174         (NJSC32_BUSMON_MESSAGE_IN & NJSC32_BUSMON_PHASE_MASK)
  175 # define NJSC32_PHASE_MESSAGE_OUT       \
  176         (NJSC32_BUSMON_MESSAGE_OUT & NJSC32_BUSMON_PHASE_MASK)
  177 # define NJSC32_PHASE_DATA_IN           \
  178         (NJSC32_BUSMON_DATA_IN & NJSC32_BUSMON_PHASE_MASK)
  179 # define NJSC32_PHASE_DATA_OUT          \
  180         (NJSC32_BUSMON_DATA_OUT & NJSC32_BUSMON_PHASE_MASK)
  181 # define NJSC32_PHASE_STATUS            \
  182         (NJSC32_BUSMON_STATUS & NJSC32_BUSMON_PHASE_MASK)
  183 # define NJSC32_PHASE_RESELECT          \
  184         (NJSC32_BUSMON_RESELECT & NJSC32_BUSMON_PHASE_MASK)
  185 
  186 #define NJSC32_REG_COMMAND_DATA         0x14    /* len=1 R/W */
  187 
  188 #define NJSC32_REG_PARITY_CONTROL       0x16    /* len=1 WO */
  189 # define NJSC32_PARITYCTL_CHECK_ENABLE  0x01
  190 # define NJSC32_PARITYCTL_CLEAR_ERROR   0x02
  191 
  192 #define NJSC32_REG_PARITY_STATUS        0x16    /* len=1 RO */
  193 # define NJSC32_PARITYSTATUS_ERROR_LSB  0x02
  194 # define NJSC32_PARITYSTATUS_ERROR_MSB  0x04    /* (UDE) */
  195 
  196 #define NJSC32_REG_RESELECT_ID          0x18    /* len=1 RO */
  197 
  198 #define NJSC32_REG_COMMAND_CONTROL      0x18    /* len=2 WO */
  199 # define NJSC32_CMD_CLEAR_CDB_FIFO_PTR  0x0001
  200 # define NJSC32_CMD_AUTO_COMMAND_PHASE  0x0002
  201 # define NJSC32_CMD_AUTO_SCSI_START     0x0004
  202 # define NJSC32_CMD_AUTO_SCSI_RESTART   0x0008
  203 # define NJSC32_CMD_AUTO_PARAMETER      0x0010  /* load parameters via DMA */
  204 # define NJSC32_CMD_AUTO_ATN            0x0020
  205 # define NJSC32_CMD_AUTO_MSGIN_00_04    0x0040  /* Command Complete (00)
  206                                                    or Disconnect (04) */
  207 # define NJSC32_CMD_AUTO_MSGIN_02       0x0080  /* Save Data Pointer */
  208 # define NJSC32_CMD_AUTO_MSGIN_03       0x0100  /* Restore Pointers */
  209 
  210 #define NJSC32_REG_SET_ARBITRATION      0x1a    /* len=1 WO */
  211 # define NJSC32_SETARB_GO               0x01
  212 # define NJSC32_SETARB_CLEAR            0x02
  213 
  214 #define NJSC32_REG_ARBITRATION_STAT     0x1a    /* len=1 RO */
  215 # define NJSC32_ARBSTAT_WIN             0x02
  216 # define NJSC32_ARBSTAT_FAIL            0x04
  217 # define NJSC32_ARBSTAT_AUTOPARAM_VALID 0x08
  218 # define NJSC32_ARBSTAT_SG_TABLE_VALID  0x10
  219 
  220 #define NJSC32_REG_SYNC                 0x1c    /* len=1 R/W */
  221 # define NJSC32_SYNC_VAL(periodnum, syncoffset) ((periodnum)<<4 | (syncoffset))
  222 
  223 # define NJSC32_SYNCPERIOD_ASYNC        0
  224 # define NJSC32_SYNCOFFSET_ASYNC        0
  225 # define NJSC32_SYNCOFFSET_MAX          15
  226 
  227 #define NJSC32_REG_ACK_WIDTH            0x1d    /* len=1 R/W */
  228 # define NJSC32_ACK_WIDTH_1CLK          0
  229 # define NJSC32_ACK_WIDTH_2CLK          1
  230 # define NJSC32_ACK_WIDTH_3CLK          2
  231 # define NJSC32_ACK_WIDTH_4CLK          3
  232 
  233 #define NJSC32_REG_SCSI_DATA_WITH_ACK   0x20    /* len=1 R/W */
  234 
  235 #define NJSC32_REG_SCSI_OUT_LATCH       0x22    /* len=1 W */
  236 #define NJSC32_REG_TARGET_ID            0x22    /* len=1 W */
  237 #define NJSC32_REG_DATA_IN              0x22    /* len=1 R */
  238 
  239 #define NJSC32_REG_SCAM_CONTROL         0x24    /* len=1 R/W */
  240 # define NJSC32_SCAMCTL_MSG             0x01
  241 # define NJSC32_SCAMCTL_IO              0x02
  242 # define NJSC32_SCAMCTL_CD              0x04
  243 # define NJSC32_SCAMCTL_BSY             0x08
  244 # define NJSC32_SCAMCTL_SEL             0x10
  245 # define NJSC32_SCAMCTL_XFEROK          0x20
  246 
  247 #define NJSC32_REG_SCAM_DATA            0x26    /* len=1 R/W */
  248 
  249 #define NJSC32_REG_SACK_CNT             0x28    /* len=4 R/W */
  250 
  251 #define NJSC32_REG_SREQ_CNT             0x2c    /* len=4 R/W */
  252 
  253 #define NJSC32_REG_FIFO_DATA            0x30    /* len=4 R/W */
  254 #define NJSC32_REG_FIFO_ADR             0x34    /* len=4 R/W */
  255 
  256 #define NJSC32_REG_BM_CNT               0x38    /* len=4 R/W */
  257 # define NJSC32_BMCNT_MASK              0x0001ffff
  258 
  259 #define NJSC32_REG_SGT_ADR              0x3c    /* len=4 R/W */
  260 
  261 #define NJSC32_REG_EXECUTE_PHASE        0x40    /* len=2 RO */
  262 # define NJSC32_XPHASE_COMMAND          0x0001
  263 # define NJSC32_XPHASE_DATA_IN          0x0002
  264 # define NJSC32_XPHASE_DATA_OUT         0x0004
  265 # define NJSC32_XPHASE_MSGOUT           0x0008
  266 # define NJSC32_XPHASE_STATUS           0x0010
  267 # define NJSC32_XPHASE_ILLEGAL          0x0020
  268 # define NJSC32_XPHASE_BUS_FREE         0x0040
  269 # define NJSC32_XPHASE_PAUSED_MSG_IN    0x0080
  270 # define NJSC32_XPHASE_PAUSED_MSG_OUT   0x0100
  271 # define NJSC32_XPHASE_SEL_TIMEOUT      0x0200
  272 # define NJSC32_XPHASE_MSGIN_00         0x0400  /* Command Complete */
  273 # define NJSC32_XPHASE_MSGIN_02         0x0800  /* Save Data Pointer */
  274 # define NJSC32_XPHASE_MSGIN_03         0x1000  /* Restore Pointers */
  275 # define NJSC32_XPHASE_MSGIN_04         0x2000  /* Disconnect */
  276                                         /* reserved */
  277 # define NJSC32_XPHASE_AUTOSCSI_BUSY    0x8000
  278 
  279 #define NJSC32_REG_SCSI_CSB_IN          0x42    /* len=1 RO */
  280 
  281 #define NJSC32_REG_SCSI_MSG_OUT         0x44    /* len=4 R/W */
  282 # define NJSC32_MSGOUT_COUNT_MASK       0x00000003
  283 # define NJSC32_MSGOUT_MAX_AUTO         3
  284 # define NJSC32_MSGOUT_VALID            0x00000080
  285 # define NJSC32_MSGOUT_MSG1_SHIFT       8       /* used only if cnt == 3 */
  286 # define NJSC32_MSGOUT_MSG2_SHIFT       16      /* used if cnt == 2 or 3 */
  287 # define NJSC32_MSGOUT_MSG3_SHIFT       24
  288 
  289 #define NJSC32_REG_SEL_TIMEOUT          0x48    /* len=2 R/W */
  290 
  291 #define NJSC32_REG_SAVED_ACK_CNT        0x4c    /* len=4 RO */
  292 
  293 #define NJSC32_REG_HTOS_DATA_DELAY      0x50    /* len=1 R/W (UDE) */
  294 # define NJSC32_HTOSDATADELAY_FACTOR    0x07
  295 # define NJSC32_HTOSDATADELAY_DATA_SEL  0x80
  296 
  297 #define NJSC32_REG_STOH_DATA_DELAY      0x54    /* len=1 R/W (UDE) */
  298 #define NJSC32_REG_ACK_SUM_CHECK_RD     0x58    /* len=2 RO (UDE) */
  299 #define NJSC32_REG_REQ_SUM_CHECK_RD     0x5c    /* len=2 RO (UDE) */
  300 
  301 /*
  302  * Indexed registers
  303  */
  304 #define NJSC32_IREG_CLOCK               0x00    /* len=1 R/W */
  305 # define NJSC32_CLOCK_DIV_2             0x01    /* external 20MHz (FAST SCSI)*/
  306 # define NJSC32_CLOCK_DIV_4             0x02    /* external 40MHz (Ultra SCSI)*/
  307 # define NJSC32_CLOCK_PCICLK            0x80    /* PCI 33.3MHz */
  308 
  309 #define NJSC32_IREG_TERM_PWR            0x01    /* len=1 R/W */
  310 # define NJSC32_TERMPWR_BPWR            0x01    /* supply termination power */
  311 # define NJSC32_TERMPWR_SENSE           0x02    /* RO */
  312 
  313 #define NJSC32_IREG_EXT_PORT_DDR        0x02    /* len=1 R/W */
  314 #define NJSC32_IREG_EXT_PORT            0x03    /* len=1 R/W */
  315 # define NJSC32_EXTPORT_LED_ON          0x00
  316 # define NJSC32_EXTPORT_LED_OFF         0x01
  317 
  318 #define NJSC32_IREG_IRQ_SELECT          0x04    /* len=2 R/W */
  319 # define NJSC32_IRQSEL_RESELECT         0x0001
  320 # define NJSC32_IRQSEL_PHASE_CHANGE     0x0002
  321 # define NJSC32_IRQSEL_SCSIRESET        0x0004
  322 # define NJSC32_IRQSEL_TIMER            0x0008
  323 # define NJSC32_IRQSEL_FIFO_THRESHOLD   0x0010
  324 # define NJSC32_IRQSEL_TARGET_ABORT     0x0020
  325 # define NJSC32_IRQSEL_MASTER_ABORT     0x0040
  326 # define NJSC32_IRQSEL_SERR             0x0080
  327 # define NJSC32_IRQSEL_PERR             0x0100
  328 # define NJSC32_IRQSEL_BMCNTERR         0x0200
  329 # define NJSC32_IRQSEL_AUTO_SCSI_SEQ    0x0400
  330 
  331 #define NJSC32_IREG_OLD_SCSI_PHASE      0x05    /* len=1 R/W */
  332 # define NJSC32_OLDSCSI_PHASE_MSG       0x01
  333 # define NJSC32_OLDSCSI_PHASE_IO        0x02
  334 # define NJSC32_OLDSCSI_PHASE_CD        0x04
  335 # define NJSC32_OLDSCSI_PHASE_BUSY      0x08
  336 
  337 #define NJSC32_IREG_FIFO_THRESHOLD_FULL         0x06    /* len=1 R/W */
  338 # define NJSC32_FIFO_FULL_PIO_MMIO      0x40
  339 # define NJSC32_FIFO_FULL_BUSMASTER     0x10
  340 #define NJSC32_IREG_FIFO_THRESHOLD_EMPTY        0x07    /* len=1 R/W */
  341 # define NJSC32_FIFO_EMPTY_PIO_MMIO     0x40
  342 # define NJSC32_FIFO_EMPTY_BUSMASTER    0x60
  343 
  344 #define NJSC32_IREG_EXP_ROM             0x08    /* len=1 R/W */
  345 # define NJSC32_EXPROM_WRITE_ENB        0x01
  346 # define NJSC32_EXPROM_IO_ACCESS_ENB    0x02
  347 # define NJSC32_EXPROM_ADR_CLEAR        0x04
  348 
  349 #define NJSC32_IREG_EXP_ROM_ADR         0x09    /* len=1 R/W */
  350 #define NJSC32_IREG_EXP_ROM_DATA        0x0a    /* len=1 R/W */
  351 
  352 #define NJSC32_IREG_CHIP_MODE           0x0b    /* len=1 RO (Bi only)*/
  353 # define NJSC32_CHIPMODE_OEM_MASK       0x06
  354 #  define NJSC32_CHIPMODE_OEM_IODATA    0x00    /* I-O DATA */
  355 #  define NJSC32_CHIPMODE_OEM_KME       0x02    /* Kyushu Matsushita Electric */
  356 #  define NJSC32_CHIPMODE_OEM_WORKBIT   0x04    /* Workbit */
  357 #  define NJSC32_CHIPMODE_OEM_EXTROM    0x06
  358 # define NJSC32_CHIPMODE_OPTB           0x08
  359 # define NJSC32_CHIPMODE_OPTC           0x10
  360 # define NJSC32_CHIPMODE_OPTD           0x20
  361 # define NJSC32_CHIPMODE_OPTE           0x40
  362 # define NJSC32_CHIPMODE_OPTF           0x80
  363 
  364 #define NJSC32_IREG_MISC                0x0c    /* len=2 R/W */
  365 # define NJSC32_MISC_SCSI_DIRECTION_DETECTOR_SELECT     0x0001
  366 # define NJSC32_MISC_SCSI2HOST_DIRECTION_VALID          0x0002  /* RO */
  367 # define NJSC32_MISC_HOST2SCSI_DIRECTION_VALID          0x0004  /* RO */
  368 # define NJSC32_MISC_DELAYED_BMSTART                    0x0008
  369 # define NJSC32_MISC_MASTER_TERMINATION_SELECT          0x0010
  370 # define NJSC32_MISC_BMREQ_NEGATE_TIMING_SEL            0x0020
  371 # define NJSC32_MISC_AUTOSEL_TIMING_SEL                 0x0040
  372 # define NJSC32_MISC_MABORT_MASK                        0x0080  /* (UDE) */
  373 # define NJSC32_MISC_BMSTOP_CHANGE2_NONDATA_PHASE       0x0100  /* (UDE) */
  374 
  375 #define NJSC32_IREG_BM                  0x0d    /* len=1 R/W */
  376 # define NJSC32_BM_CYCLE0                       0x01
  377 # define NJSC32_BM_CYCLE1                       0x02
  378 # define NJSC32_BM_FRAME_ASSERT_TIMING          0x04
  379 # define NJSC32_BM_IRDY_ASSERT_TIMING           0x08
  380 # define NJSC32_BM_SINGLE_MASTER                0x10
  381 # define NJSC32_BM_MEMRD_CMD0                   0x20
  382 # define NJSC32_BM_SGT_AUTO_PARA_MEMRD_CMD      0x40
  383 # define NJSC32_BM_MEMRD_CMD1                   0x80
  384 
  385 #define NJSC32_IREG_UP_CNT              0x0f    /* len=1 WO */
  386 # define NJSC32_UPCNT_REQCNT            0x01
  387 # define NJSC32_UPCNT_ACKCNT            0x02
  388 # define NJSC32_UPCNT_BMADR             0x10
  389 # define NJSC32_UPCNT_BMCNT             0x20
  390 # define NJSC32_UPCNT_SGTCNT            0x80
  391 
  392 #define NJSC32_IREG_CFG_CMD_STR         0x10    /* len=2 RO */
  393 
  394 #define NJSC32_IREG_CFG_LATE_CACHE      0x11    /* len=2 R/W */
  395 
  396 #define NJSC32_IREG_CFG_BASE_ADR1       0x12    /* len=2 RO */
  397 #define NJSC32_IREG_CFG_BASE_ADR2       0x13    /* len=2 RO */
  398 
  399 #define NJSC32_IREG_CFG_INLINE          0x14    /* len=2 RO */
  400 
  401 #define NJSC32_IREG_SERIAL_ROM          0x15    /* len=1 R/W (UDE) */
  402 # define NJSC32_SERIALROM_CLOCK         0x01
  403 # define NJSC32_SERIALROM_ENABLE        0x02
  404 # define NJSC32_SERIALROM_DATA          0x04
  405 
  406 #define NJSC32_IREG_HST_POINTER 0x16    /* len=1 R/W */
  407 
  408 #define NJSC32_IREG_SREQ_DELAY          0x17    /* len=1 R/W (UDE) */
  409 #define NJSC32_IREG_SACK_DELAY          0x18    /* len=1 R/W (UDE) */
  410 #define NJSC32_IREG_SREQ_NOISE_CANCEL   0x19    /* len=1 R/W (UDE) */
  411 #define NJSC32_IREG_SDP_NOISE_CANCEL    0x1a    /* len=1 R/W (UDE) */
  412 #define NJSC32_IREG_DELAY_TEST          0x1b    /* len=1 R/W (UDE) */
  413 #define NJSC32_IREG_SD0_NOISE_CANCEL    0x20    /* len=1 R/W (UDE) */
  414 #define NJSC32_IREG_SD1_NOISE_CANCEL    0x21    /* len=1 R/W (UDE) */
  415 #define NJSC32_IREG_SD2_NOISE_CANCEL    0x22    /* len=1 R/W (UDE) */
  416 #define NJSC32_IREG_SD3_NOISE_CANCEL    0x23    /* len=1 R/W (UDE) */
  417 #define NJSC32_IREG_SD4_NOISE_CANCEL    0x24    /* len=1 R/W (UDE) */
  418 #define NJSC32_IREG_SD5_NOISE_CANCEL    0x25    /* len=1 R/W (UDE) */
  419 #define NJSC32_IREG_SD6_NOISE_CANCEL    0x26    /* len=1 R/W (UDE) */
  420 #define NJSC32_IREG_SD7_NOISE_CANCEL    0x27    /* len=1 R/W (UDE) */
  421 
  422 /*
  423  * DMA data structure
  424  */
  425 
  426 /* scatter/gather transfer table entry (8 bytes) */
  427 struct njsc32_sgtable {
  428         u_int32_t       sg_addr;        /* transfer address (little endian) */
  429         u_int32_t       sg_len;         /* transfer length (little endian) */
  430 #define NJSC32_SGT_ENDMARK      0x80000000
  431 #define NJSC32_SGT_MAXSEGLEN    0x10000
  432 };
  433 #define NJSC32_SGT_MAXENTRY     18
  434 
  435 /* autoparam (88 bytes) */
  436 #define NJSC32_AUTOPARAM_CDBLEN 16
  437 struct njsc32_autoparam {
  438         struct njsc32_autoparam_cdb {
  439                 u_int8_t        cdb_data;
  440                 u_int8_t        cdb_reserved0, cdb_reserved1, cdb_reserved2;
  441         } ap_cdb[NJSC32_AUTOPARAM_CDBLEN];      /* Command Descriptor Block */
  442         u_int32_t       ap_msgout;      /* msgout buffer (little endian) */
  443         u_int8_t        ap_sync;        /* NJSC32_REG_SYNC */
  444         u_int8_t        ap_ackwidth;    /* NJSC32_REG_ACK_WIDTH */
  445         u_int8_t        ap_targetid;    /* initiator and target id */
  446         u_int8_t        ap_sample;      /* NJSC32_REG_SREQ_SAMPLING */
  447         u_int16_t       ap_cmdctl;      /* command control (little endian) */
  448         u_int16_t       ap_xferctl;     /* transfer control (little endian) */
  449         u_int32_t       ap_sgtdmaaddr;  /* SG table addr (little endian) */
  450         u_int32_t       ap_pad[2];
  451 };
  452 
  453 /*
  454  * device specific constants
  455  */
  456 
  457 #define NJSC32_NTARGET          8       /* Narrow SCSI */
  458 #define NJSC32_NLU              8
  459 
  460 #define NJSC32_INITIATOR_ID     7       /* fixed value? */
  461 #define NJSC32_MAX_TARGET_ID    6       /* 0..6 */
  462 
  463 #endif  /* _NJSC32REG_H_ */

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