FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/ns16550.h
1 /*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91
34 * $FreeBSD: releng/5.2/sys/dev/ic/ns16550.h 120124 2003-09-16 14:21:17Z bde $
35 */
36
37 /*
38 * NS8250... UART registers.
39 */
40
41 /* 8250 registers #[0-6]. */
42
43 #define com_data 0 /* data register (R/W) */
44 #define com_thr com_data /* transmitter holding register (W) */
45 #define com_rhr com_data /* receiver holding register (R) */
46
47 #define com_ier 1 /* interrupt enable register (W) */
48 #define IER_ERXRDY 0x1
49 #define IER_ETXRDY 0x2
50 #define IER_ERLS 0x4
51 #define IER_EMSC 0x8
52
53 #define com_iir 2 /* interrupt identification register (R) */
54 #define com_isr com_iir /* interrupt status register (R) */
55 #define IIR_IMASK 0xf
56 #define IIR_RXTOUT 0xc
57 #define IIR_RLS 0x6
58 #define IIR_RXRDY 0x4
59 #define IIR_TXRDY 0x2
60 #define IIR_NOPEND 0x1
61 #define IIR_MLSC 0x0
62 #define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
63
64 #define com_lcr 3 /* line control register (R/W) */
65 #define com_lctl com_lcr
66 #define com_cfcr com_lcr /* character format control register (R/W) */
67 #define LCR_DLAB 0x80
68 #define CFCR_DLAB LCR_DLAB
69 #define LCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */
70 #define CFCR_EFR_ENABLE LCR_EFR_ENABLE
71 #define CFCR_SBREAK 0x40
72 #define CFCR_PZERO 0x30
73 #define CFCR_PONE 0x20
74 #define CFCR_PEVEN 0x10
75 #define CFCR_PODD 0x00
76 #define CFCR_PENAB 0x08
77 #define CFCR_STOPB 0x04
78 #define CFCR_8BITS 0x03
79 #define CFCR_7BITS 0x02
80 #define CFCR_6BITS 0x01
81 #define CFCR_5BITS 0x00
82
83 #define com_mcr 4 /* modem control register (R/W) */
84 #define MCR_PRESCALE 0x80 /* only available on 16650 up */
85 #define MCR_LOOPBACK 0x10
86 #define MCR_IENABLE 0x08
87 #define MCR_DRS 0x04
88 #define MCR_RTS 0x02
89 #define MCR_DTR 0x01
90
91 #define com_lsr 5 /* line status register (R/W) */
92 #define LSR_RCV_FIFO 0x80
93 #define LSR_TSRE 0x40
94 #define LSR_TXRDY 0x20
95 #define LSR_BI 0x10
96 #define LSR_FE 0x08
97 #define LSR_PE 0x04
98 #define LSR_OE 0x02
99 #define LSR_RXRDY 0x01
100 #define LSR_RCV_MASK 0x1f
101
102 #define com_msr 6 /* modem status register (R/W) */
103 #define MSR_DCD 0x80
104 #define MSR_RI 0x40
105 #define MSR_DSR 0x20
106 #define MSR_CTS 0x10
107 #define MSR_DDCD 0x08
108 #define MSR_TERI 0x04
109 #define MSR_DDSR 0x02
110 #define MSR_DCTS 0x01
111
112 /* 8250 multiplexed registers #[0-1]. Access enabled by LCR[7]. */
113 #define com_dll 0 /* divisor latch low (R/W) */
114 #define com_dlbl com_dll
115 #define com_dlm 1 /* divisor latch high (R/W) */
116 #define com_dlbh com_dlm
117
118 /* 16450 register #7. Not multiplexed. */
119 #define com_scr 7 /* scratch register (R/W) */
120
121 /* 16550 register #2. Not multiplexed. */
122 #define com_fcr 2 /* FIFO control register (W) */
123 #define com_fifo com_fcr
124 #define FIFO_ENABLE 0x01
125 #define FIFO_RCV_RST 0x02
126 #define FIFO_XMT_RST 0x04
127 #define FIFO_DMA_MODE 0x08
128 #define FIFO_RX_LOW 0x00
129 #define FIFO_RX_MEDL 0x40
130 #define FIFO_RX_MEDH 0x80
131 #define FIFO_RX_HIGH 0xc0
132
133 /* 16650 registers #2,[4-7]. Access enabled by LCR_EFR_ENABLE. */
134
135 #define com_efr 2 /* enhanced features register (R/W) */
136 #define EFR_AUTOCTS 0x80
137 #define EFR_AUTORTS 0x40
138 #define EFR_EFE 0x10 /* enhanced functions enable */
139
140 #define com_xon1 4 /* XON 1 character (R/W) */
141 #define com_xon2 5 /* XON 2 character (R/W) */
142 #define com_xoff1 6 /* XOFF 1 character (R/W) */
143 #define com_xoff2 7 /* XOFF 2 character (R/W) */
144
145 /* 16950 register #1. Access enabled by ACR[7]. Also requires !LCR[7]. */
146 #define com_asr 1 /* additional status register (R[0-7]/W[0-1]) */
147
148 /* 16950 register #3. R/W access enabled by ACR[7]. */
149 #define com_rfl 3 /* receiver fifo level (R) */
150
151 /*
152 * 16950 register #4. Access enabled by ACR[7]. Also requires
153 * !LCR_EFR_ENABLE.
154 */
155 #define com_tfl 4 /* transmitter fifo level (R) */
156
157 /*
158 * 16950 register #5. Accessible if !LCR_EFR_ENABLE. Read access also
159 * requires ACR[6].
160 */
161 #define com_icr 5 /* index control register (R/W) */
162
163 /*
164 * 16950 register #7. It is the same as com_scr except it has a different
165 * abbreviation in the manufacturer's data sheet and it also serves as an
166 * index into the Indexed Control register set.
167 */
168 #define com_spr com_scr /* scratch pad (and index) register (R/W) */
169
170 /*
171 * 16950 indexed control registers #[0-0x13]. Access is via index in SPR,
172 * data in ICR (if ICR is accessible).
173 */
174
175 #define com_acr 0 /* additional control register (R/W) */
176 #define ACR_ASE 0x80 /* ASR/RFL/TFL enable */
177 #define ACR_ICRE 0x40 /* ICR enable */
178 #define ACR_TLE 0x20 /* TTL/RTL enable */
179
180 #define com_cpr 1 /* clock prescaler register (R/W) */
181 #define com_tcr 2 /* times clock register (R/W) */
182 #define com_ttl 4 /* transmitter trigger level (R/W) */
183 #define com_rtl 5 /* receiver trigger level (R/W) */
184 /* ... */
185
186 #ifdef PC98
187 /* Hardware extension mode register for RSB-2000/3000. */
188 #define com_emr com_msr
189 #define EMR_EXBUFF 0x04
190 #define EMR_CTSFLW 0x08
191 #define EMR_DSRFLW 0x10
192 #define EMR_RTSFLW 0x20
193 #define EMR_DTRFLW 0x40
194 #define EMR_EFMODE 0x80
195 #endif
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