FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/nslm7xvar.h
1 /* $NetBSD: nslm7xvar.h,v 1.34 2018/02/08 09:05:19 dholland Exp $ */
2
3 /*-
4 * Copyright (c) 2000 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Bill Squier.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #ifndef _DEV_ISA_NSLM7XVAR_H_
33 #define _DEV_ISA_NSLM7XVAR_H_
34
35 #include <dev/sysmon/sysmonvar.h>
36
37 /*
38 * National Semiconductor LM78/79/81 registers.
39 */
40
41 /* Control registers */
42
43 #define LMC_ADDR 0x05
44 #define LMC_DATA 0x06
45
46 /* Data registers */
47
48 #define LMD_POST_RAM 0x00 /* POST RAM occupies 0x00 -- 0x1f */
49 #define LMD_VALUE_RAM 0x20 /* Value RAM occupies 0x20 -- 0x3f */
50 #define LMD_FAN1 0x28 /* FAN1 reading */
51 #define LMD_FAN2 0x29 /* FAN2 reading */
52 #define LMD_FAN3 0x2a /* FAN3 reading */
53
54 #define LMD_CONFIG 0x40 /* Configuration */
55 #define LMD_ISR1 0x41 /* Interrupt Status 1 */
56 #define LMD_ISR2 0x42 /* Interrupt Status 2 */
57 #define LMD_SMI1 0x43 /* SMI Mask 1 */
58 #define LMD_SMI2 0x44 /* SMI Mask 2 */
59 #define LMD_NMI1 0x45 /* NMI Mask 1 */
60 #define LMD_NMI2 0x46 /* NMI Mask 2 */
61 #define LMD_VIDFAN 0x47 /* VID/Fan Divisor */
62 #define LMD_SBUSADDR 0x48 /* Serial Bus Address */
63 #define LMD_CHIPID 0x49 /* Chip Reset/ID */
64
65 /* Chip IDs */
66
67 #define LM_NUM_SENSORS 11
68 #define LM_ID_LM78 0x00
69 #define LM_ID_LM78J 0x40
70 #define LM_ID_LM79 0xC0
71 #define LM_ID_LM81 0x80
72 #define LM_ID_MASK 0xFE
73
74
75 /*
76 * Winbond registers
77 *
78 * Several models exists. The W83781D is mostly compatible with the
79 * LM78, but has two extra temperatures. Later models add extra
80 * voltage sensors, fans and bigger fan divisors to accommodate slow
81 * running fans. To accommodate the extra sensors some models have
82 * different memory banks.
83 */
84
85 #define WB_T23ADDR 0x4a /* Temperature 2 and 3 Serial Bus Address */
86 #define WB_PIN 0x4b /* Pin Control */
87 #define WB_BANKSEL 0x4e /* Bank Select */
88 #define WB_VENDID 0x4f /* Vendor ID */
89 #define WB_NCT6102_VENDID 0xfe /* Vendor ID for NCT610[246] */
90
91 /* Bank 0 regs */
92 #define WB_BANK0_CHIPID 0x58 /* Chip ID */
93 #define WB_BANK0_RESVD1 0x59 /* Resvd, bits 6-4 select temp sensor mode */
94 #define WB_BANK0_FAN45 0x5c /* Fan 4/5 Divisor Control (W83791D only) */
95 #define WB_BANK0_VBAT 0x5d /* VBAT Monitor Control */
96 #define WB_BANK0_FAN4 0xba /* Fan 4 reading (W83791D only) */
97 #define WB_BANK0_FAN5 0xbb /* Fan 5 reading (W83791D only) */
98
99 #define WB_BANK0_CONFIG 0x18 /* VRM & OVT Config (W83627THF/W83637HF) */
100 #define WB_BANK0_NCT6102_CHIPID 0xff /* Chip ID for NCT610[246] */
101
102 /* Bank 1 registers */
103 #define WB_BANK1_T2H 0x50 /* Temperature 2 High Byte */
104 #define WB_BANK1_T2L 0x51 /* Temperature 2 Low Byte */
105
106 /* Bank 2 registers */
107 #define WB_BANK2_T3H 0x50 /* Temperature 3 High Byte */
108 #define WB_BANK2_T3L 0x51 /* Temperature 3 Low Byte */
109
110 /* Bank 4 registers (W83782D/W83627HF and later models only) */
111 #define WB_BANK4_T1OFF 0x54 /* Temperature 1 Offset */
112 #define WB_BANK4_T2OFF 0x55 /* Temperature 2 Offset */
113 #define WB_BANK4_T3OFF 0x56 /* Temperature 3 Offset */
114
115 /* Bank 5 registers (W83782D/W83627HF and later models only) */
116 #define WB_BANK5_5VSB 0x50 /* 5VSB reading */
117 #define WB_BANK5_VBAT 0x51 /* VBAT reading */
118
119 /* Bank selection */
120 #define WB_BANKSEL_B0 0x00 /* Bank 0 */
121 #define WB_BANKSEL_B1 0x01 /* Bank 1 */
122 #define WB_BANKSEL_B2 0x02 /* Bank 2 */
123 #define WB_BANKSEL_B3 0x03 /* Bank 3 */
124 #define WB_BANKSEL_B4 0x04 /* Bank 4 */
125 #define WB_BANKSEL_B5 0x05 /* Bank 5 */
126 #define WB_BANKSEL_HBAC 0x80 /* Register 0x4f High Byte Access */
127
128 /* Vendor IDs */
129 #define WB_VENDID_WINBOND 0x5ca3 /* Winbond */
130 #define WB_VENDID_ASUS 0x12c3 /* ASUS */
131
132 /* Chip IDs */
133 #define WB_CHIPID_W83781D 0x10
134 #define WB_CHIPID_W83781D_2 0x11
135 #define WB_CHIPID_W83627HF 0x21
136 #define WB_CHIPID_AS99127F 0x31 /* Asus W83781D clone */
137 #define WB_CHIPID_W83782D 0x30
138 #define WB_CHIPID_W83783S 0x40
139 #define WB_CHIPID_W83697HF 0x60
140 #define WB_CHIPID_W83791D 0x71
141 #define WB_CHIPID_W83791SD 0x72
142 #define WB_CHIPID_W83792D 0x7a
143 #define WB_CHIPID_W83637HF 0x80
144 #define WB_CHIPID_W83627EHF_A 0x88 /* early version, only for ASUS MBs */
145 #define WB_CHIPID_W83627THF 0x90
146 #define WB_CHIPID_W83627EHF 0xa1
147 #define WB_CHIPID_W83627DHG 0xc1
148
149 /* Config bits */
150 #define WB_CONFIG_VMR9 0x01
151
152 /* Reference voltage (mV) */
153 #define WB_VREF 3600
154 #define WB_W83627EHF_VREF 2048
155
156 #define WB_MAX_SENSORS 36
157
158 struct lm_softc {
159 device_t sc_dev;
160
161 callout_t sc_callout;
162
163 envsys_data_t sensors[WB_MAX_SENSORS];
164 struct sysmon_envsys *sc_sme;
165 uint8_t numsensors;
166
167 void (*refresh_sensor_data)(struct lm_softc *);
168
169 uint8_t (*lm_readreg)(struct lm_softc *, int);
170 void (*lm_writereg)(struct lm_softc *, int, uint8_t);
171
172 const struct lm_sensor *lm_sensors;
173 uint8_t chipid;
174 uint8_t vrm9;
175 uint16_t sioid;
176 };
177
178 struct lm_sensor {
179 const char *desc;
180 enum envsys_units type;
181 uint8_t bank;
182 uint8_t reg;
183 void (*refresh)(struct lm_softc *, int);
184 int rfact;
185 };
186
187 struct wb_product {
188 uint16_t id; /* WB_CHIPID(8b) or WBSIO_ID(16b) or WB_VENDID(16b) */
189 const char *str;
190 const struct lm_sensor *sensors;
191 void (*extattach)(struct lm_softc *);
192 };
193
194 int lm_match(struct lm_softc *);
195 void lm_attach(struct lm_softc *);
196 void lm_detach(struct lm_softc *);
197
198 #endif /* _DEV_ISA_NSLM7XVAR_H_ */
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