The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/osiopreg.h

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    1 /*      $NetBSD: osiopreg.h,v 1.5 2005/12/11 12:21:28 christos Exp $    */
    2 
    3 /*
    4  * Copyright (c) 1990 The Regents of the University of California.
    5  * All rights reserved.
    6  *
    7  * This code is derived from software contributed to Berkeley by
    8  * Van Jacobson of Lawrence Berkeley Laboratory.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  * 3. Neither the name of the University nor the names of its contributors
   19  *    may be used to endorse or promote products derived from this software
   20  *    without specific prior written permission.
   21  *
   22  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   25  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   32  * SUCH DAMAGE.
   33  *
   34  *      @(#)siopreg.h   7.3 (Berkeley) 2/5/91
   35  */
   36 
   37 /*
   38  * NCR 53C710 SCSI interface hardware description.
   39  *
   40  * From the Mach scsi driver for the 53C710 and amiga siop driver
   41  */
   42 
   43 /* byte lane definitions */
   44 #if BYTE_ORDER == LITTLE_ENDIAN
   45 #define BL0     0
   46 #define BL1     1
   47 #define BL2     2
   48 #define BL3     3
   49 #else
   50 #define BL0     3
   51 #define BL1     2
   52 #define BL2     1
   53 #define BL3     0
   54 #endif
   55 
   56 #define OSIOP_SCNTL0    (0x00+BL0)      /* rw: SCSI control reg 0 */
   57 #define OSIOP_SCNTL1    (0x00+BL1)      /* rw: SCSI control reg 1 */
   58 #define OSIOP_SDID      (0x00+BL2)      /* rw: SCSI destination ID */
   59 #define OSIOP_SIEN      (0x00+BL3)      /* rw: SCSI interrupt enable */
   60 
   61 #define OSIOP_SCID      (0x04+BL0)      /* rw: SCSI Chip ID reg */
   62 #define OSIOP_SXFER     (0x04+BL1)      /* rw: SCSI Transfer reg */
   63 #define OSIOP_SODL      (0x04+BL2)      /* rw: SCSI Output Data Latch */
   64 #define OSIOP_SOCL      (0x04+BL3)      /* rw: SCSI Output Control Latch */
   65 
   66 #define OSIOP_SFBR      (0x08+BL0)      /* ro: SCSI First Byte Received */
   67 #define OSIOP_SIDL      (0x08+BL1)      /* ro: SCSI Input Data Latch */
   68 #define OSIOP_SBDL      (0x08+BL2)      /* ro: SCSI Bus Data Lines */
   69 #define OSIOP_SBCL      (0x08+BL3)      /* rw: SCSI Bus Control Lines */
   70 
   71 #define OSIOP_DSTAT     (0x0c+BL0)      /* ro: DMA status */
   72 #define OSIOP_SSTAT0    (0x0c+BL1)      /* ro: SCSI status reg 0 */
   73 #define OSIOP_SSTAT1    (0x0c+BL2)      /* ro: SCSI status reg 1 */
   74 #define OSIOP_SSTAT2    (0x0c+BL3)      /* ro: SCSI status reg 2 */
   75 
   76 #define OSIOP_DSA       0x10            /* rw: Data Structure Address */
   77 
   78 #define OSIOP_CTEST0    (0x14+BL0)      /* ro: Chip test register 0 */
   79 #define OSIOP_CTEST1    (0x14+BL1)      /* ro: Chip test register 1 */
   80 #define OSIOP_CTEST2    (0x14+BL2)      /* ro: Chip test register 2 */
   81 #define OSIOP_CTEST3    (0x14+BL3)      /* ro: Chip test register 3 */
   82 
   83 #define OSIOP_CTEST4    (0x18+BL0)      /* rw: Chip test register 4 */
   84 #define OSIOP_CTEST5    (0x18+BL1)      /* rw: Chip test register 5 */
   85 #define OSIOP_CTEST6    (0x18+BL2)      /* rw: Chip test register 6 */
   86 #define OSIOP_CTEST7    (0x18+BL3)      /* rw: Chip test register 7 */
   87 
   88 #define OSIOP_TEMP      0x1c            /* rw: Temporary Stack reg */
   89 
   90 #define OSIOP_DFIFO     (0x20+BL0)      /* rw: DMA FIFO */
   91 #define OSIOP_ISTAT     (0x20+BL1)      /* rw: Interrupt Status reg */
   92 #define OSIOP_CTEST8    (0x20+BL2)      /* rw: Chip test register 8 */
   93 #define OSIOP_LCRC      (0x20+BL3)      /* rw: LCRC value */
   94 
   95 #define OSIOP_DBC       0x24            /* rw: DMA Counter reg (longword) */
   96 #define OSIOP_DBC0      (0x24+BL0)      /* rw: DMA Byte Counter reg 0 */
   97 #define OSIOP_DBC1      (0x24+BL1)      /* rw: DMA Byte Counter reg 1 */
   98 #define OSIOP_DBC2      (0x24+BL2)      /* rw: DMA Byte Counter reg 2 */
   99 #define OSIOP_DCMD      (0x24+BL3)      /* rw: DMA Command Register */
  100 
  101 #define OSIOP_DNAD      0x28            /* rw: DMA Next Data Address */
  102 
  103 #define OSIOP_DSP       0x2c            /* rw: DMA SCRIPTS Pointer reg */
  104 
  105 #define OSIOP_DSPS      0x30            /* rw: DMA SCRIPTS Pointer Save reg */
  106 
  107 #define OSIOP_SCRATCH   0x34            /* rw: Scratch register */
  108 
  109 #define OSIOP_DMODE     (0x38+BL0)      /* rw: DMA Mode reg */
  110 #define OSIOP_DIEN      (0x38+BL1)      /* rw: DMA Interrupt Enable */
  111 #define OSIOP_DWT       (0x38+BL2)      /* rw: DMA Watchdog Timer */
  112 #define OSIOP_DCNTL     (0x38+BL3)      /* rw: DMA Control reg */
  113 
  114 #define OSIOP_ADDER     0x3c            /* ro: Adder Sum Output */
  115 
  116 #define OSIOP_NREGS     0x40
  117 
  118 
  119 /*
  120  * Register defines
  121  */
  122 
  123 /* Scsi control register 0 (scntl0) */
  124 
  125 #define OSIOP_SCNTL0_ARB        0xc0    /* Arbitration mode */
  126 #define  OSIOP_ARB_SIMPLE       0x00
  127 #define  OSIOP_ARB_FULL         0xc0
  128 #define OSIOP_SCNTL0_START      0x20    /* Start Sequence */
  129 #define OSIOP_SCNTL0_WATN       0x10    /* (Select) With ATN */
  130 #define OSIOP_SCNTL0_EPC        0x08    /* Enable Parity Checking */
  131 #define OSIOP_SCNTL0_EPG        0x04    /* Enable Parity Generation */
  132 #define OSIOP_SCNTL0_AAP        0x02    /* Assert ATN on Parity Error */
  133 #define OSIOP_SCNTL0_TRG        0x01    /* Target Mode */
  134 
  135 /* Scsi control register 1 (scntl1) */
  136 
  137 #define OSIOP_SCNTL1_EXC        0x80    /* Extra Clock Cycle of data setup */
  138 #define OSIOP_SCNTL1_ADB        0x40    /* Assert Data Bus */
  139 #define OSIOP_SCNTL1_ESR        0x20    /* Enable Selection/Reselection */
  140 #define OSIOP_SCNTL1_CON        0x10    /* Connected */
  141 #define OSIOP_SCNTL1_RST        0x08    /* Assert RST */
  142 #define OSIOP_SCNTL1_AESP       0x04    /* Assert even SCSI parity */
  143 #define OSIOP_SCNTL1_PAR        0x04    /* Force bad Parity */
  144 #define OSIOP_SCNTL1_RES0       0x02    /* Reserved */
  145 #define OSIOP_SCNTL1_RES1       0x01    /* Reserved */
  146 
  147 /* Scsi interrupt enable register (sien) */
  148 
  149 #define OSIOP_SIEN_M_A          0x80    /* Phase Mismatch or ATN active */
  150 #define OSIOP_SIEN_FCMP         0x40    /* Function Complete */
  151 #define OSIOP_SIEN_STO          0x20    /* (Re)Selection timeout */
  152 #define OSIOP_SIEN_SEL          0x10    /* (Re)Selected */
  153 #define OSIOP_SIEN_SGE          0x08    /* SCSI Gross Error */
  154 #define OSIOP_SIEN_UDC          0x04    /* Unexpected Disconnect */
  155 #define OSIOP_SIEN_RST          0x02    /* RST asserted */
  156 #define OSIOP_SIEN_PAR          0x01    /* Parity Error */
  157 
  158 /* Scsi chip ID (scid) */
  159 
  160 #define OSIOP_SCID_VALUE(i)     (1 << (i))
  161 
  162 /* Scsi transfer register (sxfer) */
  163 
  164 #define OSIOP_SXFER_DHP         0x80    /* Disable Halt on Parity error/
  165                                            ATN asserted */
  166 #define OSIOP_SXFER_TP          0x70    /* Synch Transfer Period */
  167                                         /* see specs for formulas:
  168                                                 Period = TCP * (4 + XFERP )
  169                                                 TCP = 1 + CLK + 1..2;
  170                                          */
  171 #define OSIOP_SXFER_MO          0x0f    /* Synch Max Offset */
  172 #define  OSIOP_MAX_OFFSET       8
  173 
  174 /* Scsi output data latch register (sodl) */
  175 
  176 /* Scsi output control latch register (socl) */
  177 
  178 #define OSIOP_REQ               0x80    /* SCSI signal <x> asserted */
  179 #define OSIOP_ACK               0x40
  180 #define OSIOP_BSY               0x20
  181 #define OSIOP_SEL               0x10
  182 #define OSIOP_ATN               0x08
  183 #define OSIOP_MSG               0x04
  184 #define OSIOP_CD                0x02
  185 #define OSIOP_IO                0x01
  186 
  187 #define OSIOP_PHASE(x)          ((x) & (OSIOP_MSG|OSIOP_CD|OSIOP_IO))
  188 #define DATA_OUT_PHASE          0x00
  189 #define DATA_IN_PHASE           OSIOP_IO
  190 #define COMMAND_PHASE           OSIOP_CD
  191 #define STATUS_PHASE            (OSIOP_CD|OSIOP_IO)
  192 #define MSG_OUT_PHASE           (OSIOP_MSG|OSIOP_CD)
  193 #define MSG_IN_PHASE            (OSIOP_MSG|OSIOP_CD|OSIOP_IO)
  194 
  195 /* Scsi first byte received register (sfbr) */
  196 
  197 /* Scsi input data latch register (sidl) */
  198 
  199 /* Scsi bus data lines register (sbdl) */
  200 
  201 /* Scsi bus control lines register (sbcl).  Same as socl */
  202 
  203 #define OSIOP_SBCL_SSCF1        0x02    /* wo */
  204 #define OSIOP_SBCL_SSCF0        0x01    /* wo */
  205 
  206 /* DMA status register (dstat) */
  207 
  208 #define OSIOP_DSTAT_DFE         0x80    /* DMA FIFO empty */
  209 #define OSIOP_DSTAT_RES         0x40
  210 #define OSIOP_DSTAT_BF          0x20    /* Bus fault */
  211 #define OSIOP_DSTAT_ABRT        0x10    /* Aborted */
  212 #define OSIOP_DSTAT_SSI         0x08    /* SCRIPT Single Step */
  213 #define OSIOP_DSTAT_SIR         0x04    /* SCRIPT Interrupt Instruction */
  214 #define OSIOP_DSTAT_WTD         0x02    /* Watchdog Timeout Detected */
  215 #define OSIOP_DSTAT_IID         0x01    /* Invalid Instruction Detected */
  216 
  217 /* Scsi status register 0 (sstat0) */
  218 
  219 #define OSIOP_SSTAT0_M_A        0x80    /* Phase Mismatch or ATN active */
  220 #define OSIOP_SSTAT0_FCMP       0x40    /* Function Complete */
  221 #define OSIOP_SSTAT0_STO        0x20    /* (Re)Selection timeout */
  222 #define OSIOP_SSTAT0_SEL        0x10    /* (Re)Selected */
  223 #define OSIOP_SSTAT0_SGE        0x08    /* SCSI Gross Error */
  224 #define OSIOP_SSTAT0_UDC        0x04    /* Unexpected Disconnect */
  225 #define OSIOP_SSTAT0_RST        0x02    /* RST asserted */
  226 #define OSIOP_SSTAT0_PAR        0x01    /* Parity Error */
  227 
  228 /* Scsi status register 1 (sstat1) */
  229 
  230 #define OSIOP_SSTAT1_ILF        0x80    /* Input latch (sidl) full */
  231 #define OSIOP_SSTAT1_ORF        0x40    /* output reg (sodr) full */
  232 #define OSIOP_SSTAT1_OLF        0x20    /* output latch (sodl) full */
  233 #define OSIOP_SSTAT1_AIP        0x10    /* Arbitration in progress */
  234 #define OSIOP_SSTAT1_LOA        0x08    /* Lost arbitration */
  235 #define OSIOP_SSTAT1_WOA        0x04    /* Won arbitration */
  236 #define OSIOP_SSTAT1_RST        0x02    /* SCSI RST current value */
  237 #define OSIOP_SSTAT1_SDP        0x01    /* SCSI SDP current value */
  238 
  239 /* Scsi status register 2 (sstat2) */
  240 
  241 #define OSIOP_SSTAT2_FF         0xf0    /* SCSI FIFO flags (bytecount) */
  242 #define  OSIOP_SCSI_FIFO_DEEP   8
  243 #define OSIOP_SSTAT2_SDP        0x08    /* Latched (on REQ) SCSI SDP */
  244 #define OSIOP_SSTAT2_MSG        0x04    /* Latched SCSI phase */
  245 #define OSIOP_SSTAT2_CD         0x02
  246 #define OSIOP_SSTAT2_IO         0x01
  247 
  248 /* Chip test register 0 (ctest0) */
  249 
  250 #define OSIOP_CTEST0_RES0       0x80
  251 #define OSIOP_CTEST0_BTD        0x40    /* Byte-to-byte Timer Disable */
  252 #define OSIOP_CTEST0_GRP        0x20    /* Generate Receive Parity */
  253 #define OSIOP_CTEST0_EAN        0x10    /* Enable Active Negation */
  254 #define OSIOP_CTEST0_HSC        0x08    /* Halt SCSI clock */
  255 #define OSIOP_CTEST0_ERF        0x04    /* Extend REQ/ACK Filtering */
  256 #define OSIOP_CTEST0_RES1       0x02
  257 #define OSIOP_CTEST0_DDIR       0x01    /* Xfer direction (1-> from SCSI bus) */
  258 
  259 
  260 /* Chip test register 1 (ctest1) */
  261 
  262 #define OSIOP_CTEST1_FMT        0xf0    /* Byte empty in DMA FIFO bottom
  263                                            (high->byte3) */
  264 #define OSIOP_CTEST1_FFL        0x0f    /* Byte full in DMA FIFO top, same */
  265 
  266 /* Chip test register 2 (ctest2) */
  267 
  268 #define OSIOP_CTEST2_RES        0x80
  269 #define OSIOP_CTEST2_SIGP       0x40    /* Signal process */
  270 #define OSIOP_CTEST2_SOFF       0x20    /* Synch Offset compare
  271                                            (1-> zero Init, max Tgt */
  272 #define OSIOP_CTEST2_SFP        0x10    /* SCSI FIFO Parity */
  273 #define OSIOP_CTEST2_DFP        0x08    /* DMA FIFO Parity */
  274 #define OSIOP_CTEST2_TEOP       0x04    /* True EOP (a-la 5380) */
  275 #define OSIOP_CTEST2_DREQ       0x02    /* DREQ status */
  276 #define OSIOP_CTEST2_DACK       0x01    /* DACK status */
  277 
  278 /* Chip test register 3 (ctest3) read-only, top of SCSI FIFO */
  279 
  280 /* Chip test register 4 (ctest4) */
  281 
  282 #define OSIOP_CTEST4_MUX        0x80    /* Host bus multiplex mode */
  283 #define OSIOP_CTEST4_ZMOD       0x40    /* High-impedance outputs */
  284 #define OSIOP_CTEST4_SZM        0x20    /* ditto, SCSI "outputs" */
  285 #define OSIOP_CTEST4_SLBE       0x10    /* SCSI loopback enable */
  286 #define OSIOP_CTEST4_SFWR       0x08    /* SCSI FIFO write enable (from sodl) */
  287 #define OSIOP_CTEST4_FBL        0x07    /* DMA FIFO Byte Lane select
  288                                            (from ctest6) 4->0, .. 7->3 */
  289 
  290 /* Chip test register 5 (ctest5) */
  291 
  292 #define OSIOP_CTEST5_ADCK       0x80    /* Clock Address Incrementor */
  293 #define OSIOP_CTEST5_BBCK       0x40    /* Clock Byte counter */
  294 #define OSIOP_CTEST5_ROFF       0x20    /* Reset SCSI offset */
  295 #define OSIOP_CTEST5_MASR       0x10    /* Master set/reset pulses
  296                                            (of bits 3-0) */
  297 #define OSIOP_CTEST5_DDIR       0x08    /* (re)set internal DMA direction */
  298 #define OSIOP_CTEST5_EOP        0x04    /* (re)set internal EOP */
  299 #define OSIOP_CTEST5_DREQ       0x02    /* (re)set internal REQ */
  300 #define OSIOP_CTEST5_DACK       0x01    /* (re)set internal ACK */
  301 
  302 /* Chip test register 6 (ctest6)  DMA FIFO access */
  303 
  304 /* Chip test register 7 (ctest7) */
  305 
  306 #define OSIOP_CTEST7_CDIS       0x80    /* Cache burst disable */
  307 #define OSIOP_CTEST7_SC1        0x40    /* Snoop control 1 */
  308 #define OSIOP_CTEST7_SC0        0x20    /* Snoop contorl 0 */
  309 #define OSIOP_CTEST7_STD        0x10    /* Selection timeout disable */
  310 #define OSIOP_CTEST7_DFP        0x08    /* DMA FIFO parity bit */
  311 #define OSIOP_CTEST7_EVP        0x04    /* Even parity (to host bus) */
  312 #define OSIOP_CTEST7_TT1        0x02    /* Transfer type bit */
  313 #define OSIOP_CTEST7_DIFF       0x01    /* Differential mode */
  314 
  315 /* DMA FIFO register (dfifo) */
  316 
  317 #define OSIOP_DFIFO_FLF         0x80    /* Flush (spill) DMA FIFO */
  318 #define OSIOP_DFIFO_BO          0x7f    /* FIFO byte offset counter */
  319 
  320 /* Interrupt status register (istat) */
  321 
  322 #define OSIOP_ISTAT_ABRT        0x80    /* Abort operation */
  323 #define OSIOP_ISTAT_RST         0x40    /* Software reset */
  324 #define OSIOP_ISTAT_SIGP        0x20    /* Signal process */
  325 #define OSIOP_ISTAT_RES         0x10
  326 #define OSIOP_ISTAT_CON         0x08    /* Connected */
  327 #define OSIOP_ISTAT_RES1        0x04
  328 #define OSIOP_ISTAT_SIP         0x02    /* SCSI Interrupt pending */
  329 #define OSIOP_ISTAT_DIP         0x01    /* DMA Interrupt pending */
  330 
  331 /* Chip test register 8 (ctest8) */
  332 
  333 #define OSIOP_CTEST8_V          0xf0    /* Chip revision level */
  334 #define OSIOP_CTEST8_FLF        0x08    /* Flush DMA FIFO */
  335 #define OSIOP_CTEST8_CLF        0x04    /* Clear DMA and SCSI FIFOs */
  336 #define OSIOP_CTEST8_FM         0x02    /* Fetch pin mode */
  337 #define OSIOP_CTEST8_SM         0x01    /* Snoop pins mode */
  338 
  339 /* DMA Mode register (dmode) */
  340 
  341 #define OSIOP_DMODE_BL_MASK     0xc0    /* DMA burst length */
  342 #define  OSIOP_DMODE_BL8        0xc0    /* 8 bytes */
  343 #define  OSIOP_DMODE_BL4        0x80    /* 4 bytes */
  344 #define  OSIOP_DMODE_BL2        0x40    /* 2 bytes */
  345 #define  OSIOP_DMODE_BL1        0x00    /* 1 byte */
  346 #define OSIOP_DMODE_FC          0x30    /* Function code */
  347 #define OSIOP_DMODE_PD          0x08    /* Program/data */
  348 #define OSIOP_DMODE_FAM         0x04    /* fixed address mode */
  349 #define OSIOP_DMODE_U0          0x02    /* User programmable transfer type */
  350 #define OSIOP_DMODE_MAN         0x01    /* SCRIPTS in Manual start mode */
  351 
  352 /* DMA interrupt enable register (dien) */
  353 
  354 #define OSIOP_DIEN_RES          0xc0
  355 #define OSIOP_DIEN_BF           0x20    /* On Bus Fault */
  356 #define OSIOP_DIEN_ABRT         0x10    /* On Abort */
  357 #define OSIOP_DIEN_SSI          0x08    /* On SCRIPTS sstep */
  358 #define OSIOP_DIEN_SIR          0x04    /* On SCRIPTS intr instruction */
  359 #define OSIOP_DIEN_WTD          0x02    /* On watchdog timeout */
  360 #define OSIOP_DIEN_IID          0x01    /* On illegal instruction detected */
  361 
  362 /* DMA control register (dcntl) */
  363 
  364 #define OSIOP_DCNTL_CF_MASK     0xc0    /* Clock frequency dividers: */
  365 #define  OSIOP_DCNTL_CF_2       0x00    /*  0 --> 37.51..50.00 MHz, div=2 */
  366 #define  OSIOP_DCNTL_CF_1_5     0x40    /*  1 --> 25.01..37.50 MHz, div=1.5 */
  367 #define  OSIOP_DCNTL_CF_1       0x80    /*  2 --> 16.67..25.00 MHz, div=1 */
  368 #define  OSIOP_DCNTL_CF_3       0xc0    /*  3 --> 50.01..66.67 MHz, div=3 */
  369 #define OSIOP_DCNTL_EA          0x20    /* Enable ACK */
  370 #define OSIOP_DCNTL_SSM         0x10    /* Single step mode */
  371 #define OSIOP_DCNTL_LLM         0x08    /* Enable SCSI Low-level mode */
  372 #define OSIOP_DCNTL_STD         0x04    /* Start DMA operation */
  373 #define OSIOP_DCNTL_FA          0x02    /* Fast arbitration */
  374 #define OSIOP_DCNTL_COM         0x01    /* 53C700 Compatibility */

Cache object: f8e7471b15bb4074df8266d3103d3c82


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