The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/quicc.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2006 Juniper Networks
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  *
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   27  *
   28  * $FreeBSD: releng/12.0/sys/dev/ic/quicc.h 326255 2017-11-27 14:52:40Z pfg $
   29  */
   30 
   31 #ifndef _DEV_IC_QUICC_H_
   32 #define _DEV_IC_QUICC_H_
   33 
   34 /*
   35  * Device parameter RAM
   36  */
   37 #define QUICC_PRAM_BASE         0x8000
   38 
   39 #define QUICC_PRAM_REV_NUM      (QUICC_PRAM_BASE + 0xaf0)
   40 
   41 /* SCC parameter RAM. */
   42 #define QUICC_PRAM_SIZE_SCC     256
   43 #define QUICC_PRAM_BASE_SCC(u)  (QUICC_PRAM_BASE + QUICC_PRAM_SIZE_SCC * (u))
   44 
   45 /* SCC parameters that are common for all modes. */
   46 #define QUICC_PRAM_SCC_RBASE(u) (QUICC_PRAM_BASE_SCC(u) + 0x00)
   47 #define QUICC_PRAM_SCC_TBASE(u) (QUICC_PRAM_BASE_SCC(u) + 0x02)
   48 #define QUICC_PRAM_SCC_RFCR(u)  (QUICC_PRAM_BASE_SCC(u) + 0x04)
   49 #define QUICC_PRAM_SCC_TFCR(u)  (QUICC_PRAM_BASE_SCC(u) + 0x05)
   50 #define QUICC_PRAM_SCC_MRBLR(u) (QUICC_PRAM_BASE_SCC(u) + 0x06)
   51 #define QUICC_PRAM_SCC_RBPTR(u) (QUICC_PRAM_BASE_SCC(u) + 0x10)
   52 #define QUICC_PRAM_SCC_TBPTR(u) (QUICC_PRAM_BASE_SCC(u) + 0x20)
   53 
   54 /*
   55  * SCC parameters that are specific to UART/ASYNC mode.
   56  */
   57 #define QUICC_PRAM_SIZE_SCC_UART        0x68    /* Rounded up. */
   58 
   59 #define QUICC_PRAM_SCC_UART_MAX_IDL(u)  (QUICC_PRAM_BASE_SCC(u) + 0x38)
   60 #define QUICC_PRAM_SCC_UART_IDLC(u)     (QUICC_PRAM_BASE_SCC(u) + 0x3a)
   61 #define QUICC_PRAM_SCC_UART_BRKCR(u)    (QUICC_PRAM_BASE_SCC(u) + 0x3c)
   62 #define QUICC_PRAM_SCC_UART_PAREC(u)    (QUICC_PRAM_BASE_SCC(u) + 0x3e)
   63 #define QUICC_PRAM_SCC_UART_FRMEC(u)    (QUICC_PRAM_BASE_SCC(u) + 0x40)
   64 #define QUICC_PRAM_SCC_UART_NOSEC(u)    (QUICC_PRAM_BASE_SCC(u) + 0x42)
   65 #define QUICC_PRAM_SCC_UART_BRKEC(u)    (QUICC_PRAM_BASE_SCC(u) + 0x44)
   66 #define QUICC_PRAM_SCC_UART_BRKLN(u)    (QUICC_PRAM_BASE_SCC(u) + 0x46)
   67 #define QUICC_PRAM_SCC_UART_UADDR1(u)   (QUICC_PRAM_BASE_SCC(u) + 0x48)
   68 #define QUICC_PRAM_SCC_UART_UADDR2(u)   (QUICC_PRAM_BASE_SCC(u) + 0x4a)
   69 #define QUICC_PRAM_SCC_UART_TOSEQ(u)    (QUICC_PRAM_BASE_SCC(u) + 0x4e)
   70 #define QUICC_PRAM_SCC_UART_CC(u,n)     (QUICC_PRAM_BASE_SCC(u) + 0x50 + (n)*2)
   71 #define QUICC_PRAM_SCC_UART_RCCM(u)     (QUICC_PRAM_BASE_SCC(u) + 0x60)
   72 #define QUICC_PRAM_SCC_UART_RCCR(u)     (QUICC_PRAM_BASE_SCC(u) + 0x62)
   73 #define QUICC_PRAM_SCC_UART_RLBC(u)     (QUICC_PRAM_BASE_SCC(u) + 0x64)
   74 
   75 /*
   76  * Interrupt controller.
   77  */
   78 #define QUICC_REG_SICR          0x10c00
   79 #define QUICC_REG_SIVEC         0x10c04
   80 #define QUICC_REG_SIPNR_H       0x10c08
   81 #define QUICC_REG_SIPNR_L       0x10c0c
   82 #define QUICC_REG_SCPRR_H       0x10c14
   83 #define QUICC_REG_SCPRR_L       0x10c18
   84 #define QUICC_REG_SIMR_H        0x10c1c
   85 #define QUICC_REG_SIMR_L        0x10c20
   86 #define QUICC_REG_SIEXR         0x10c24
   87 
   88 /*
   89  * System clock control register.
   90  */
   91 #define QUICC_REG_SCCR          0x10c80
   92 
   93 /*
   94  * Baudrate generator registers.
   95  */
   96 #define QUICC_REG_BRG(u)        (0x119f0 + ((u) & 3) * 4 - ((u) & 4) * 0x100)
   97 
   98 /*
   99  * SCC registers.
  100  */
  101 #define QUICC_REG_SIZE_SCC      0x20
  102 #define QUICC_REG_BASE_SCC(u)   (0x11a00 + QUICC_REG_SIZE_SCC * (u))
  103 
  104 #define QUICC_REG_SCC_GSMR_L(u) (QUICC_REG_BASE_SCC(u) + 0x00)
  105 #define QUICC_REG_SCC_GSMR_H(u) (QUICC_REG_BASE_SCC(u) + 0x04)
  106 #define QUICC_REG_SCC_PSMR(u)   (QUICC_REG_BASE_SCC(u) + 0x08)
  107 #define QUICC_REG_SCC_TODR(u)   (QUICC_REG_BASE_SCC(u) + 0x0c)
  108 #define QUICC_REG_SCC_DSR(u)    (QUICC_REG_BASE_SCC(u) + 0x0e)
  109 #define QUICC_REG_SCC_SCCE(u)   (QUICC_REG_BASE_SCC(u) + 0x10)
  110 #define QUICC_REG_SCC_SCCM(u)   (QUICC_REG_BASE_SCC(u) + 0x14)
  111 #define QUICC_REG_SCC_SCCS(u)   (QUICC_REG_BASE_SCC(u) + 0x17)
  112 
  113 #endif /* _DEV_IC_QUICC_H_ */

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