The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/rf3000reg.h

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    1 /* $NetBSD: rf3000reg.h,v 1.5 2006/03/08 08:26:50 dyoung Exp $ */
    2 
    3 /*
    4  * Copyright (c) 2005 David Young.  All rights reserved.
    5  *
    6  * This code was written by David Young.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  * 3. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
   21  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
   22  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
   23  * PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL David
   24  * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
   25  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
   26  * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
   28  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
   29  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
   31  * OF SUCH DAMAGE.
   32  */
   33 
   34 #ifndef _DEV_IC_RF3000REG_H_
   35 #define _DEV_IC_RF3000REG_H_
   36 
   37 /*
   38  * Serial bus format for RF Microdevices RF3000 spread-spectrum
   39  * baseband modem.
   40  */
   41 #define RF3000_TWI_DATA_MASK    0xff
   42 #define RF3000_TWI_ADDR_MASK    0x7f
   43 #define RF3000_TWI_AI           0x80    /* auto-increment */
   44 
   45 /*
   46  * Registers for RFMD RF3000.
   47  */
   48 #define RF3000_CTL              0x01            /* modem control */
   49 #define         RF3000_CTL_MODE_MASK            __BITS(7, 4)
   50 #define         RF3000_CTL_MODE_1MBPS           0
   51 #define         RF3000_CTL_MODE_RSVD0           1
   52 #define         RF3000_CTL_MODE_2MBPS           2
   53 #define         RF3000_CTL_MODE_2MBPS_SHORT     3
   54 #define         RF3000_CTL_MODE_5MBPS           4
   55 #define         RF3000_CTL_MODE_5MBPS_SHORT     5
   56 #define         RF3000_CTL_MODE_11MBPS          6
   57 #define         RF3000_CTL_MODE_11MBPS_SHORT    7
   58 #define         RF3000_CTL_MODE_BPSK            8
   59 #define         RF3000_CTL_MODE_QPSK            9
   60 #define         RF3000_CTL_MODE_RSVD1           10
   61 #define         RF3000_CTL_MODE_RSVD2           11
   62 #define RF3000_RXSTAT           RF3000_CTL      /* RX status */
   63 #define         RF3000_RXSTAT_SHORTPRE          __BIT(3)/* 1: short preamble */
   64 #define         RF3000_RXSTAT_ACQ               __BIT(2)/* 1: acquired */
   65 #define         RF3000_RXSTAT_SFD               __BIT(1)/* 1: SFD detected */
   66 #define         RF3000_RXSTAT_CRC               __BIT(0)/* 1: CRC invalid */
   67 #define RF3000_CCACTL           0x02            /* CCA control */
   68 /* CCA mode */
   69 #define         RF3000_CCACTL_MODE_MASK         __BITS(7, 6)
   70 #define         RF3000_CCACTL_MODE_RSSIT        0       /* RSSI threshold */
   71 #define         RF3000_CCACTL_MODE_ACQ          1       /* acquisition */
   72 #define         RF3000_CCACTL_MODE_BOTH         2       /* threshold or acq. */
   73 /* RSSI threshold for CCA */
   74 #define         RF3000_CCACTL_RSSIT_MASK        __BITS(5, 0)
   75 #define RF3000_DIVCTL           0x03            /* diversity control */
   76 #define         RF3000_DIVCTL_ENABLE            __BIT(7)/* enable diversity */
   77 #define         RF3000_DIVCTL_ANTSEL            __BIT(6)/* if ENABLE = 0, set
   78                                                          * ANT SEL
   79                                                          */
   80 #define RF3000_RSSI             RF3000_DIVCTL   /* RSSI value */
   81 #define         RF3000_RSSI_MASK                __BITS(5, 0)
   82 #define RF3000_GAINCTL          0x11            /* TX variable gain control */
   83 #define         RF3000_GAINCTL_TXVGC_MASK       __BITS(7, 2)
   84 #define         RF3000_GAINCTL_SCRAMBLER        __BIT(1)
   85 #define RF3000_LOGAINCAL        0x14            /* low gain calibration */
   86 #define         RF3000_LOGAINCAL_CAL_MASK       __BITS(5, 0)
   87 #define RF3000_HIGAINCAL        0x15            /* high gain calibration */
   88 #define         RF3000_HIGAINCAL_CAL_MASK       __BITS(5, 0)
   89 #define         RF3000_HIGAINCAL_DSSSPAD        __BIT(6)/* 6dB gain pad for DSSS
   90                                                          * modes (meaning?)
   91                                                          */
   92 #define RF3000_OPTIONS1         0x1C            /* Options Register 1 */
   93 /* Saturation threshold is 4 + offset, where -3 <= offset <= 3.
   94  * SAT_THRESH is the absolute value, SAT_THRESH_SIGN is the sign.
   95  */
   96 #define         RF3000_OPTIONS1_SAT_THRESH_SIGN __BIT(7)
   97 #define         RF3000_OPTIONS1_SAT_THRESH      __BITS(6,5)
   98 #define         RF3000_OPTIONS1_ALTAGC          __BIT(4)/* 1: retrigger AGC
   99                                                          * algorithm on ADC
  100                                                          * saturation
  101                                                          */
  102 #define         RF3000_OPTIONS1_ALTBUS          __BIT(3)/* 1: enable alternate
  103                                                          * Tx/Rx data bus
  104                                                          * interface.
  105                                                          */
  106 #define         RF3000_OPTIONS1_RESERVED0_MASK  __BITS(2,0)/* 0 */
  107 
  108 #define RF3000_OPTIONS2         0x1D            /* Options Register 2 */
  109 /* 1: delay next AGC 2us instead of 1us after a 1->0 LNAGS-pin transition. */
  110 #define         RF3000_OPTIONS2_LNAGS_DELAY     __BIT(7)
  111 #define         RF3000_OPTIONS2_RESERVED0_MASK  __BITS(6,3)     /* 0 */
  112 /* Threshold for AGC re-trigger. 0: high count, 1: low count. */
  113 #define         RF3000_OPTIONS2_RTG_THRESH      __BIT(2)
  114 #define         RF3000_OPTIONS2_RESERVED1_MASK  __BITS(1,0)     /* 0 */
  115 
  116 #endif /* _DEV_IC_RF3000REG_H_ */

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