1 /* $NetBSD: rrunnerreg.h,v 1.8 2006/02/25 02:28:58 wiz Exp $ */
2
3 /*
4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code contributed to The NetBSD Foundation by Kevin M. Lahey
8 * of the Numerical Aerospace Simulation Facility, NASA Ames Research
9 * Center.
10 *
11 * Partially based on a HIPPI driver written by Essential Communications
12 * Corporation. Thanks to Jason Thorpe, Matt Jacob, and Fred Templin
13 * for invaluable advice and encouragement!
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. All advertising materials mentioning features or use of this software
24 * must display the following acknowledgement:
25 * This product includes software developed by the NetBSD
26 * Foundation, Inc. and its contributors.
27 * 4. Neither the name of The NetBSD Foundation nor the names of its
28 * contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
30 *
31 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
32 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
33 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
34 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
35 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
36 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
37 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
38 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
39 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
40 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
41 * POSSIBILITY OF SUCH DAMAGE.
42 */
43
44 /*
45 * Description of RoadRunner registers and hardware constructs.
46 *
47 * We're trying to support version 1 AND version 2 of the RunCode.
48 * The fields that changed for version 2 are prefixed with RR2_ instead
49 * of RR_. If version 1 disappears (it is currently deprecated),
50 * we can remove compatibility, but it seems a shame to lose functionality
51 * for no good reason.
52 */
53
54 /* PCI registers */
55
56 #define RR_PCI_BIST 0x0c /* Built-In Self Test */
57
58 /* General control registers */
59
60 #define RR_MISC_HOST_CTL 0x40 /* Misc. Host Control */
61 #define RR_MISC_LOCAL_CTL 0x44 /* Misc. Local Control */
62 #define RR_PROC_PC 0x48 /* i960 program counter */
63 #define RR_PROC_BREAKPT 0x4c /* set breakpoint on i960 */
64 #define RR_TIMER 0x54 /* clock */
65 #define RR_TIMER_REF 0x58 /* When this matches the TIMER, interrupt */
66 #define RR_PCI_STATE 0x5c /* misc configuration */
67 #define RR_MAIN_EVENT 0x60 /* main event register for i960 & RoadRunner */
68 #define RR_WINDOW_BASE 0x68 /* pointer to internal memory*/
69 #define RR_WINDOW_DATA 0x6c /* value of mem at WINDOW_BASE */
70 #define RR_RX_STATE 0x70 /* HIPPI receiver state */
71 #define RR_TX_STATE 0x74 /* HIPPI transmitter state */
72 #define RR_EXT_SER_DATA 0x7c /* controls hardware besides RR on board */
73
74 /* Host DMA registers */
75
76 #define RR_WRITE_HOST 0x80 /* 64-bit pointer to data on host */
77 #define RR_READ_HOST 0x90
78 #define RR_WRITE_LENGTH 0x9c /* length of data to be moved */
79 #define RR_READ_LENGTH 0xac
80 #define RR_DMA_WRITE_STATE 0xa0 /* controls DMA */
81 #define RR_DMA_READ_STATE 0xb0
82 #define RR_WRITE_DST 0xa4 /* Internal destination of DMA */
83 #define RR_READ_DST 0xb4
84
85 /* RunCode registers */
86
87 #define RR_EVENT_CONSUMER 0x200 /* index of consumer in event ring */
88 #define RR_SEND_PRODUCER 0x218 /* index of producer in sender ring */
89 #define RR_SNAP_RECV_PRODUCER 0x21c /* index of producer in SNAP ring */
90 #define RR_RECVS_PRODUCER 0x220 /* index of producer in recv rings */
91 #define RR_COMMAND_RING 0x240 /* set of 16 command ring elements */
92
93 #define RR_ULA 0x280 /* Universal LAN Address */
94 #define RR_RECV_RING_PTR 0x288 /* receive ring address */
95 #define RR_GEN_INFO_PTR 0x290 /* general info block address */
96 #define RR_MODE_AND_STATUS 0x298 /* operating mode and status */
97 #define RR_CONN_RETRY_COUNT 0x29c /* when no campon, try count */
98 #define RR_CONN_RETRY_TIMER 0x2a0 /* clock ticks to delay retry */
99 #define RR_CONN_TIMEOUT 0x2a4 /* campon delay timeout */
100 #define RR_STATS_TIMER 0x2a8 /* clock ticks between stats copy */
101 #define RR_MAX_RECV_RINGS 0x2ac /* max receive rings (RO) */
102 #define RR_INTERRUPT_TIMER 0x2b0 /* clock ticks between interrupts */
103 #define RR_TX_TIMEOUT 0x2b4 /* transmit data not moving timer */
104 #define RR_RX_TIMEOUT 0x2b8 /* receive data not moving timer */
105 #define RR_EVENT_PRODUCER 0x2bc /* index of producer in event ring */
106 #define RR_TRACE_INDEX 0x2c0 /* RunCode trace pointer */
107 #define RR_RUNCODE_FAIL1 0x2c4 /* failure codes */
108 #define RR_RUNCODE_FAIL2 0x2c8
109 #define RR_FILTER_LA 0x2d0 /* internal debug, filtering */
110 #define RR_RUNCODE_VERSION 0x2d4 /* RunCode version data */
111
112 #define RR_RUNCODE_RECV_CONS 0x300 /* Runcode receive ring consumption */
113 #define RR_DRIVER_RECV_CONS 0x320 /* Driver receive ring consumption */
114
115 #define RR_MEMORY_WINDOW 0x800 /* Memory window */
116
117
118 /*
119 * Event codes
120 */
121
122 /* General events */
123
124 #define RR_EC_RUNCODE_UP 0x01
125 #define RR_EC_WATCHDOG 0x02
126 #define RR_EC_TRACE 0x03
127 #define RR_EC_STATS_RETRIEVED 0x04
128 #define RR_EC_INVALID_CMD 0x05
129 #define RR_EC_SET_CMD_CONSUMER 0x06
130 #define RR_EC_LINK_ON 0x07
131 #define RR_EC_LINK_OFF 0x08
132 #define RR2_EC_INTERNAL_ERROR 0x09
133 #define RR_EC_INTERNAL_ERROR 0x0a
134 #define RR2_EC_SOFTWARE_ERROR 0x0a
135 #define RR_EC_STATS_UPDATE 0x0b
136 #define RR_EC_REJECTING 0x0c
137
138 /* Send events */
139
140 #define RR_EC_SET_SND_CONSUMER 0x10
141 #define RR_EC_PACKET_SENT 0x11
142 #define RR_EC_SEND_RING_LOW 0x12
143 #define RR_EC_CONN_REJECT 0x13
144 #define RR_EC_CAMPON_TIMEOUT 0x14
145 #define RR_EC_CONN_TIMEOUT 0x15
146 #define RR_EC_DISCONN_ERR 0x16
147 #define RR_EC_INTERNAL_PARITY 0x17
148 #define RR_EC_TX_IDLE 0x18
149 #define RR_EC_SEND_LINK_OFF 0x19
150 #define RR_EC_BAD_SEND_RING 0x1a
151 #define RR_EC_BAD_SEND_BUF 0x1b
152 #define RR_EC_BAD_SEND_DESC 0x1c
153
154 /* Receive events */
155
156 #define RR_EC_RING_ENABLED 0x20
157 #define RR_EC_RING_ENABLE_ERR 0x21
158 #define RR_EC_RING_DISABLED 0x22
159 #define RR_EC_RECV_RING_LOW 0x23
160 #define RR_EC_RECV_RING_OUT 0x24
161 #define RR_EC_PACKET_DISCARDED 0x25
162 #define RR_EC_RECV_RING_FLUSH 0x26
163 #define RR_EC_RECV_ERROR_INFO 0x27
164 #define RR_EC_SET_RECV_CONSUMER 0x29
165 #define RR_EC_PACKET_RECVED 0x2a
166 #define RR_EC_PARITY_ERR 0x2b
167 #define RR_EC_LLRC_ERR 0x2c
168 #define RR_EC_IP_HDR_CKSUM_ERR 0x2d
169 #define RR_EC_DATA_CKSUM_ERR 0x2e
170 #define RR_EC_SHORT_BURST_ERR 0x2f
171 #define RR_EC_RECV_LINK_OFF 0x30
172 #define RR_EC_FLAG_SYNC_ERR 0x31
173 #define RR_EC_FRAME_ERR 0x32
174 #define RR_EC_RECV_IDLE 0x33
175 #define RR_EC_PKT_LENGTH_ERR 0x34
176 #define RR_EC_STATE_TRANS_ERR 0x35
177 #define RR_EC_NO_READY_PULSE 0x3c
178 #define RR_EC_BAD_RECV_BUF 0x36
179 #define RR_EC_BAD_RECV_DESC 0x37
180 #define RR_EC_BAD_RECV_RING 0x38
181 #define RR_EC_NO_RING_FOR_ULP 0x3a
182 #define RR_EC_OUT_OF_BUF 0x3b
183 #define RR_EC_UNIMPLEMENTED 0x40
184
185
186 /*
187 * Command codes
188 */
189
190 #define RR_CC_START_RUNCODE 0x01
191 #define RR_CC_UPDATE_STATS 0x02
192 #define RR_CC_DISCONN_SRC 0x03
193 #define RR_CC_DISCONN_DST 0x04
194 #define RR_CC_WATCHDOG 0x05
195 #define RR_CC_TRACE 0x06
196 #define RR_CC_SET_SEND_PRODUCER 0x07
197 #define RR_CC_SET_RECV_PRODUCER 0x08
198 #define RR_CC_DISABLE_RING 0x09
199 #define RR_CC_ENABLE_RING 0x0a
200 #define RR_CC_DISCARD_PKT 0x0b
201 #define RR_CC_FLUSH_RECV_RING 0x0c /* unimplemented */
202 #define RR_CC_CONN_MGT 0x0d
203
204
205 /*
206 * Masks for registers
207 */
208
209 /* Misc Host Control */
210
211 #define RR_MH_INTERRUPT 0x001 /* interrupt state */
212 #define RR_MH_CLEAR_INT 0x002 /* clear interrupt */
213 #define RR_MH_NO_SWAP 0x004 /* disable normal endian swap to host */
214 #define RR_MH_HALT_PROC 0x010 /* set to halt processor, clear to start */
215 #define RR_MH_STEP 0x020 /* set to single step processor */
216 #define RR_MH_PROC_HALT 0x100 /* indicates processor has been halted */
217 #define RR_MH_BAD_INSTR 0x200 /* indicates invalid instruction executed */
218
219 #define RR_MH_REVISION_MASK 0xf0000000 /* mask to retrieve revision code */
220
221 /* Misc Local Control */
222
223 #define RR_LC_CLEAR_INT 0x0002 /* clear interrupt */
224 #define RR_LC_FAST_PROM 0x0008 /* use fast EEPROM access */
225 #define RR_LC_ADD_SRAM 0x0100 /* > 1MB SRAM present */
226 #define RR_LC_ADD_HIPPI 0x0200 /* double number of HIPPI descriptors */
227 #define RR_LC_PARITY_ON 0x0400 /* enable local parity checking */
228 #define RR_LC_WRITE_PROM 0x1000 /* EEPROM write enable */
229
230 /* PCI State */
231
232 #define RR_PS_READ_MASK 0x1c
233 #define RR_PS_READ_SHIFT 2
234 #define RR_PS_READ_DISABLE (0 << RR_PS_READ_SHIFT)
235 #define RR_PS_READ_4 (1 << RR_PS_READ_SHIFT)
236 #define RR_PS_READ_16 (2 << RR_PS_READ_SHIFT)
237 #define RR_PS_READ_32 (3 << RR_PS_READ_SHIFT)
238 #define RR_PS_READ_64 (4 << RR_PS_READ_SHIFT)
239 #define RR_PS_READ_128 (5 << RR_PS_READ_SHIFT)
240 #define RR_PS_READ_256 (6 << RR_PS_READ_SHIFT)
241 #define RR_PS_READ_1024 (7 << RR_PS_READ_SHIFT)
242
243 #define RR_PS_WRITE_MASK 0xe0
244 #define RR_PS_WRITE_SHIFT 5
245 #define RR_PS_WRITE_DISABLE (0 << RR_PS_WRITE_SHIFT)
246 #define RR_PS_WRITE_4 (1 << RR_PS_WRITE_SHIFT)
247 #define RR_PS_WRITE_16 (2 << RR_PS_WRITE_SHIFT)
248 #define RR_PS_WRITE_32 (3 << RR_PS_WRITE_SHIFT)
249 #define RR_PS_WRITE_64 (4 << RR_PS_WRITE_SHIFT)
250 #define RR_PS_WRITE_128 (5 << RR_PS_WRITE_SHIFT)
251 #define RR_PS_WRITE_256 (6 << RR_PS_WRITE_SHIFT)
252 #define RR_PS_WRITE_1024 (7 << RR_PS_WRITE_SHIFT)
253 #define RR_PS_MIN_DMA_MASK 0xff00
254 #define RR_PS_MIN_DMA_SHIFT 8
255
256 /* HIPPI Receive State */
257
258 #define RR_RS_ENABLE 0x01 /* enable new connections */
259 #define RR_RS_RESET 0x02 /* reset receive interface */
260 #define RR_RS_REJECT_NONE 0x00 /* don't ever reject connections */
261 #define RR_RS_REJECT_2K 0x20 /* reject if only 2KB free */
262 #define RR_RS_REJECT_4K 0x30 /* reject if only 4KB free */
263 #define RR_RS_REJECT_8K 0x40 /* reject if only 8KB free */
264 #define RR_RS_REJECT_16K 0x50 /* reject if only 16KB free */
265 #define RR_RS_REJECT_32K 0x60 /* reject if only 32KB free */
266 #define RR_RS_REJECT_64K 0x70 /* reject if only 64KB free */
267
268 /* HIPPI Transmit State */
269
270 #define RR_TS_ENABLE 0x01 /* enable transmit state machine */
271 #define RR_TS_PERMANENT 0x02 /* this connection permanent while set */
272
273 /* External Serial Data */
274
275 /*
276 * This controls hardware that is external to the RoadRunner.
277 * Bits 0-15 are set on write, 16-31 are read on read.
278 */
279
280 #define RR_ES_TDAV 0x004 /* transmit data available */
281 #define RR_ES_LED1 0x008 /* LED1 control */
282 #define RR_ES_LED2 0x010 /* LED2 control */
283 #define RR_ES_RX_PERM 0x020 /* set permanent receive connection */
284 #define RR_ES_LEDAUTO 0x040 /* clear to let LED1 and LED2 control LEDs */
285 #define RR_ES_LLB_ENA 0x080 /* local loopback enable */
286 #define RR_ES_TP_START 0x100 /* test points (bits 8-13) */
287
288 #define RR_ES_REGINT 0x10000 /* interrupt from SEEQ-8100 (Gig-E) */
289 #define RR_ES_MISC 0x20000 /* misc input */
290 #define RR_ES_RXSIGDET 0x40000 /* fiber optic RXSIGDET output */
291
292 /* DMA Read State */
293
294 #define RR_DR_RESET 0x001 /* set to reset read DMA */
295 #define RR_DR_ACTIVE 0x008 /* set to start DMA */
296 #define RR_DR_THRESHOLD_MASK 0x1f0 /* mask off threshold values */
297 #define RR_DR_THRESHOLD_SHIFT 4 /* shift to set threshold values */
298 #define RR_DR_THRESHOLD_MAX 16
299
300 /* DMA Write State */
301
302 #define RR_DW_RESET 0x001 /* set to reset write DMA */
303 #define RR_DW_CKSUM 0x004 /* set to enable checksum calc on DMA */
304 #define RR_DW_ACTIVE 0x008 /* set to start DMA */
305 #define RR_DW_THRESHOLD_MASK 0x1f0 /* mask off threshold values */
306 #define RR_DW_THRESHOLD_SHIFT 4 /* shift to set threshold values */
307 #define RR_DW_THRESHOLD_MAX 18
308
309
310 /* Operating Mode and Status */
311
312 #define RR_MS_LOOPBACK 0x0001 /* loopback through the GLink hardware */
313 #define RR_MS_PH_MODE 0x0002 /* set for PH, clear for FP */
314 #define RR_MS_LONG_PTRS 0x0004 /* set indicates 64-bit pointers */
315 #define RR_MS_WORD_SWAP 0x0008 /* set to swap words in 64-bit pointers */
316 #define RR_MS_WARNINGS 0x0010 /* set to enable warning events */
317 #define RR_MS_ERR_TERM 0x0020 /* set to terminate connection on error */
318 #define RR_MS_DIRECT 0x0040 /* debug flag. enable filterLA checks */
319 #define RR_MS_NO_WATCHDOG 0x0080 /* set to disable watchdog */
320 #define RR_MS_SWAP_DATA 0x0100 /* set to byte swap data */
321 #define RR_MS_SWAP_CNTRL 0x0200 /* set to byte swap control structures */
322 #define RR_MS_ERR_HALT 0x0400 /* set to halt NIC on RunCode error */
323 #define RR_MS_NO_RESTART 0x0800 /* set to prevent NIC restart after error */
324 #define RR_MS_TX_HALFDUP 0x1000 /* NIC does half-duplex transmit */
325 #define RR_MS_RX_HALFDUP 0x2000 /* NIC does half-duplex receive */
326 #define RR_MS_GIG_E 0x4000 /* NIC does Gig-E instead of HIPPI */
327
328 #define RR_MS_FATAL_ERR 0x4000000 /* fatal error on NIC */
329 #define RR_MS_EVENT_OVER 0x8000000 /* event ring overflow */
330
331 /* Options field (top half of high word of ULA in RunCode) */
332
333 #define RR_OP_GIGE 0x01 /* Support for Gig-E NIC */
334 #define RR_OP_TRACED 0x02 /* Runcode generates debug traces */
335 #define RR_OP_1MEG 0x04 /* Support for 1MB of SRAM */
336 #define RR_OP_CDI 0x08 /* Support for Character Device Interace */
337 #define RR_OP_MSDOS 0x10 /* For testing RunCode under MS-DOS!? */
338 #define RR_OP_COMEV 0x20 /* New v2 Command/Event interface */
339 #define RR_OP_LONG_TX 0x40 /* Long transmit descr */
340 #define RR_OP_LONG_RX 0x80 /* Long receive descr (set when not CDI) */
341
342 /*
343 * EEPROM locations
344 *
345 * The EEPROM layout is a little weird. There is a valid byte every
346 * eight bytes. Words are then smeared out over 32 bytes.
347 * All addresses listed here are the actual starting addresses.
348 * The programmer is responsible for assembling a word from each of the
349 * bytes available.
350 *
351 * NB: This is incomplete. I just ran out of patience for entering values.
352 */
353
354 #define RR_EE_OFFSET 0x80000000 /* offset to the start of EEPROM mem */
355 #define RR_EE_WORD_LEN 0x20 /* jump between words in the EEPROM */
356 #define RR_EE_BYTE_LEN 0x08 /* jump between bytes in the EEPROM */
357 #define RR_EE_MAX_LEN 8192 /* maximum number of words in EEPROM */
358 #define RR_EE_SEG_SIZE 512 /* maximum size of a segment */
359
360 #define RR_EE_PROM_INIT 0x801ff00 /* jump here to start RunCode loader */
361
362 #define RR_EE_HEADER_FORMAT_MAGIC 1 /* version number we can handle*/
363
364 #define RR_EE_SRAM_SIZE 0x0040 /* SRAM size */
365 #define RR_EE_PHASE1_START 0x0060 /* target byte address in SRAM */
366 #define RR_EE_PHASE1_LEN 0x0080 /* length in words of phase 1 */
367 #define RR_EE_PHASE1_EE_START 0x00a0 /* address of phase 1 in EEPROM */
368
369 #define RR_EE_PCI_DEV_VEND 0x0100 /* PCI device/vendor */
370 #define RR_EE_PCI_REV_CLASS 0x0120 /* PCI revision/class */
371 #define RR_EE_PCI_LATENCY 0x0140 /* PCI latency timer */
372 #define RR_EE_PCI_BAR0 0x0160 /* PCI bar0 address */
373 #define RR_EE_PCI_COMM_STAT 0x0180 /* PCI command/status */
374 #define RR_EE_PCI_LAT_GNT 0x01a0 /* PCI max latency/ minimum grant */
375 #define RR_EE_PCI_CHECKSUM 0x01f0 /* PCI area checksum */
376
377 #define RR_EE_HEADER_FORMAT 0x0200 /* revision of header format
378 (should be 1) */
379 #define RR_EE_ULA_HI 0x0500 /* Universal LAN Address (ULA) */
380 #define RR_EE_ULA_LO 0x0520
381
382 #define RR_EE_RUNCODE_START 0x0a00 /* runcode start PC */
383 #define RR_EE_RUNCODE_VERSION 0x0a20 /* runcode revision number */
384 #define RR_EE_RUNCODE_DATE 0x0a40 /* runcode revision date */
385 #define RR_EE_RUNCODE_SEGMENTS 0x0a80 /* address of count of segments */
386
387 #define RR_EE_MODE_AND_STATUS 0x0e00 /* mode and status saved value */
388 #define RR_EE_CONN_RETRY_COUNT 0x0e20 /* connection retry count */
389 #define RR_EE_CONN_RETRY_TIMER 0x0e40 /* clock ticks to delay retry */
390 #define RR_EE_CONN_TIMEOUT 0x0e60 /* campon delay timeout */
391 #define RR_EE_STATS_TIMER 0x0e80 /* clock ticks between stats copy */
392 #define RR_EE_INTERRUPT_TIMER 0x0ea0 /* clock ticks between interrupts */
393 #define RR_EE_TX_TIMEOUT 0x0ec0 /* transmit data not moving timer */
394 #define RR_EE_RX_TIMEOUT 0x0ee0 /* receive data not moving timer */
395
396 #define RR_EE_PCI_STATE 0x0f00 /* misc PCI DMA config */
397 #define RR_EE_DMA_WRITE_STATE 0x0f20 /* dma write config */
398 #define RR_EE_DMA_READ_STATE 0x0f40 /* dma read config */
399 #define RR_EE_DRIVER_PARAM 0x0f60 /* driver-specific params (unused) */
400
401 #define RR_EE_HEADER_CHECKSUM 0x0fe0 /* checksum for manufacturing header
402 (0x200 - 0xfc0) */
403
404 #define RR_EE_PHASE2_START 0x1040 /* phase 2 start in SRAM */
405 #define RR_EE_PHASE2_LENGTH 0x1060 /* phase 2 length in words */
406 #define RR_EE_PHASE2_EE_START 0x1080 /* phase 2 EEPROM start */
407
408 /*
409 * Event descriptor
410 */
411
412 struct rr_event {
413 u_int16_t re_index; /* merge? Different event types? */
414 u_int8_t re_ring;
415 u_int8_t re_code;
416 u_int32_t re_timestamp;
417 };
418
419 /*
420 * Command descriptor
421 */
422
423 union rr_cmd {
424 struct {
425 u_int16_t rc_index;
426 u_int8_t rc_ring;
427 u_int8_t rc_code;
428 } b;
429 u_int32_t l;
430 };
431
432 /*
433 * Scatter/gather descriptor -- points to buffers to be DMA'ed in and
434 * out of host space.
435 */
436
437 struct rr_descr {
438 u_int32_t rd_reserved1;
439 u_int32_t rd_buffer_addr;
440 u_int32_t rd_reserved2;
441 u_int16_t rd_length;
442 u_int8_t rd_ring;
443 u_int8_t rd_control;
444 #define RR_CT_TX_IPCKSUM 0x04
445 #define RR_CT_PACKET_END 0x08
446 #define RR_CT_PACKET_START 0x10
447 #define RR_CT_INTERRUPT 0x20
448 #define RR_CT_SHORT_BURST 0x40
449 #define RR_CT_SAME_IFIELD 0x80
450 };
451
452 /*
453 * Long scatter/gather descriptor -- similar to above descriptor,
454 * but closer to RR's Assist register layout, so that it can just
455 * be DMA'ed into the NIC, and let loose. Required by Runcode v. 2
456 * and greater.
457 */
458
459 struct rr2_descr {
460 u_int32_t rd_reserved1;
461 u_int32_t rd_buffer_addr;
462 u_int32_t rd_reserved2;
463 u_int16_t rd_length;
464 u_int8_t rd_reserved3;
465 u_int8_t rd_control;
466 u_int32_t rd_dma_state;
467 #define RR_DM_TX 0x00606 /* swap code for dma_state on tx */
468 #define RR_DM_RX 0x20606 /* swap code for dma_state on rx */
469 u_int32_t rd_reserved4;
470 u_int32_t rd_pkt_length;
471 u_int32_t rd_reserved5;
472 #define RR2_CT_INTERRUPT 0x02
473 #define RR2_CT_TX_IPCKSUM 0x04
474 #define RR2_CT_PACKET_END 0x08
475 #define RR2_CT_PACKET_START 0x10
476 #define RR2_CT_RING_OUT 0x20
477 #define RR2_CT_SHORT_BURST 0x40
478 #define RR2_CT_SAME_IFIELD 0x80
479 };
480
481 /*
482 * Ring control structure -- points to array of buffer descriptors
483 */
484
485 struct rr_ring_ctl {
486 u_int32_t rr_reserved1;
487 u_int32_t rr_ring_addr; /* pointer to array of s/g descrs */
488 u_int16_t rr_entries;
489 u_int8_t rr_free_bufs;
490 #define RR_RR_DONT_COMPLAIN 0xff /* disable free_bufs warning */
491 u_int8_t rr_entry_size;
492 u_int16_t rr_prod_index;
493 u_int16_t rr_mode;
494 /* XXX: Picture in docs is right, description is wrong */
495 #define RR_RR_CHARACTER 0x01 /* character mode interface */
496 #define RR_RR_SEPARATE 0x02 /* separate headers from data */
497 #define RR_RR_CHECKSUM 0x04 /* doing IP checksums (requires IP on) */
498 #define RR_RR_IP 0x08 /* receiving IP packets to this ring */
499 };
500
501 /* Statistics block, for now, undifferentiated. */
502
503 struct rr_stats {
504 u_int32_t rs_stats[128];
505 };
506
507 /*
508 * General information block
509 */
510
511 struct rr_gen_info {
512 struct rr_stats ri_stats;
513 struct rr_ring_ctl ri_event_ring_ctl;
514 struct rr_ring_ctl ri_cmd_ring_ctl;
515 struct rr_ring_ctl ri_send_ring_ctl;
516 u_int8_t ri_reserved1[464];
517 u_int8_t ri_nic_trace[3072];
518 };
519
520 /*
521 * A few constants:
522 */
523
524 #define RR_DMA_BOUNDARY (64 * 1024) /* can't cross 64K boundaries on DMA */
525 #define RR_DMA_MAX 65535 /* maximum that can be transferred in
526 one DMA operation */
527 #define RR_ULP_COUNT 256 /* number of possible ULPs */
528 #define RR_INIT_CMD 15 /* initial command index */
529
530 /* NB: All of the ring sizes have to be powers of two */
531
532 #define RR_MAX_RECV_RING 32 /* maximum number of receive rings */
533 #define RR_MAX_DESCR 256 /* maximum number of possible
534 descriptors. XXX: increase
535 with caution, as this allocates
536 static space! */
537 #define RR_EVENT_RING_SIZE 128 /* why not go for it? */
538 #define RR_SEND_RING_SIZE 32 /* firmware restriction! */
539
540 #define RR_SNAP_RECV_RING_SIZE 32 /* seems to work */
541 #define RR_FP_RECV_RING_SIZE 32 /* seems to work */
542
543 #define RR2_SEND_RING_SIZE 16 /* firmware restriction! */
544 #define RR2_SNAP_RECV_RING_SIZE 16 /* firmware restriction! */
545
546 #define RR_MAX_SEND_RING_SIZE max(RR_SEND_RING_SIZE, RR2_SEND_RING_SIZE)
547 #define RR_MAX_SNAP_RECV_RING_SIZE \
548 max(RR_SNAP_RECV_RING_SIZE, RR_SNAP_RECV_RING_SIZE)
Cache object: 2eb31047bbc1aedc5510f51cec5ba666
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