The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/rs5c313reg.h

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    1 /*      $NetBSD: rs5c313reg.h,v 1.3 2010/04/06 15:29:19 nonaka Exp $    */
    2 
    3 /*-
    4  * Copyright (c) 2005 The NetBSD Foundation, Inc.
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  *
   16  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   17  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   18  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   19  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   20  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   21  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   26  * POSSIBILITY OF SUCH DAMAGE.
   27  */
   28 
   29 #ifndef _DEV_IC_RS5C313REG_H_
   30 #define _DEV_IC_RS5C313REG_H_
   31 
   32 /*
   33  * RICOH RS5C3[12]x Real Time Clock
   34  */
   35                                 /* 5c313/5c314 don't have bank1 */
   36 #define RS5C313_SEC1    0       /* bank0 */
   37 #define RS5C313_SEC10   1       /* bank0 */
   38 #define RS5C313_MIN1    2       /* bank0 */
   39 #define RS5C313_MIN10   3       /* bank0 */
   40 #define RS5C313_HOUR1   4       /* bank0 */
   41 #define RS5C313_HOUR10  5       /* bank0 */
   42 #define RS5C313_WDAY    6       /* bank0 */
   43 #define RS5C313_TINT    7       /* bank0/1 (5c313/5c314/5c316/5c317) */
   44 #define RS5C313_SCRATCH 7       /* bank0/1 (5c321) */
   45 #define RS5C313_DAY1    8       /* bank0 */
   46 #define RS5C313_DAY10   9       /* bank0 */
   47 #define RS5C313_MON1    10      /* bank0 */
   48 #define RS5C313_MON10   11      /* bank0 */
   49 #define RS5C313_YEAR1   12      /* bank0 */
   50 #define RS5C313_YEAR10  13      /* bank0 */
   51 #define RS5C313_CTRL    14      /* bank0/1 */
   52 #define RS5C313_CTRL2   15      /* bank0/1 */
   53 
   54 /* Alarm register (5c316/5c317) */
   55 #define RS5C313_AWOD1   0       /* bank1 */
   56 #define RS5C313_AWOD2   1       /* bank1 */
   57 #define RS5C313_AMIN1   2       /* bank1 */
   58 #define RS5C313_AMIN10  3       /* bank1 */
   59 #define RS5C313_AHOUR1  4       /* bank1 */
   60 #define RS5C313_AHOUR10 5       /* bank1 */
   61 
   62 /* Timer register (5c317) */
   63 #define RS5C313_TMR     9       /* bank1 */
   64 
   65 /* 32kHz control register (5c317/5c321) */
   66 #define RS5C313_32KHZ   10      /* bank1 */
   67 
   68 /* TINT register */
   69 #define TINT_CT0                0x01
   70 #define TINT_CT1                0x02
   71 #define TINT_CT2                0x04
   72 #define TINT_CT3                0x08
   73 
   74 /* CTRL register */
   75 #define CTRL_BSY                0x01    /* read */
   76 #define CTRL_ADJ                0x01    /* write */
   77 #define CTRL_XSTP               0x02    /* read */
   78 #define CTRL_WTEN               0x02    /* write */
   79 #define CTRL_24H                0x04    /* read/write (5c313/5c314) */
   80 #define CTRL_ALFG               0x04    /* read/write (5c316/5c317) */
   81 #define CTRL_CTFG               0x08    /* read/write */
   82 
   83 /* CTRL2 register */
   84 #define CTRL2_NTEST             0x01
   85 #define CTRL2_BANK              0x02    /* (5c316/5c317/5c321) */
   86 #define CTRL2_TMR               0x04    /* (5c317) */
   87 #define CTRL2_24H               0x08    /* (5c316/5c317/5c321) */
   88 
   89 #endif  /* _DEV_IC_RS5C313REG_H_ */

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