The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/rsa.h

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    1 /*-
    2  * Copyright (c) 1999 FreeBSD Inc.
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  *
   26  * $FreeBSD: releng/11.0/sys/dev/ic/rsa.h 77962 2001-06-10 04:28:39Z nyan $
   27  */
   28 
   29 /*
   30  * RSA Mode Driver Data Sheet
   31  *
   32  * <<Register Map>>
   33  * Base + 0x00
   34  * Mode Select Register(Read/Write)
   35  * bit4=interrupt type(1: level, 0: edge)
   36  * bit3=Auto RTS-CTS Flow Control Enable
   37  * bit2=External FIFO Enable
   38  * bit1=Reserved(Default 0)Don't Change!!
   39  * bit0=Swap Upper 8byte and Lower 8byte in 16byte space.
   40  *
   41  * Base + 0x01
   42  * Interrupt Enable Register(Read/Write)
   43  * bit4=Hardware Timer Interrupt Enable
   44  * bit3=Character Time-Out Interrupt Enable
   45  * bit2=Tx FIFO Empty Interrupt Enable
   46  * bit1=Tx FIFO Half Full Interrupt Enable
   47  * bit0=Rx FIFO Half Full Interrupt Enable
   48  *
   49  * Base + 0x02
   50  * Status Read Register(Read)
   51  * bit7=Hardware  Time Out Interrupt Status(1: True, 0: False)
   52  * bit6=Character Time Out Interrupt Status
   53  * bit5=Rx FIFO Full Flag(0: True, 1: False)
   54  * bit4=Rx FIFO Half Full Flag
   55  * bit3=Rx FIFO Empty Flag
   56  * bit2=Tx FIFO Full Flag
   57  * bit1=Tx FIFO Half Full Flag
   58  * bit0=Tx FIFO Empty Flag
   59  *
   60  * Base + 0x02
   61  * FIFO Reset Register(Write)
   62  * Reset Extrnal FIFO
   63  *
   64  * Base + 0x03
   65  * Timer Interval Value Set Register(Read/Write)
   66  * Range of n: 1-255
   67  * Interval Value: n * 0.2ms
   68  *
   69  * Base + 0x04
   70  * Timer Control Register(Read/Write)
   71  * bit0=Timer Enable
   72  *
   73  * Base + 0x08 - 0x0f
   74  * Same as UART 16550
   75  *
   76  * Special Regisgter in RSA Mode
   77  * UART Data Register(Base + 0x08)
   78  * Data transfer between Extrnal FIFO
   79  *
   80  * UART MCR(Base + 0x0c)
   81  * bit3(OUT2[MCR_IENABLE])=1: Diable 16550   to Rx FIFO transfer
   82  * bit2(OUT1[MCR_DRS])=1:     Diable Tx FIFO to 16550   transfer
   83  *
   84  * <<Intrrupt and Intrrupt Reset>>
   85  * o Reciver Line Status(from UART16550)
   86  *   Reset: Read LSR
   87  *
   88  * o Modem Status(from UART16550)
   89  *   Reset: Read MSR
   90  *
   91  * o Rx FIFO Half Full(from Extrnal FIFO)
   92  *   Reset: Read Rx FIFO under Hall Full 
   93  *
   94  * o Character Time Out(from Extrnal FIFO)
   95  *   Reset: Read Rx FIFO or SRR
   96  *
   97  * o Tx FIFO Empty(from Extrnal FIFO)
   98  *   Reset: Write Tx FIFO or Read SRR
   99  *
  100  * o Tx FIFO Half Full(from Extrnal FIFO)
  101  *   Reset: Write Tx FIFO until Hall Full or Read SRR
  102  * 
  103  * o Hardware Timer(from Extrnal FIFO)
  104  *   Reset: Disable Timer in TCR
  105  *   Notes: If you want to use Timer for next intrrupt,
  106  *          you must enable Timer in TCR
  107  *
  108  * <<Used Setting>>
  109  * Auto RTS-CTS:    Enable or Disable
  110  * External FIFO:   Enable
  111  * Swap 8bytes:     Disable
  112  * Haredware Timer: Disable
  113  * interrupt type:  edge
  114  * interrupt source:
  115  *           Hareware Timer
  116  *           Character Time Out
  117  *           Tx FIFO Empty
  118  *           Rx FIFO Half Full
  119  *
  120  */
  121 
  122 /* I/O-DATA RSA Serise Exrension Register */
  123 #define rsa_msr         0       /* Mode Status Register (R/W) */
  124 #define rsa_ier         1       /* Interrupt Enable Register (R/W) */
  125 #define rsa_srr         2       /* Status Read Register (R) */
  126 #define rsa_frr         2       /* FIFO Reset Register (W) */
  127 #define rsa_tivsr       3       /* Timer Interval Value Set Register (R/W) */
  128 #define rsa_tcr         4       /* Timer Control Register (W) */

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